X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86InstrInfo.td;h=53a82ba3802d23b0a58c9d764737fce334d238af;hb=16b04f3d5e2a602333a7f64d66e3b78bc1679110;hp=083a9365164f2a5fa06e99cb09db6ef7da118694;hpb=284b496aaeb959d382b2410e4bd21fb6e0c694bb;p=oota-llvm.git diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 083a9365164..53a82ba3802 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -13,6 +13,29 @@ // //===----------------------------------------------------------------------===// +// *mem - Operand definitions for the funky X86 addressing mode operands. +// + +class X86MemOperand : Operand { + let NumMIOperands = 4; + let PrintMethod = "printMemoryOperand"; +} +def SSECC : Operand { + let PrintMethod = "printSSECC"; +} + +def i8mem : X86MemOperand; +def i16mem : X86MemOperand; +def i32mem : X86MemOperand; +def i64mem : X86MemOperand; +def f32mem : X86MemOperand; +def f64mem : X86MemOperand; +def f80mem : X86MemOperand; + +// PCRelative calls need special operand formatting. +let PrintMethod = "printCallOperand" in + def calltarget : Operand; + // Format specifies the encoding used by the instruction. This is part of the // ad-hoc solution used to emit machine instruction encodings by our machine // code emitter. @@ -42,20 +65,6 @@ def Imm8 : ImmType<1>; def Imm16 : ImmType<2>; def Imm32 : ImmType<3>; -// MemType - This specifies the immediate type used by an instruction. This is -// part of the ad-hoc solution used to emit machine instruction encodings by our -// machine code emitter. -class MemType val> { - bits<3> Value = val; -} -def NoMem : MemType<0>; -def Mem8 : MemType<1>; -def Mem16 : MemType<2>; -def Mem32 : MemType<3>; -def Mem64 : MemType<4>; -def Mem80 : MemType<5>; -def Mem128 : MemType<6>; - // FPFormat - This specifies what form this FP instruction has. This is used by // the Floating-Point stackifier pass. class FPFormat val> { @@ -66,37 +75,29 @@ def ZeroArgFP : FPFormat<1>; def OneArgFP : FPFormat<2>; def OneArgFPRW : FPFormat<3>; def TwoArgFP : FPFormat<4>; -def CondMovFP : FPFormat<5>; -def SpecialFP : FPFormat<6>; +def CompareFP : FPFormat<5>; +def CondMovFP : FPFormat<6>; +def SpecialFP : FPFormat<7>; -class X86Inst opcod, Format f, MemType m, ImmType i> : Instruction { +class X86Inst opcod, Format f, ImmType i, dag ops, string AsmStr> + : Instruction { let Namespace = "X86"; - let Name = nam; bits<8> Opcode = opcod; Format Form = f; bits<5> FormBits = Form.Value; - MemType MemT = m; - bits<3> MemTypeBits = MemT.Value; ImmType ImmT = i; bits<2> ImmTypeBits = ImmT.Value; + dag OperandList = ops; + string AsmString = AsmStr; + // // Attributes specific to X86 instructions... // bit hasOpSizePrefix = 0; // Does this inst have a 0x66 prefix? - // Flag whether implicit register usage is printed before/after the - // instruction - bit printImplicitUsesBefore = 0; - bit printImplicitUsesAfter = 0; - - // Flag whether implicit register definitions are printed before/after the - // instruction - bit printImplicitDefsBefore = 0; - bit printImplicitDefsAfter = 0; - bits<4> Prefix = 0; // Which prefix byte does this inst have? FPFormat FPForm; // What flavor of FP instruction is this? bits<3> FPFormBits = 0; @@ -107,10 +108,6 @@ class Imp uses, list defs> { list Defs = defs; } -class Pattern { - dag Pattern = P; -} - // Prefix byte classes which are used to indicate to the ad-hoc machine code // emitter that various prefix bytes are required. @@ -125,75 +122,67 @@ class DC { bits<4> Prefix = 7; } class DD { bits<4> Prefix = 8; } class DE { bits<4> Prefix = 9; } class DF { bits<4> Prefix = 10; } +class XD { bits<4> Prefix = 11; } +class XS { bits<4> Prefix = 12; } //===----------------------------------------------------------------------===// // Instruction templates... -class I o, Format f> : X86Inst; - -class Im o, Format f, MemType m> : X86Inst; -class Im8 o, Format f> : Im; -class Im16 o, Format f> : Im; -class Im32 o, Format f> : Im; - -class Ii o, Format f, ImmType i> : X86Inst; -class Ii8 o, Format f> : Ii; -class Ii16 o, Format f> : Ii; -class Ii32 o, Format f> : Ii; - -class Im8i8 o, Format f> : X86Inst; -class Im16i16 o, Format f> : X86Inst; -class Im32i32 o, Format f> : X86Inst; - -class Im16i8 o, Format f> : X86Inst; -class Im32i8 o, Format f> : X86Inst; - -// Helper for shift instructions -class UsesCL { list Uses = [CL]; bit printImplicitUsesAfter = 1; } -class PrintImpUsesAfter {bit printImplicitUsesAfter = 1;} -class PrintImpDefsAfter {bit printImplicitDefsAfter = 1;} +class I o, Format f, dag ops, string asm> + : X86Inst; +class Ii8 o, Format f, dag ops, string asm> + : X86Inst; +class Ii16 o, Format f, dag ops, string asm> + : X86Inst; +class Ii32 o, Format f, dag ops, string asm> + : X86Inst; //===----------------------------------------------------------------------===// // Instruction list... // -def PHI : I<"PHI", 0, Pseudo>; // PHI node... - -def NOOP : I<"nop", 0x90, RawFrm>; // nop +def PHI : I<0, Pseudo, (ops), "PHINODE">; // PHI node. +def NOOP : I<0x90, RawFrm, (ops), "nop">; // nop -def ADJCALLSTACKDOWN : I<"ADJCALLSTACKDOWN", 0, Pseudo>; -def ADJCALLSTACKUP : I<"ADJCALLSTACKUP", 0, Pseudo>; -def IMPLICIT_USE : I<"IMPLICIT_USE", 0, Pseudo>; -def IMPLICIT_DEF : I<"IMPLICIT_DEF", 0, Pseudo>; +def ADJCALLSTACKDOWN : I<0, Pseudo, (ops), "#ADJCALLSTACKDOWN">; +def ADJCALLSTACKUP : I<0, Pseudo, (ops), "#ADJCALLSTACKUP">; +def IMPLICIT_USE : I<0, Pseudo, (ops), "#IMPLICIT_USE">; +def IMPLICIT_DEF : I<0, Pseudo, (ops), "#IMPLICIT_DEF">; let isTerminator = 1 in let Defs = [FP0, FP1, FP2, FP3, FP4, FP5, FP6] in - def FP_REG_KILL : I<"FP_REG_KILL", 0, Pseudo>; + def FP_REG_KILL : I<0, Pseudo, (ops), "#FP_REG_KILL">; + //===----------------------------------------------------------------------===// // Control Flow Instructions... // -// Return instruction... -let isTerminator = 1, isReturn = 1 in - def RET : I<"ret", 0xC3, RawFrm>, Pattern<(retvoid)>; +// Return instructions. +let isTerminator = 1, isReturn = 1, isBarrier = 1 in + def RET : I<0xC3, RawFrm, (ops), "ret">; +let isTerminator = 1, isReturn = 1, isBarrier = 1 in + def RETI : Ii16<0xC2, RawFrm, (ops i16imm:$amt), "ret $amt">; // All branches are RawFrm, Void, Branch, and Terminators let isBranch = 1, isTerminator = 1 in - class IBr opcode> : I; - -def JMP : IBr<"jmp", 0xE9>, Pattern<(br basicblock)>; -def JB : IBr<"jb" , 0x82>, TB; -def JAE : IBr<"jae", 0x83>, TB; -def JE : IBr<"je" , 0x84>, TB, Pattern<(isVoid (unspec1 basicblock))>; -def JNE : IBr<"jne", 0x85>, TB; -def JBE : IBr<"jbe", 0x86>, TB; -def JA : IBr<"ja" , 0x87>, TB; -def JS : IBr<"js" , 0x88>, TB; -def JNS : IBr<"jns", 0x89>, TB; -def JL : IBr<"jl" , 0x8C>, TB; -def JGE : IBr<"jge", 0x8D>, TB; -def JLE : IBr<"jle", 0x8E>, TB; -def JG : IBr<"jg" , 0x8F>, TB; + class IBr opcode, dag ops, string asm> : I; + +let isBarrier = 1 in + def JMP : IBr<0xE9, (ops i32imm:$dst), "jmp $dst">; +def JB : IBr<0x82, (ops i32imm:$dst), "jb $dst">, TB; +def JAE : IBr<0x83, (ops i32imm:$dst), "jae $dst">, TB; +def JE : IBr<0x84, (ops i32imm:$dst), "je $dst">, TB; +def JNE : IBr<0x85, (ops i32imm:$dst), "jne $dst">, TB; +def JBE : IBr<0x86, (ops i32imm:$dst), "jbe $dst">, TB; +def JA : IBr<0x87, (ops i32imm:$dst), "ja $dst">, TB; +def JS : IBr<0x88, (ops i32imm:$dst), "js $dst">, TB; +def JNS : IBr<0x89, (ops i32imm:$dst), "jns $dst">, TB; +def JP : IBr<0x8A, (ops i32imm:$dst), "jp $dst">, TB; +def JNP : IBr<0x8B, (ops i32imm:$dst), "jnp $dst">, TB; +def JL : IBr<0x8C, (ops i32imm:$dst), "jl $dst">, TB; +def JGE : IBr<0x8D, (ops i32imm:$dst), "jge $dst">, TB; +def JLE : IBr<0x8E, (ops i32imm:$dst), "jle $dst">, TB; +def JG : IBr<0x8F, (ops i32imm:$dst), "jg $dst">, TB; //===----------------------------------------------------------------------===// @@ -201,116 +190,228 @@ def JG : IBr<"jg" , 0x8F>, TB; // let isCall = 1 in // All calls clobber the non-callee saved registers... - let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6] in { - def CALLpcrel32 : I <"call", 0xE8, RawFrm>; - def CALL32r : I <"call", 0xFF, MRM2r>; - def CALL32m : Im32<"call", 0xFF, MRM2m>; + let Defs = [EAX, ECX, EDX, FP0, FP1, FP2, FP3, FP4, FP5, FP6, ST0, + XMM0, XMM1, XMM2, XMM3, XMM4, XMM5, XMM6, XMM7] in { + def CALLpcrel32 : I<0xE8, RawFrm, (ops calltarget:$dst), "call $dst">; + def CALL32r : I<0xFF, MRM2r, (ops R32:$dst), "call {*}$dst">; + def CALL32m : I<0xFF, MRM2m, (ops i32mem:$dst), "call {*}$dst">; } - +// Tail call stuff. +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPd : IBr<0xE9, (ops calltarget:$dst), "jmp $dst # TAIL CALL">; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPr : I<0xFF, MRM4r, (ops R32:$dst), "jmp {*}$dst # TAIL CALL">; +let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in + def TAILJMPm : I<0xFF, MRM4m, (ops i32mem:$dst), "jmp {*}$dst # TAIL CALL">; + +// ADJSTACKPTRri - This is a standard ADD32ri instruction, identical in every +// way, except that it is marked as being a terminator. This causes the epilog +// inserter to insert reloads of callee saved registers BEFORE this. We need +// this until we have a more accurate way of tracking where the stack pointer is +// within a function. +let isTerminator = 1, isTwoAddress = 1 in + def ADJSTACKPTRri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; + //===----------------------------------------------------------------------===// // Miscellaneous Instructions... // -def LEAVE : I<"leave", 0xC9, RawFrm>, Imp<[EBP,ESP],[EBP,ESP]>; -def POP32r : I<"pop", 0x58, AddRegFrm>, Imp<[ESP],[ESP]>; - -let isTwoAddress = 1 in // R32 = bswap R32 - def BSWAP32r : I<"bswap", 0xC8, AddRegFrm>, TB; - -def XCHG8rr : I <"xchg", 0x86, MRMDestReg>; // xchg R8, R8 -def XCHG16rr : I <"xchg", 0x87, MRMDestReg>, OpSize; // xchg R16, R16 -def XCHG32rr : I <"xchg", 0x87, MRMDestReg>; // xchg R32, R32 -def XCHG8mr : Im8 <"xchg", 0x86, MRMDestMem>; // xchg [mem8], R8 -def XCHG16mr : Im16<"xchg", 0x87, MRMDestMem>, OpSize; // xchg [mem16], R16 -def XCHG32mr : Im32<"xchg", 0x87, MRMDestMem>; // xchg [mem32], R32 -def XCHG8rm : Im8 <"xchg", 0x86, MRMSrcMem >; // xchg R8, [mem8] -def XCHG16rm : Im16<"xchg", 0x87, MRMSrcMem >, OpSize; // xchg R16, [mem16] -def XCHG32rm : Im32<"xchg", 0x87, MRMSrcMem >; // xchg R32, [mem32] - -def LEA16r : Im32<"lea", 0x8D, MRMSrcMem>, OpSize; // R16 = lea [mem] -def LEA32r : Im32<"lea", 0x8D, MRMSrcMem>; // R32 = lea [mem] - - -def REP_MOVSB : I<"rep movsb", 0xA4, RawFrm>, REP, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; -def REP_MOVSW : I<"rep movsw", 0xA5, RawFrm>, REP, OpSize, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; -def REP_MOVSD : I<"rep movsd", 0xA5, RawFrm>, REP, - Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>; - -def REP_STOSB : I<"rep stosb", 0xAA, RawFrm>, REP, - Imp<[AL,ECX,EDI], [ECX,EDI]>; -def REP_STOSW : I<"rep stosw", 0xAB, RawFrm>, REP, OpSize, - Imp<[AX,ECX,EDI], [ECX,EDI]>; -def REP_STOSD : I<"rep stosd", 0xAB, RawFrm>, REP, - Imp<[EAX,ECX,EDI], [ECX,EDI]>; +def LEAVE : I<0xC9, RawFrm, + (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>; +def POP32r : I<0x58, AddRegFrm, + (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>; + +let isTwoAddress = 1 in // R32 = bswap R32 + def BSWAP32r : I<0xC8, AddRegFrm, + (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB; + +def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 + (ops R8:$src1, R8:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; +def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 + (ops R16:$src1, R16:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; +def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 + (ops R32:$src1, R32:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; + +def XCHG8mr : I<0x86, MRMDestMem, + (ops i8mem:$src1, R8:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; +def XCHG16mr : I<0x87, MRMDestMem, + (ops i16mem:$src1, R16:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; +def XCHG32mr : I<0x87, MRMDestMem, + (ops i32mem:$src1, R32:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; +def XCHG8rm : I<0x86, MRMSrcMem, + (ops R8:$src1, i8mem:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; +def XCHG16rm : I<0x87, MRMSrcMem, + (ops R16:$src1, i16mem:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; +def XCHG32rm : I<0x87, MRMSrcMem, + (ops R32:$src1, i32mem:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; + +def LEA16r : I<0x8D, MRMSrcMem, + (ops R16:$dst, i32mem:$src), + "lea{w} {$src|$dst}, {$dst|$src}">, OpSize; +def LEA32r : I<0x8D, MRMSrcMem, + (ops R32:$dst, i32mem:$src), + "lea{l} {$src|$dst}, {$dst|$src}">; + + +def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">, + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; +def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">, + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; +def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">, + Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; + +def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">, + Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; +def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">, + Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; +def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosl|rep stosd}">, + Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; + //===----------------------------------------------------------------------===// // Input/Output Instructions... // -def IN8 : I<"in", 0xEC, RawFrm>, Imp<[DX],[AL]>, PrintImpUsesAfter, PrintImpDefsAfter; // in AL = I/O address DX -def IN16 : I<"in", 0xED, RawFrm>, Imp<[DX],[AX]>, OpSize, PrintImpUsesAfter, PrintImpDefsAfter; // in AX = I/O address DX -def IN32 : I<"in", 0xED, RawFrm>, Imp<[DX],[EAX]>, PrintImpUsesAfter, PrintImpDefsAfter; // in EAX = I/O address DX - -def OUT8 : I<"out", 0xEE, RawFrm>, Imp<[DX, AL], []>, PrintImpUsesAfter; -def OUT16 : I<"out", 0xEF, RawFrm>, Imp<[DX, AX], []>, OpSize, PrintImpUsesAfter; -def OUT32 : I<"out", 0xEF, RawFrm>, Imp<[DX, EAX], []>, PrintImpUsesAfter; +def IN8rr : I<0xEC, RawFrm, (ops), + "in{b} {%dx, %al|%AL, %DX}">, Imp<[DX], [AL]>; +def IN16rr : I<0xED, RawFrm, (ops), + "in{w} {%dx, %ax|%AX, %DX}">, Imp<[DX], [AX]>, OpSize; +def IN32rr : I<0xED, RawFrm, (ops), + "in{l} {%dx, %eax|%EAX, %DX}">, Imp<[DX],[EAX]>; + +def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port), + "in{b} {$port, %al|%AL, $port}">, Imp<[], [AL]>; +def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), + "in{w} {$port, %ax|%AX, $port}">, Imp<[], [AX]>, OpSize; +def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), + "in{l} {$port, %eax|%EAX, $port}">, Imp<[],[EAX]>; + +def OUT8rr : I<0xEE, RawFrm, (ops), + "out{b} {%al, %dx|%DX, %AL}">, Imp<[DX, AL], []>; +def OUT16rr : I<0xEF, RawFrm, (ops), + "out{w} {%ax, %dx|%DX, %AX}">, Imp<[DX, AX], []>, OpSize; +def OUT32rr : I<0xEF, RawFrm, (ops), + "out{l} {%eax, %dx|%DX, %EAX}">, Imp<[DX, EAX], []>; + +def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port), + "out{b} {%al, $port|$port, %AL}">, Imp<[AL], []>; +def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), + "out{w} {%ax, $port|$port, %AX}">, Imp<[AX], []>, OpSize; +def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), + "out{l} {%eax, $port|$port, %EAX}">, Imp<[EAX], []>; //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I <"mov", 0x88, MRMDestReg>, Pattern<(set R8 , R8 )>; -def MOV16rr : I <"mov", 0x89, MRMDestReg>, OpSize, Pattern<(set R16, R16)>; -def MOV32rr : I <"mov", 0x89, MRMDestReg>, Pattern<(set R32, R32)>; -def MOV8ri : Ii8 <"mov", 0xB0, AddRegFrm >, Pattern<(set R8 , imm )>; -def MOV16ri : Ii16 <"mov", 0xB8, AddRegFrm >, OpSize, Pattern<(set R16, imm)>; -def MOV32ri : Ii32 <"mov", 0xB8, AddRegFrm >, Pattern<(set R32, imm)>; -def MOV8mi : Im8i8 <"mov", 0xC6, MRM0m >; // [mem8] = imm8 -def MOV16mi : Im16i16<"mov", 0xC7, MRM0m >, OpSize; // [mem16] = imm16 -def MOV32mi : Im32i32<"mov", 0xC7, MRM0m >; // [mem32] = imm32 - -def MOV8rm : Im8 <"mov", 0x8A, MRMSrcMem>; // R8 = [mem8] -def MOV16rm : Im16 <"mov", 0x8B, MRMSrcMem>, OpSize, // R16 = [mem16] - Pattern<(set R16, (load (plus R32, (plus (times imm, R32), imm))))>; -def MOV32rm : Im32 <"mov", 0x8B, MRMSrcMem>, // R32 = [mem32] - Pattern<(set R32, (load (plus R32, (plus (times imm, R32), imm))))>; - -def MOV8mr : Im8 <"mov", 0x88, MRMDestMem>; // [mem8] = R8 -def MOV16mr : Im16 <"mov", 0x89, MRMDestMem>, OpSize; // [mem16] = R16 -def MOV32mr : Im32 <"mov", 0x89, MRMDestMem>; // [mem32] = R32 - +def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), + "mov{l} {$src, $dst|$dst, $src}">; +def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), + "mov{l} {$src, $dst|$dst, $src}">; +def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), + "mov{l} {$src, $dst|$dst, $src}">; + +def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), + "mov{l} {$src, $dst|$dst, $src}">; + +def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), + "mov{l} {$src, $dst|$dst, $src}">; + //===----------------------------------------------------------------------===// // Fixed-Register Multiplication and Division Instructions... // // Extra precision multiplication -def MUL8r : I <"mul", 0xF6, MRM4r>, Imp<[AL],[AX]>; // AL,AH = AL*R8 -def MUL16r : I <"mul", 0xF7, MRM4r>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def MUL32r : I <"mul", 0xF7, MRM4r>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 -def MUL8m : Im8 <"mul", 0xF6, MRM4m>, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] -def MUL16m : Im16<"mul", 0xF7, MRM4m>, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] -def MUL32m : Im32<"mul", 0xF7, MRM4m>, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] +def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">, + Imp<[AL],[AX]>; // AL,AH = AL*R8 +def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">, + Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 +def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">, + Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 +def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), + "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] +def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), + "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] +def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), + "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] + +def IMUL8r : I<0xF6, MRM5r, (ops R8:$src), "imul{b} $src">, + Imp<[AL],[AX]>; // AL,AH = AL*R8 +def IMUL16r : I<0xF7, MRM5r, (ops R16:$src), "imul{w} $src">, + Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 +def IMUL32r : I<0xF7, MRM5r, (ops R32:$src), "imul{l} $src">, + Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 +def IMUL8m : I<0xF6, MRM5m, (ops i8mem :$src), + "imul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] +def IMUL16m : I<0xF7, MRM5m, (ops i16mem:$src), + "imul{w} $src">, Imp<[AX],[AX,DX]>, OpSize;// AX,DX = AX*[mem16] +def IMUL32m : I<0xF7, MRM5m, (ops i32mem:$src), + "imul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder -def DIV8r : I <"div", 0xF6, MRM6r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH -def DIV16r : I <"div", 0xF7, MRM6r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def DIV32r : I <"div", 0xF7, MRM6r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX -def DIV8m : Im8 <"div", 0xF6, MRM6m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH -def DIV16m : Im16<"div", 0xF7, MRM6m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX -def DIV32m : Im32<"div", 0xF7, MRM6m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX - -// signed division/remainder -def IDIV8r : I <"idiv",0xF6, MRM7r>, Imp<[AX],[AX]>; // AX/r8 = AL,AH -def IDIV16r: I <"idiv",0xF7, MRM7r>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def IDIV32r: I <"idiv",0xF7, MRM7r>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX -def IDIV8m : Im8 <"idiv",0xF6, MRM7m>, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH -def IDIV16m: Im16<"idiv",0xF7, MRM7m>, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX -def IDIV32m: Im32<"idiv",0xF7, MRM7m>, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX - -// Sign-extenders for division -def CBW : I<"cbw", 0x98, RawFrm >, Imp<[AL],[AH]>; // AX = signext(AL) -def CWD : I<"cwd", 0x99, RawFrm >, Imp<[AX],[DX]>; // DX:AX = signext(AX) -def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) +def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH + "div{b} $src">, Imp<[AX],[AX]>; +def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX + "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX + "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; +def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH + "div{b} $src">, Imp<[AX],[AX]>; +def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX + "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX + "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + +// Signed division/remainder. +def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH + "idiv{b} $src">, Imp<[AX],[AX]>; +def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX + "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX + "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; +def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH + "idiv{b} $src">, Imp<[AX],[AX]>; +def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX + "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX + "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; + +// Sign-extenders for division. +def CBW : I<0x98, RawFrm, (ops), + "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL) +def CWD : I<0x99, RawFrm, (ops), + "{cwtd|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX) +def CDQ : I<0x99, RawFrm, (ops), + "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) + //===----------------------------------------------------------------------===// // Two address Instructions... @@ -318,575 +419,1368 @@ def CDQ : I<"cdq", 0x99, RawFrm >, Imp<[EAX],[EDX]>; // EDX:EAX let isTwoAddress = 1 in { // Conditional moves -def CMOVB16rr : I <"cmovb", 0x42, MRMSrcReg>, TB, OpSize; // if , TB, OpSize; // if , TB; // if , TB; // if , TB, OpSize; // if >=u, R16 = R16 -def CMOVAE16rm: Im16<"cmovae", 0x43, MRMSrcMem>, TB, OpSize; // if >=u, R16 = [mem16] -def CMOVAE32rr: I <"cmovae", 0x43, MRMSrcReg>, TB; // if >=u, R32 = R32 -def CMOVAE32rm: Im32<"cmovae", 0x43, MRMSrcMem>, TB; // if >=u, R32 = [mem32] - -def CMOVE16rr : I <"cmove", 0x44, MRMSrcReg>, TB, OpSize; // if ==, R16 = R16 -def CMOVE16rm : Im16<"cmove", 0x44, MRMSrcMem>, TB, OpSize; // if ==, R16 = [mem16] -def CMOVE32rr : I <"cmove", 0x44, MRMSrcReg>, TB; // if ==, R32 = R32 -def CMOVE32rm : Im32<"cmove", 0x44, MRMSrcMem>, TB; // if ==, R32 = [mem32] - -def CMOVNE16rr: I <"cmovne",0x45, MRMSrcReg>, TB, OpSize; // if !=, R16 = R16 -def CMOVNE16rm: Im16<"cmovne",0x45, MRMSrcMem>, TB, OpSize; // if !=, R16 = [mem16] -def CMOVNE32rr: I <"cmovne",0x45, MRMSrcReg>, TB; // if !=, R32 = R32 -def CMOVNE32rm: Im32<"cmovne",0x45, MRMSrcMem>, TB; // if !=, R32 = [mem32] - -def CMOVBE16rr: I <"cmovbe",0x46, MRMSrcReg>, TB, OpSize; // if <=u, R16 = R16 -def CMOVBE16rm: Im16<"cmovbe",0x46, MRMSrcMem>, TB, OpSize; // if <=u, R16 = [mem16] -def CMOVBE32rr: I <"cmovbe",0x46, MRMSrcReg>, TB; // if <=u, R32 = R32 -def CMOVBE32rm: Im32<"cmovbe",0x46, MRMSrcMem>, TB; // if <=u, R32 = [mem32] - -def CMOVA16rr : I <"cmova", 0x47, MRMSrcReg>, TB, OpSize; // if >u, R16 = R16 -def CMOVA16rm : Im16<"cmova", 0x47, MRMSrcMem>, TB, OpSize; // if >u, R16 = [mem16] -def CMOVA32rr : I <"cmova", 0x47, MRMSrcReg>, TB; // if >u, R32 = R32 -def CMOVA32rm : Im32<"cmova", 0x47, MRMSrcMem>, TB; // if >u, R32 = [mem32] - -def CMOVS16rr : I <"cmovs", 0x48, MRMSrcReg>, TB, OpSize; // if signed, R16 = R16 -def CMOVS16rm : Im16<"cmovs", 0x48, MRMSrcMem>, TB, OpSize; // if signed, R16 = [mem16] -def CMOVS32rr : I <"cmovs", 0x48, MRMSrcReg>, TB; // if signed, R32 = R32 -def CMOVS32rm : Im32<"cmovs", 0x48, MRMSrcMem>, TB; // if signed, R32 = [mem32] - -def CMOVNS16rr: I <"cmovns",0x49, MRMSrcReg>, TB, OpSize; // if !signed, R16 = R16 -def CMOVNS16rm: Im16<"cmovns",0x49, MRMSrcMem>, TB, OpSize; // if !signed, R16 = [mem16] -def CMOVNS32rr: I <"cmovns",0x49, MRMSrcReg>, TB; // if !signed, R32 = R32 -def CMOVNS32rm: Im32<"cmovns",0x49, MRMSrcMem>, TB; // if !signed, R32 = [mem32] - -def CMOVL16rr : I <"cmovl", 0x4C, MRMSrcReg>, TB, OpSize; // if , TB, OpSize; // if , TB; // if , TB; // if , TB, OpSize; // if >=s, R16 = R16 -def CMOVGE16rm: Im16<"cmovge",0x4D, MRMSrcMem>, TB, OpSize; // if >=s, R16 = [mem16] -def CMOVGE32rr: I <"cmovge",0x4D, MRMSrcReg>, TB; // if >=s, R32 = R32 -def CMOVGE32rm: Im32<"cmovge",0x4D, MRMSrcMem>, TB; // if >=s, R32 = [mem32] - -def CMOVLE16rr: I <"cmovle",0x4E, MRMSrcReg>, TB, OpSize; // if <=s, R16 = R16 -def CMOVLE16rm: Im16<"cmovle",0x4E, MRMSrcMem>, TB, OpSize; // if <=s, R16 = [mem16] -def CMOVLE32rr: I <"cmovle",0x4E, MRMSrcReg>, TB; // if <=s, R32 = R32 -def CMOVLE32rm: Im32<"cmovle",0x4E, MRMSrcMem>, TB; // if <=s, R32 = [mem32] - -def CMOVG16rr : I <"cmovg", 0x4F, MRMSrcReg>, TB, OpSize; // if >s, R16 = R16 -def CMOVG16rm : Im16<"cmovg", 0x4F, MRMSrcMem>, TB, OpSize; // if >s, R16 = [mem16] -def CMOVG32rr : I <"cmovg", 0x4F, MRMSrcReg>, TB; // if >s, R32 = R32 -def CMOVG32rm : Im32<"cmovg", 0x4F, MRMSrcMem>, TB; // if >s, R32 = [mem32] +def CMOVB16rr : I<0x42, MRMSrcReg, // if , TB, OpSize; +def CMOVB16rm : I<0x42, MRMSrcMem, // if , TB, OpSize; +def CMOVB32rr : I<0x42, MRMSrcReg, // if , TB; +def CMOVB32rm : I<0x42, MRMSrcMem, // if , TB; + +def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB; +def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB; + +def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB; +def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB; + +def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB; +def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB; + +def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB; +def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB; + +def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB; +def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB; + +def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB; +def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB; + +def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB; +def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB; + +def CMOVP16rr : I<0x4A, MRMSrcReg, // if parity, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVP16rm : I<0x4A, MRMSrcMem, // if parity, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovp {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVP32rr : I<0x4A, MRMSrcReg, // if parity, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovp {$src2, $dst|$dst, $src2}">, TB; +def CMOVP32rm : I<0x4A, MRMSrcMem, // if parity, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovp {$src2, $dst|$dst, $src2}">, TB; + + +def CMOVNP16rr : I<0x4B, MRMSrcReg, // if !parity, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNP16rm : I<0x4B, MRMSrcMem, // if !parity, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovnp {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNP32rr : I<0x4B, MRMSrcReg, // if !parity, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovnp {$src2, $dst|$dst, $src2}">, TB; +def CMOVNP32rm : I<0x4B, MRMSrcMem, // if !parity, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovnp {$src2, $dst|$dst, $src2}">, TB; + + +def CMOVL16rr : I<0x4C, MRMSrcReg, // if , TB, OpSize; +def CMOVL16rm : I<0x4C, MRMSrcMem, // if , TB, OpSize; +def CMOVL32rr : I<0x4C, MRMSrcReg, // if , TB; +def CMOVL32rm : I<0x4C, MRMSrcMem, // if , TB; + +def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB; +def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB; + +def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB; +def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB; + +def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB; +def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB; // unary instructions -def NEG8r : I <"neg", 0xF6, MRM3r>; // R8 = -R8 = 0-R8 -def NEG16r : I <"neg", 0xF7, MRM3r>, OpSize; // R16 = -R16 = 0-R16 -def NEG32r : I <"neg", 0xF7, MRM3r>; // R32 = -R32 = 0-R32 -def NEG8m : Im8 <"neg", 0xF6, MRM3m>; // [mem8] = -[mem8] = 0-[mem8] -def NEG16m : Im16<"neg", 0xF7, MRM3m>, OpSize; // [mem16] = -[mem16] = 0-[mem16] -def NEG32m : Im32<"neg", 0xF7, MRM3m>; // [mem32] = -[mem32] = 0-[mem32] - -def NOT8r : I <"not", 0xF6, MRM2r>; // R8 = ~R8 = R8^-1 -def NOT16r : I <"not", 0xF7, MRM2r>, OpSize; // R16 = ~R16 = R16^-1 -def NOT32r : I <"not", 0xF7, MRM2r>; // R32 = ~R32 = R32^-1 -def NOT8m : Im8 <"not", 0xF6, MRM2m>; // [mem8] = ~[mem8] = [mem8^-1] -def NOT16m : Im16<"not", 0xF7, MRM2m>, OpSize; // [mem16] = ~[mem16] = [mem16^-1] -def NOT32m : Im32<"not", 0xF7, MRM2m>; // [mem32] = ~[mem32] = [mem32^-1] - -def INC8r : I <"inc", 0xFE, MRM0r>; // ++R8 -def INC16r : I <"inc", 0xFF, MRM0r>, OpSize; // ++R16 -def INC32r : I <"inc", 0xFF, MRM0r>; // ++R32 -def INC8m : Im8 <"inc", 0xFE, MRM0m>; // ++R8 -def INC16m : Im16<"inc", 0xFF, MRM0m>, OpSize; // ++R16 -def INC32m : Im32<"inc", 0xFF, MRM0m>; // ++R32 - -def DEC8r : I <"dec", 0xFE, MRM1r>; // --R8 -def DEC16r : I <"dec", 0xFF, MRM1r>, OpSize; // --R16 -def DEC32r : I <"dec", 0xFF, MRM1r>; // --R32 -def DEC8m : Im8 <"dec", 0xFE, MRM1m>; // --[mem8] -def DEC16m : Im16<"dec", 0xFF, MRM1m>, OpSize; // --[mem16] -def DEC32m : Im32<"dec", 0xFF, MRM1m>; // --[mem32] +def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">; +def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize; +def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">; +let isTwoAddress = 0 in { + def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">; + def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize; + def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">; +} + +def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">; +def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize; +def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">; +let isTwoAddress = 0 in { + def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">; + def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize; + def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">; +} + +def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">; +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize; +def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">; +} +let isTwoAddress = 0 in { + def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">; + def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize; + def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">; +} + +def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">; +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize; +def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">; +} + +let isTwoAddress = 0 in { + def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">; + def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize; + def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">; +} // Logical operators... -def AND8rr : I <"and", 0x20, MRMDestReg>, Pattern<(set R8 , (and R8 , R8 ))>; -def AND16rr : I <"and", 0x21, MRMDestReg>, OpSize, Pattern<(set R16, (and R16, R16))>; -def AND32rr : I <"and", 0x21, MRMDestReg>, Pattern<(set R32, (and R32, R32))>; -def AND8mr : Im8 <"and", 0x20, MRMDestMem>; // [mem8] &= R8 -def AND16mr : Im16 <"and", 0x21, MRMDestMem>, OpSize; // [mem16] &= R16 -def AND32mr : Im32 <"and", 0x21, MRMDestMem>; // [mem32] &= R32 -def AND8rm : Im8 <"and", 0x22, MRMSrcMem >; // R8 &= [mem8] -def AND16rm : Im16 <"and", 0x23, MRMSrcMem >, OpSize; // R16 &= [mem16] -def AND32rm : Im32 <"and", 0x23, MRMSrcMem >; // R32 &= [mem32] - -def AND8ri : Ii8 <"and", 0x80, MRM4r >, Pattern<(set R8 , (and R8 , imm))>; -def AND16ri : Ii16 <"and", 0x81, MRM4r >, OpSize, Pattern<(set R16, (and R16, imm))>; -def AND32ri : Ii32 <"and", 0x81, MRM4r >, Pattern<(set R32, (and R32, imm))>; -def AND8mi : Im8i8 <"and", 0x80, MRM4m >; // [mem8] &= imm8 -def AND16mi : Im16i16<"and", 0x81, MRM4m >, OpSize; // [mem16] &= imm16 -def AND32mi : Im32i32<"and", 0x81, MRM4m >; // [mem32] &= imm32 - -def AND16ri8 : Ii8 <"and", 0x83, MRM4r >, OpSize; // R16 &= imm8 -def AND32ri8 : Ii8 <"and", 0x83, MRM4r >; // R32 &= imm8 -def AND16mi8 : Im16i8<"and", 0x83, MRM4m >, OpSize; // [mem16] &= imm8 -def AND32mi8 : Im32i8<"and", 0x83, MRM4m >; // [mem32] &= imm8 - - -def OR8rr : I <"or" , 0x08, MRMDestReg>, Pattern<(set R8 , (or R8 , R8 ))>; -def OR16rr : I <"or" , 0x09, MRMDestReg>, OpSize, Pattern<(set R16, (or R16, R16))>; -def OR32rr : I <"or" , 0x09, MRMDestReg>, Pattern<(set R32, (or R32, R32))>; -def OR8mr : Im8 <"or" , 0x08, MRMDestMem>; // [mem8] |= R8 -def OR16mr : Im16 <"or" , 0x09, MRMDestMem>, OpSize; // [mem16] |= R16 -def OR32mr : Im32 <"or" , 0x09, MRMDestMem>; // [mem32] |= R32 -def OR8rm : Im8 <"or" , 0x0A, MRMSrcMem >; // R8 |= [mem8] -def OR16rm : Im16 <"or" , 0x0B, MRMSrcMem >, OpSize; // R16 |= [mem16] -def OR32rm : Im32 <"or" , 0x0B, MRMSrcMem >; // R32 |= [mem32] - -def OR8ri : Ii8 <"or" , 0x80, MRM1r >, Pattern<(set R8 , (or R8 , imm))>; -def OR16ri : Ii16 <"or" , 0x81, MRM1r >, OpSize, Pattern<(set R16, (or R16, imm))>; -def OR32ri : Ii32 <"or" , 0x81, MRM1r >, Pattern<(set R32, (or R32, imm))>; -def OR8mi : Im8i8 <"or" , 0x80, MRM1m >; // [mem8] |= imm8 -def OR16mi : Im16i16<"or" , 0x81, MRM1m >, OpSize; // [mem16] |= imm16 -def OR32mi : Im32i32<"or" , 0x81, MRM1m >; // [mem32] |= imm32 - -def OR16ri8 : Ii8 <"or" , 0x83, MRM1r >, OpSize; // R16 |= imm8 -def OR32ri8 : Ii8 <"or" , 0x83, MRM1r >; // R32 |= imm8 -def OR16mi8 : Im16i8<"or" , 0x83, MRM1m >, OpSize; // [mem16] |= imm8 -def OR32mi8 : Im32i8<"or" , 0x83, MRM1m >; // [mem32] |= imm8 - - -def XOR8rr : I <"xor", 0x30, MRMDestReg>, Pattern<(set R8 , (xor R8 , R8 ))>; -def XOR16rr : I <"xor", 0x31, MRMDestReg>, OpSize, Pattern<(set R16, (xor R16, R16))>; -def XOR32rr : I <"xor", 0x31, MRMDestReg>, Pattern<(set R32, (xor R32, R32))>; -def XOR8mr : Im8 <"xor", 0x30, MRMDestMem>; // [mem8] ^= R8 -def XOR16mr : Im16 <"xor", 0x31, MRMDestMem>, OpSize; // [mem16] ^= R16 -def XOR32mr : Im32 <"xor", 0x31, MRMDestMem>; // [mem32] ^= R32 -def XOR8rm : Im8 <"xor", 0x32, MRMSrcMem >; // R8 ^= [mem8] -def XOR16rm : Im16 <"xor", 0x33, MRMSrcMem >, OpSize; // R16 ^= [mem16] -def XOR32rm : Im32 <"xor", 0x33, MRMSrcMem >; // R32 ^= [mem32] - -def XOR8ri : Ii8 <"xor", 0x80, MRM6r >, Pattern<(set R8 , (xor R8 , imm))>; -def XOR16ri : Ii16 <"xor", 0x81, MRM6r >, OpSize, Pattern<(set R16, (xor R16, imm))>; -def XOR32ri : Ii32 <"xor", 0x81, MRM6r >, Pattern<(set R32, (xor R32, imm))>; -def XOR8mi : Im8i8 <"xor", 0x80, MRM6m >; // [mem8] ^= R8 -def XOR16mi : Im16i16<"xor", 0x81, MRM6m >, OpSize; // [mem16] ^= R16 -def XOR32mi : Im32i32<"xor", 0x81, MRM6m >; // [mem32] ^= R32 - -def XOR16ri8 : Ii8 <"xor", 0x83, MRM6r >, OpSize; // R16 ^= imm8 -def XOR32ri8 : Ii8 <"xor", 0x83, MRM6r >; // R32 ^= imm8 -def XOR16mi8 : Im16i8<"xor", 0x83, MRM6m >, OpSize; // [mem16] ^= imm8 -def XOR32mi8 : Im32i8<"xor", 0x83, MRM6m >; // [mem32] ^= imm8 +let isCommutable = 1 in { // X = AND Y, Z --> X = AND Z, Y +def AND8rr : I<0x20, MRMDestReg, + (ops R8 :$dst, R8 :$src1, R8 :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16rr : I<0x21, MRMDestReg, + (ops R16:$dst, R16:$src1, R16:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32rr : I<0x21, MRMDestReg, + (ops R32:$dst, R32:$src1, R32:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; +} + +def AND8rm : I<0x22, MRMSrcMem, + (ops R8 :$dst, R8 :$src1, i8mem :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16rm : I<0x23, MRMSrcMem, + (ops R16:$dst, R16:$src1, i16mem:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32rm : I<0x23, MRMSrcMem, + (ops R32:$dst, R32:$src1, i32mem:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; + +def AND8ri : Ii8<0x80, MRM4r, + (ops R8 :$dst, R8 :$src1, i8imm :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16ri : Ii16<0x81, MRM4r, + (ops R16:$dst, R16:$src1, i16imm:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32ri : Ii32<0x81, MRM4r, + (ops R32:$dst, R32:$src1, i32imm:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; +def AND16ri8 : Ii8<0x83, MRM4r, + (ops R16:$dst, R16:$src1, i8imm:$src2), + "and{w} {$src2, $dst|$dst, $src2}" >, OpSize; +def AND32ri8 : Ii8<0x83, MRM4r, + (ops R32:$dst, R32:$src1, i8imm:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def AND8mr : I<0x20, MRMDestMem, + (ops i8mem :$dst, R8 :$src), + "and{b} {$src, $dst|$dst, $src}">; + def AND16mr : I<0x21, MRMDestMem, + (ops i16mem:$dst, R16:$src), + "and{w} {$src, $dst|$dst, $src}">, OpSize; + def AND32mr : I<0x21, MRMDestMem, + (ops i32mem:$dst, R32:$src), + "and{l} {$src, $dst|$dst, $src}">; + def AND8mi : Ii8<0x80, MRM4m, + (ops i8mem :$dst, i8imm :$src), + "and{b} {$src, $dst|$dst, $src}">; + def AND16mi : Ii16<0x81, MRM4m, + (ops i16mem:$dst, i16imm:$src), + "and{w} {$src, $dst|$dst, $src}">, OpSize; + def AND32mi : Ii32<0x81, MRM4m, + (ops i32mem:$dst, i32imm:$src), + "and{l} {$src, $dst|$dst, $src}">; + def AND16mi8 : Ii8<0x83, MRM4m, + (ops i16mem:$dst, i8imm :$src), + "and{w} {$src, $dst|$dst, $src}">, OpSize; + def AND32mi8 : Ii8<0x83, MRM4m, + (ops i32mem:$dst, i8imm :$src), + "and{l} {$src, $dst|$dst, $src}">; +} + + +let isCommutable = 1 in { // X = OR Y, Z --> X = OR Z, Y +def OR8rr : I<0x08, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), + "or{b} {$src2, $dst|$dst, $src2}">; +def OR16rr : I<0x09, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + "or{w} {$src2, $dst|$dst, $src2}">, OpSize; +def OR32rr : I<0x09, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "or{l} {$src2, $dst|$dst, $src2}">; +} +def OR8rm : I<0x0A, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), + "or{b} {$src2, $dst|$dst, $src2}">; +def OR16rm : I<0x0B, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), + "or{w} {$src2, $dst|$dst, $src2}">, OpSize; +def OR32rm : I<0x0B, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), + "or{l} {$src2, $dst|$dst, $src2}">; + +def OR8ri : Ii8 <0x80, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "or{b} {$src2, $dst|$dst, $src2}">; +def OR16ri : Ii16<0x81, MRM1r, (ops R16:$dst, R16:$src1, i16imm:$src2), + "or{w} {$src2, $dst|$dst, $src2}">, OpSize; +def OR32ri : Ii32<0x81, MRM1r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "or{l} {$src2, $dst|$dst, $src2}">; + +def OR16ri8 : Ii8<0x83, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "or{w} {$src2, $dst|$dst, $src2}">, OpSize; +def OR32ri8 : Ii8<0x83, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "or{l} {$src2, $dst|$dst, $src2}">; +let isTwoAddress = 0 in { + def OR8mr : I<0x08, MRMDestMem, (ops i8mem:$dst, R8:$src), + "or{b} {$src, $dst|$dst, $src}">; + def OR16mr : I<0x09, MRMDestMem, (ops i16mem:$dst, R16:$src), + "or{w} {$src, $dst|$dst, $src}">, OpSize; + def OR32mr : I<0x09, MRMDestMem, (ops i32mem:$dst, R32:$src), + "or{l} {$src, $dst|$dst, $src}">; + def OR8mi : Ii8<0x80, MRM1m, (ops i8mem :$dst, i8imm:$src), + "or{b} {$src, $dst|$dst, $src}">; + def OR16mi : Ii16<0x81, MRM1m, (ops i16mem:$dst, i16imm:$src), + "or{w} {$src, $dst|$dst, $src}">, OpSize; + def OR32mi : Ii32<0x81, MRM1m, (ops i32mem:$dst, i32imm:$src), + "or{l} {$src, $dst|$dst, $src}">; + def OR16mi8 : Ii8<0x83, MRM1m, (ops i16mem:$dst, i8imm:$src), + "or{w} {$src, $dst|$dst, $src}">, OpSize; + def OR32mi8 : Ii8<0x83, MRM1m, (ops i32mem:$dst, i8imm:$src), + "or{l} {$src, $dst|$dst, $src}">; +} + + +let isCommutable = 1 in { // X = XOR Y, Z --> X = XOR Z, Y +def XOR8rr : I<0x30, MRMDestReg, + (ops R8 :$dst, R8 :$src1, R8 :$src2), + "xor{b} {$src2, $dst|$dst, $src2}">; +def XOR16rr : I<0x31, MRMDestReg, + (ops R16:$dst, R16:$src1, R16:$src2), + "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; +def XOR32rr : I<0x31, MRMDestReg, + (ops R32:$dst, R32:$src1, R32:$src2), + "xor{l} {$src2, $dst|$dst, $src2}">; +} + +def XOR8rm : I<0x32, MRMSrcMem , + (ops R8 :$dst, R8:$src1, i8mem :$src2), + "xor{b} {$src2, $dst|$dst, $src2}">; +def XOR16rm : I<0x33, MRMSrcMem , + (ops R16:$dst, R8:$src1, i16mem:$src2), + "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; +def XOR32rm : I<0x33, MRMSrcMem , + (ops R32:$dst, R8:$src1, i32mem:$src2), + "xor{l} {$src2, $dst|$dst, $src2}">; + +def XOR8ri : Ii8<0x80, MRM6r, + (ops R8:$dst, R8:$src1, i8imm:$src2), + "xor{b} {$src2, $dst|$dst, $src2}">; +def XOR16ri : Ii16<0x81, MRM6r, + (ops R16:$dst, R16:$src1, i16imm:$src2), + "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; +def XOR32ri : Ii32<0x81, MRM6r, + (ops R32:$dst, R32:$src1, i32imm:$src2), + "xor{l} {$src2, $dst|$dst, $src2}">; +def XOR16ri8 : Ii8<0x83, MRM6r, + (ops R16:$dst, R16:$src1, i8imm:$src2), + "xor{w} {$src2, $dst|$dst, $src2}">, OpSize; +def XOR32ri8 : Ii8<0x83, MRM6r, + (ops R32:$dst, R32:$src1, i8imm:$src2), + "xor{l} {$src2, $dst|$dst, $src2}">; +let isTwoAddress = 0 in { + def XOR8mr : I<0x30, MRMDestMem, + (ops i8mem :$dst, R8 :$src), + "xor{b} {$src, $dst|$dst, $src}">; + def XOR16mr : I<0x31, MRMDestMem, + (ops i16mem:$dst, R16:$src), + "xor{w} {$src, $dst|$dst, $src}">, OpSize; + def XOR32mr : I<0x31, MRMDestMem, + (ops i32mem:$dst, R32:$src), + "xor{l} {$src, $dst|$dst, $src}">; + def XOR8mi : Ii8<0x80, MRM6m, + (ops i8mem :$dst, i8imm :$src), + "xor{b} {$src, $dst|$dst, $src}">; + def XOR16mi : Ii16<0x81, MRM6m, + (ops i16mem:$dst, i16imm:$src), + "xor{w} {$src, $dst|$dst, $src}">, OpSize; + def XOR32mi : Ii32<0x81, MRM6m, + (ops i32mem:$dst, i32imm:$src), + "xor{l} {$src, $dst|$dst, $src}">; + def XOR16mi8 : Ii8<0x83, MRM6m, + (ops i16mem:$dst, i8imm :$src), + "xor{w} {$src, $dst|$dst, $src}">, OpSize; + def XOR32mi8 : Ii8<0x83, MRM6m, + (ops i32mem:$dst, i8imm :$src), + "xor{l} {$src, $dst|$dst, $src}">; +} // Shift instructions // FIXME: provide shorter instructions when imm8 == 1 -def SHL8rCL : I <"shl", 0xD2, MRM4r > , UsesCL; // R8 <<= cl -def SHL16rCL : I <"shl", 0xD3, MRM4r >, OpSize, UsesCL; // R16 <<= cl -def SHL32rCL : I <"shl", 0xD3, MRM4r > , UsesCL; // R32 <<= cl -def SHL8mCL : Im8 <"shl", 0xD2, MRM4m > , UsesCL; // [mem8] <<= cl -def SHL16mCL : Im16 <"shl", 0xD3, MRM4m >, OpSize, UsesCL; // [mem16] <<= cl -def SHL32mCL : Im32 <"shl", 0xD3, MRM4m > , UsesCL; // [mem32] <<= cl - -def SHL8ri : Ii8 <"shl", 0xC0, MRM4r >; // R8 <<= imm8 -def SHL16ri : Ii8 <"shl", 0xC1, MRM4r >, OpSize; // R16 <<= imm8 -def SHL32ri : Ii8 <"shl", 0xC1, MRM4r >; // R32 <<= imm8 -def SHL8mi : Im8i8 <"shl", 0xC0, MRM4m >; // [mem8] <<= imm8 -def SHL16mi : Im16i8<"shl", 0xC1, MRM4m >, OpSize; // [mem16] <<= imm8 -def SHL32mi : Im32i8<"shl", 0xC1, MRM4m >; // [mem32] <<= imm8 - -def SHR8rCL : I <"shr", 0xD2, MRM5r > , UsesCL; // R8 >>= cl -def SHR16rCL : I <"shr", 0xD3, MRM5r >, OpSize, UsesCL; // R16 >>= cl -def SHR32rCL : I <"shr", 0xD3, MRM5r > , UsesCL; // R32 >>= cl -def SHR8mCL : Im8 <"shr", 0xD2, MRM5m > , UsesCL; // [mem8] >>= cl -def SHR16mCL : Im16 <"shr", 0xD3, MRM5m >, OpSize, UsesCL; // [mem16] >>= cl -def SHR32mCL : Im32 <"shr", 0xD3, MRM5m > , UsesCL; // [mem32] >>= cl - -def SHR8ri : Ii8 <"shr", 0xC0, MRM5r >; // R8 >>= imm8 -def SHR16ri : Ii8 <"shr", 0xC1, MRM5r >, OpSize; // R16 >>= imm8 -def SHR32ri : Ii8 <"shr", 0xC1, MRM5r >; // R32 >>= imm8 -def SHR8mi : Im8i8 <"shr", 0xC0, MRM5m >; // [mem8] >>= imm8 -def SHR16mi : Im16i8<"shr", 0xC1, MRM5m >, OpSize; // [mem16] >>= imm8 -def SHR32mi : Im32i8<"shr", 0xC1, MRM5m >; // [mem32] >>= imm8 - -def SAR8rCL : I <"sar", 0xD2, MRM7r > , UsesCL; // R8 >>>= cl -def SAR16rCL : I <"sar", 0xD3, MRM7r >, OpSize, UsesCL; // R16 >>>= cl -def SAR32rCL : I <"sar", 0xD3, MRM7r > , UsesCL; // R32 >>>= cl -def SAR8mCL : Im8 <"sar", 0xD2, MRM7m > , UsesCL; // [mem8] >>>= cl -def SAR16mCL : Im16 <"sar", 0xD3, MRM7m >, OpSize, UsesCL; // [mem16] >>>= cl -def SAR32mCL : Im32 <"sar", 0xD3, MRM7m > , UsesCL; // [mem32] >>>= cl - -def SAR8ri : Ii8 <"sar", 0xC0, MRM7r >; // R8 >>>= imm8 -def SAR16ri : Ii8 <"sar", 0xC1, MRM7r >, OpSize; // R16 >>>= imm8 -def SAR32ri : Ii8 <"sar", 0xC1, MRM7r >; // R32 >>>= imm8 -def SAR8mi : Im8i8 <"sar", 0xC0, MRM7m >; // [mem8] >>>= imm8 -def SAR16mi : Im16i8<"sar", 0xC1, MRM7m >, OpSize; // [mem16] >>>= imm8 -def SAR32mi : Im32i8<"sar", 0xC1, MRM7m >; // [mem32] >>>= imm8 - -def SHLD32rrCL : I <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl -def SHLD32mrCL : Im32 <"shld", 0xA5, MRMDestMem>, TB, UsesCL; // [mem32] <<= [mem32],R32 cl -def SHLD32rri8 : Ii8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8 -def SHLD32mri8 : Im32i8<"shld", 0xA4, MRMDestMem>, TB; // [mem32] <<= [mem32],R32 imm8 - -def SHRD32rrCL : I <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl -def SHRD32mrCL : Im32 <"shrd", 0xAD, MRMDestMem>, TB, UsesCL; // [mem32] >>= [mem32],R32 cl -def SHRD32rri8 : Ii8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8 -def SHRD32mri8 : Im32i8<"shrd", 0xAC, MRMDestMem>, TB; // [mem32] >>= [mem32],R32 imm8 - - -// Arithmetic... -def ADD8rr : I <"add", 0x00, MRMDestReg>, Pattern<(set R8 , (plus R8 , R8 ))>; -def ADD16rr : I <"add", 0x01, MRMDestReg>, OpSize, Pattern<(set R16, (plus R16, R16))>; -def ADD32rr : I <"add", 0x01, MRMDestReg>, Pattern<(set R32, (plus R32, R32))>; -def ADD8mr : Im8 <"add", 0x00, MRMDestMem>; // [mem8] += R8 -def ADD16mr : Im16 <"add", 0x01, MRMDestMem>, OpSize; // [mem16] += R16 -def ADD32mr : Im32 <"add", 0x01, MRMDestMem>; // [mem32] += R32 -def ADD8rm : Im8 <"add", 0x02, MRMSrcMem >; // R8 += [mem8] -def ADD16rm : Im16 <"add", 0x03, MRMSrcMem >, OpSize; // R16 += [mem16] -def ADD32rm : Im32 <"add", 0x03, MRMSrcMem >; // R32 += [mem32] - -def ADD8ri : Ii8 <"add", 0x80, MRM0r >, Pattern<(set R8 , (plus R8 , imm))>; -def ADD16ri : Ii16 <"add", 0x81, MRM0r >, OpSize, Pattern<(set R16, (plus R16, imm))>; -def ADD32ri : Ii32 <"add", 0x81, MRM0r >, Pattern<(set R32, (plus R32, imm))>; -def ADD8mi : Im8i8 <"add", 0x80, MRM0m >; // [mem8] += I8 -def ADD16mi : Im16i16<"add", 0x81, MRM0m >, OpSize; // [mem16] += I16 -def ADD32mi : Im32i32<"add", 0x81, MRM0m >; // [mem32] += I32 - -def ADD16ri8 : Ii8 <"add", 0x83, MRM0r >, OpSize; // ADDri with sign extended 8 bit imm -def ADD32ri8 : Ii8 <"add", 0x83, MRM0r >; -def ADD16mi8 : Im16i8<"add", 0x83, MRM0m >, OpSize; // [mem16] += I8 -def ADD32mi8 : Im32i8<"add", 0x83, MRM0m >; // [mem32] += I8 - -def ADC32rr : I <"adc", 0x11, MRMDestReg>; // R32 += R32+Carry -def ADC32mr : Im32 <"adc", 0x11, MRMDestMem>; // [mem32] += R32+Carry -def ADC32rm : Im32 <"adc", 0x13, MRMSrcMem >; // R32 += [mem32]+Carry -def ADC32ri : Ii32 <"adc", 0x81, MRM2r >; // R32 += I32+Carry -def ADC32ri8 : Ii8 <"adc", 0x83, MRM2r >; // R32 += I8+Carry -def ADC32mi : Im32i32<"adc", 0x81, MRM2m >; // [mem32] += I32+Carry -def ADC32mi8 : Im32i8 <"adc", 0x83, MRM2m >; // [mem32] += I8+Carry - -def SUB8rr : I <"sub", 0x28, MRMDestReg>, Pattern<(set R8 , (minus R8 , R8 ))>; -def SUB16rr : I <"sub", 0x29, MRMDestReg>, OpSize, Pattern<(set R16, (minus R16, R16))>; -def SUB32rr : I <"sub", 0x29, MRMDestReg>, Pattern<(set R32, (minus R32, R32))>; -def SUB8mr : Im8 <"sub", 0x28, MRMDestMem>; // [mem8] -= R8 -def SUB16mr : Im16 <"sub", 0x29, MRMDestMem>, OpSize; // [mem16] -= R16 -def SUB32mr : Im32 <"sub", 0x29, MRMDestMem>; // [mem32] -= R32 -def SUB8rm : Im8 <"sub", 0x2A, MRMSrcMem >; // R8 -= [mem8] -def SUB16rm : Im16 <"sub", 0x2B, MRMSrcMem >, OpSize; // R16 -= [mem16] -def SUB32rm : Im32 <"sub", 0x2B, MRMSrcMem >; // R32 -= [mem32] - -def SUB8ri : Ii8 <"sub", 0x80, MRM5r >, Pattern<(set R8 , (minus R8 , imm))>; -def SUB16ri : Ii16 <"sub", 0x81, MRM5r >, OpSize, Pattern<(set R16, (minus R16, imm))>; -def SUB32ri : Ii32 <"sub", 0x81, MRM5r >, Pattern<(set R32, (minus R32, imm))>; -def SUB8mi : Im8i8 <"sub", 0x80, MRM5m >; // [mem8] -= I8 -def SUB16mi : Im16i16<"sub", 0x81, MRM5m >, OpSize; // [mem16] -= I16 -def SUB32mi : Im32i32<"sub", 0x81, MRM5m >; // [mem32] -= I32 - -def SUB16ri8 : Ii8 <"sub", 0x83, MRM5r >, OpSize; -def SUB32ri8 : Ii8 <"sub", 0x83, MRM5r >; -def SUB16mi8 : Im16i8<"sub", 0x83, MRM5m >, OpSize; // [mem16] -= I8 -def SUB32mi8 : Im32i8<"sub", 0x83, MRM5m >; // [mem32] -= I8 - -def SBB32rr : I <"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carry -def SBB32mr : Im32 <"sbb", 0x19, MRMDestMem>; // [mem32] -= R32+Carry -def SBB32rm : Im32 <"sbb", 0x1B, MRMSrcMem >; // R32 -= [mem32]+Carry -def SBB32ri : Ii32 <"sbb", 0x81, MRM3r >; // R32 -= I32+Carry -def SBB32ri8 : Ii8 <"sbb", 0x83, MRM3r >; // R32 -= I8+Carry -def SBB32mi : Im32i32<"sbb", 0x81, MRM3m >; // [mem32] -= I32+Carry -def SBB32mi8 : Im32i8 <"sbb", 0x83, MRM3m >; // [mem32] -= I8+Carry - -def IMUL16rr : I <"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>; -def IMUL32rr : I <"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>; -def IMUL16rm : Im16 <"imul", 0xAF, MRMSrcMem>, TB, OpSize; -def IMUL32rm : Im32 <"imul", 0xAF, MRMSrcMem>, TB ; +def SHL8rCL : I<0xD2, MRM4r, (ops R8 :$dst, R8 :$src), + "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; +def SHL16rCL : I<0xD3, MRM4r, (ops R16:$dst, R16:$src), + "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; +def SHL32rCL : I<0xD3, MRM4r, (ops R32:$dst, R32:$src), + "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + +def SHL8ri : Ii8<0xC0, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "shl{b} {$src2, $dst|$dst, $src2}">; +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def SHL16ri : Ii8<0xC1, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "shl{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SHL32ri : Ii8<0xC1, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "shl{l} {$src2, $dst|$dst, $src2}">; +} + +let isTwoAddress = 0 in { + def SHL8mCL : I<0xD2, MRM4m, (ops i8mem :$dst), + "shl{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SHL16mCL : I<0xD3, MRM4m, (ops i16mem:$dst), + "shl{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + def SHL32mCL : I<0xD3, MRM4m, (ops i32mem:$dst), + "shl{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SHL8mi : Ii8<0xC0, MRM4m, (ops i8mem :$dst, i8imm:$src), + "shl{b} {$src, $dst|$dst, $src}">; + def SHL16mi : Ii8<0xC1, MRM4m, (ops i16mem:$dst, i8imm:$src), + "shl{w} {$src, $dst|$dst, $src}">, OpSize; + def SHL32mi : Ii8<0xC1, MRM4m, (ops i32mem:$dst, i8imm:$src), + "shl{l} {$src, $dst|$dst, $src}">; +} + +def SHR8rCL : I<0xD2, MRM5r, (ops R8 :$dst, R8 :$src), + "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; +def SHR16rCL : I<0xD3, MRM5r, (ops R16:$dst, R16:$src), + "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; +def SHR32rCL : I<0xD3, MRM5r, (ops R32:$dst, R32:$src), + "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + +def SHR8ri : Ii8<0xC0, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), + "shr{b} {$src2, $dst|$dst, $src2}">; +def SHR16ri : Ii8<0xC1, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "shr{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SHR32ri : Ii8<0xC1, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "shr{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def SHR8mCL : I<0xD2, MRM5m, (ops i8mem :$dst), + "shr{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SHR16mCL : I<0xD3, MRM5m, (ops i16mem:$dst), + "shr{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + def SHR32mCL : I<0xD3, MRM5m, (ops i32mem:$dst), + "shr{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SHR8mi : Ii8<0xC0, MRM5m, (ops i8mem :$dst, i8imm:$src), + "shr{b} {$src, $dst|$dst, $src}">; + def SHR16mi : Ii8<0xC1, MRM5m, (ops i16mem:$dst, i8imm:$src), + "shr{w} {$src, $dst|$dst, $src}">, OpSize; + def SHR32mi : Ii8<0xC1, MRM5m, (ops i32mem:$dst, i8imm:$src), + "shr{l} {$src, $dst|$dst, $src}">; +} + +def SAR8rCL : I<0xD2, MRM7r, (ops R8 :$dst, R8 :$src), + "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; +def SAR16rCL : I<0xD3, MRM7r, (ops R16:$dst, R16:$src), + "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; +def SAR32rCL : I<0xD3, MRM7r, (ops R32:$dst, R32:$src), + "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + +def SAR8ri : Ii8<0xC0, MRM7r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "sar{b} {$src2, $dst|$dst, $src2}">; +def SAR16ri : Ii8<0xC1, MRM7r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "sar{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SAR32ri : Ii8<0xC1, MRM7r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "sar{l} {$src2, $dst|$dst, $src2}">; +let isTwoAddress = 0 in { + def SAR8mCL : I<0xD2, MRM7m, (ops i8mem :$dst), + "sar{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SAR16mCL : I<0xD3, MRM7m, (ops i16mem:$dst), + "sar{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + def SAR32mCL : I<0xD3, MRM7m, (ops i32mem:$dst), + "sar{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def SAR8mi : Ii8<0xC0, MRM7m, (ops i8mem :$dst, i8imm:$src), + "sar{b} {$src, $dst|$dst, $src}">; + def SAR16mi : Ii8<0xC1, MRM7m, (ops i16mem:$dst, i8imm:$src), + "sar{w} {$src, $dst|$dst, $src}">, OpSize; + def SAR32mi : Ii8<0xC1, MRM7m, (ops i32mem:$dst, i8imm:$src), + "sar{l} {$src, $dst|$dst, $src}">; +} + +// Rotate instructions +// FIXME: provide shorter instructions when imm8 == 1 +def ROL8rCL : I<0xD2, MRM0r, (ops R8 :$dst, R8 :$src), + "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; +def ROL16rCL : I<0xD3, MRM0r, (ops R16:$dst, R16:$src), + "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; +def ROL32rCL : I<0xD3, MRM0r, (ops R32:$dst, R32:$src), + "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + +def ROL8ri : Ii8<0xC0, MRM0r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "rol{b} {$src2, $dst|$dst, $src2}">; +def ROL16ri : Ii8<0xC1, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "rol{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ROL32ri : Ii8<0xC1, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "rol{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def ROL8mCL : I<0xD2, MRM0m, (ops i8mem :$dst), + "rol{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def ROL16mCL : I<0xD3, MRM0m, (ops i16mem:$dst), + "rol{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + def ROL32mCL : I<0xD3, MRM0m, (ops i32mem:$dst), + "rol{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def ROL8mi : Ii8<0xC0, MRM0m, (ops i8mem :$dst, i8imm:$src), + "rol{b} {$src, $dst|$dst, $src}">; + def ROL16mi : Ii8<0xC1, MRM0m, (ops i16mem:$dst, i8imm:$src), + "rol{w} {$src, $dst|$dst, $src}">, OpSize; + def ROL32mi : Ii8<0xC1, MRM0m, (ops i32mem:$dst, i8imm:$src), + "rol{l} {$src, $dst|$dst, $src}">; +} + +def ROR8rCL : I<0xD2, MRM1r, (ops R8 :$dst, R8 :$src), + "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; +def ROR16rCL : I<0xD3, MRM1r, (ops R16:$dst, R16:$src), + "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; +def ROR32rCL : I<0xD3, MRM1r, (ops R32:$dst, R32:$src), + "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + +def ROR8ri : Ii8<0xC0, MRM1r, (ops R8 :$dst, R8 :$src1, i8imm:$src2), + "ror{b} {$src2, $dst|$dst, $src2}">; +def ROR16ri : Ii8<0xC1, MRM1r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "ror{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ROR32ri : Ii8<0xC1, MRM1r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "ror{l} {$src2, $dst|$dst, $src2}">; +let isTwoAddress = 0 in { + def ROR8mCL : I<0xD2, MRM1m, (ops i8mem :$dst), + "ror{b} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def ROR16mCL : I<0xD3, MRM1m, (ops i16mem:$dst), + "ror{w} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>, OpSize; + def ROR32mCL : I<0xD3, MRM1m, (ops i32mem:$dst), + "ror{l} {%cl, $dst|$dst, %CL}">, Imp<[CL],[]>; + def ROR8mi : Ii8<0xC0, MRM1m, (ops i8mem :$dst, i8imm:$src), + "ror{b} {$src, $dst|$dst, $src}">; + def ROR16mi : Ii8<0xC1, MRM1m, (ops i16mem:$dst, i8imm:$src), + "ror{w} {$src, $dst|$dst, $src}">, OpSize; + def ROR32mi : Ii8<0xC1, MRM1m, (ops i32mem:$dst, i8imm:$src), + "ror{l} {$src, $dst|$dst, $src}">; +} + + + +// Double shift instructions (generalizations of rotate) + +def SHLD32rrCL : I<0xA5, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB; +def SHRD32rrCL : I<0xAD, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB; +def SHLD16rrCL : I<0xA5, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB, OpSize; +def SHRD16rrCL : I<0xAD, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB, OpSize; + +let isCommutable = 1 in { // These instructions commute to each other. +def SHLD32rri8 : Ii8<0xA4, MRMDestReg, + (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), + "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; +def SHRD32rri8 : Ii8<0xAC, MRMDestReg, + (ops R32:$dst, R32:$src1, R32:$src2, i8imm:$src3), + "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; +def SHLD16rri8 : Ii8<0xA4, MRMDestReg, + (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), + "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">, + TB, OpSize; +def SHRD16rri8 : Ii8<0xAC, MRMDestReg, + (ops R16:$dst, R16:$src1, R16:$src2, i8imm:$src3), + "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">, + TB, OpSize; +} + +let isTwoAddress = 0 in { + def SHLD32mrCL : I<0xA5, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "shld{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB; + def SHRD32mrCL : I<0xAD, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "shrd{l} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB; + def SHLD32mri8 : Ii8<0xA4, MRMDestMem, + (ops i32mem:$dst, R32:$src2, i8imm:$src3), + "shld{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; + def SHRD32mri8 : Ii8<0xAC, MRMDestMem, + (ops i32mem:$dst, R32:$src2, i8imm:$src3), + "shrd{l} {$src3, $src2, $dst|$dst, $src2, $src3}">, TB; + + def SHLD16mrCL : I<0xA5, MRMDestMem, (ops i16mem:$dst, R16:$src2), + "shld{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB, OpSize; + def SHRD16mrCL : I<0xAD, MRMDestMem, (ops i16mem:$dst, R16:$src2), + "shrd{w} {%cl, $src2, $dst|$dst, $src2, %CL}">, + Imp<[CL],[]>, TB, OpSize; + def SHLD16mri8 : Ii8<0xA4, MRMDestMem, + (ops i16mem:$dst, R16:$src2, i8imm:$src3), + "shld{w} {$src3, $src2, $dst|$dst, $src2, $src3}">, + TB, OpSize; + def SHRD16mri8 : Ii8<0xAC, MRMDestMem, + (ops i16mem:$dst, R16:$src2, i8imm:$src3), + "shrd{w} {$src3, $src2, $dst|$dst, $src2, $src3}">, + TB, OpSize; +} + + +// Arithmetic. +let isCommutable = 1 in { // X = ADD Y, Z --> X = ADD Z, Y +def ADD8rr : I<0x00, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), + "add{b} {$src2, $dst|$dst, $src2}">; +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def ADD16rr : I<0x01, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ADD32rr : I<0x01, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; +} // end isConvertibleToThreeAddress +} // end isCommutable +def ADD8rm : I<0x02, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), + "add{b} {$src2, $dst|$dst, $src2}">; +def ADD16rm : I<0x03, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ADD32rm : I<0x03, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; + +def ADD8ri : Ii8<0x80, MRM0r, (ops R8:$dst, R8:$src1, i8imm:$src2), + "add{b} {$src2, $dst|$dst, $src2}">; + +let isConvertibleToThreeAddress = 1 in { // Can transform into LEA. +def ADD16ri : Ii16<0x81, MRM0r, (ops R16:$dst, R16:$src1, i16imm:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ADD32ri : Ii32<0x81, MRM0r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; +} + +def ADD16ri8 : Ii8<0x83, MRM0r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; +def ADD32ri8 : Ii8<0x83, MRM0r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def ADD8mr : I<0x00, MRMDestMem, (ops i8mem :$dst, R8 :$src2), + "add{b} {$src2, $dst|$dst, $src2}">; + def ADD16mr : I<0x01, MRMDestMem, (ops i16mem:$dst, R16:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + def ADD32mr : I<0x01, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; + def ADD8mi : Ii8<0x80, MRM0m, (ops i8mem :$dst, i8imm :$src2), + "add{b} {$src2, $dst|$dst, $src2}">; + def ADD16mi : Ii16<0x81, MRM0m, (ops i16mem:$dst, i16imm:$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + def ADD32mi : Ii32<0x81, MRM0m, (ops i32mem:$dst, i32imm:$src2), + "add{l} {$src2, $dst|$dst, $src2}">; + def ADD16mi8 : Ii8<0x83, MRM0m, (ops i16mem:$dst, i8imm :$src2), + "add{w} {$src2, $dst|$dst, $src2}">, OpSize; + def ADD32mi8 : Ii8<0x83, MRM0m, (ops i32mem:$dst, i8imm :$src2), + "add{l} {$src2, $dst|$dst, $src2}">; +} + +let isCommutable = 1 in { // X = ADC Y, Z --> X = ADC Z, Y +def ADC32rr : I<0x11, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; +} +def ADC32rm : I<0x13, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; +def ADC32ri : Ii32<0x81, MRM2r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; +def ADC32ri8 : Ii8<0x83, MRM2r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def ADC32mr : I<0x11, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; + def ADC32mi : Ii32<0x81, MRM2m, (ops i32mem:$dst, i32imm:$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; + def ADC32mi8 : Ii8<0x83, MRM2m, (ops i32mem:$dst, i8imm :$src2), + "adc{l} {$src2, $dst|$dst, $src2}">; +} + +def SUB8rr : I<0x28, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), + "sub{b} {$src2, $dst|$dst, $src2}">; +def SUB16rr : I<0x29, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SUB32rr : I<0x29, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; +def SUB8rm : I<0x2A, MRMSrcMem, (ops R8 :$dst, R8 :$src1, i8mem :$src2), + "sub{b} {$src2, $dst|$dst, $src2}">; +def SUB16rm : I<0x2B, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SUB32rm : I<0x2B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; + +def SUB8ri : Ii8 <0x80, MRM5r, (ops R8:$dst, R8:$src1, i8imm:$src2), + "sub{b} {$src2, $dst|$dst, $src2}">; +def SUB16ri : Ii16<0x81, MRM5r, (ops R16:$dst, R16:$src1, i16imm:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SUB32ri : Ii32<0x81, MRM5r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; +def SUB16ri8 : Ii8<0x83, MRM5r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SUB32ri8 : Ii8<0x83, MRM5r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; +let isTwoAddress = 0 in { + def SUB8mr : I<0x28, MRMDestMem, (ops i8mem :$dst, R8 :$src2), + "sub{b} {$src2, $dst|$dst, $src2}">; + def SUB16mr : I<0x29, MRMDestMem, (ops i16mem:$dst, R16:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + def SUB32mr : I<0x29, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; + def SUB8mi : Ii8<0x80, MRM5m, (ops i8mem :$dst, i8imm:$src2), + "sub{b} {$src2, $dst|$dst, $src2}">; + def SUB16mi : Ii16<0x81, MRM5m, (ops i16mem:$dst, i16imm:$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + def SUB32mi : Ii32<0x81, MRM5m, (ops i32mem:$dst, i32imm:$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; + def SUB16mi8 : Ii8<0x83, MRM5m, (ops i16mem:$dst, i8imm :$src2), + "sub{w} {$src2, $dst|$dst, $src2}">, OpSize; + def SUB32mi8 : Ii8<0x83, MRM5m, (ops i32mem:$dst, i8imm :$src2), + "sub{l} {$src2, $dst|$dst, $src2}">; +} + +def SBB32rr : I<0x19, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; + +let isTwoAddress = 0 in { + def SBB32mr : I<0x19, MRMDestMem, (ops i32mem:$dst, R32:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; + def SBB8mi : Ii32<0x80, MRM3m, (ops i8mem:$dst, i8imm:$src2), + "sbb{b} {$src2, $dst|$dst, $src2}">; + def SBB16mi : Ii32<0x81, MRM3m, (ops i16mem:$dst, i16imm:$src2), + "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; + def SBB32mi : Ii32<0x81, MRM3m, (ops i32mem:$dst, i32imm:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; + def SBB16mi8 : Ii8<0x83, MRM3m, (ops i16mem:$dst, i8imm :$src2), + "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; + def SBB32mi8 : Ii8<0x83, MRM3m, (ops i32mem:$dst, i8imm :$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; +} +def SBB8ri : Ii8<0x80, MRM3r, (ops R8:$dst, R8:$src1, i8imm:$src2), + "sbb{b} {$src2, $dst|$dst, $src2}">; +def SBB16ri : Ii16<0x81, MRM3r, (ops R16:$dst, R16:$src1, i16imm:$src2), + "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; + +def SBB32rm : I<0x1B, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; +def SBB32ri : Ii32<0x81, MRM3r, (ops R32:$dst, R32:$src1, i32imm:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; + +def SBB16ri8 : Ii8<0x83, MRM3r, (ops R16:$dst, R16:$src1, i8imm:$src2), + "sbb{w} {$src2, $dst|$dst, $src2}">, OpSize; +def SBB32ri8 : Ii8<0x83, MRM3r, (ops R32:$dst, R32:$src1, i8imm:$src2), + "sbb{l} {$src2, $dst|$dst, $src2}">; + +let isCommutable = 1 in { // X = IMUL Y, Z --> X = IMUL Z, Y +def IMUL16rr : I<0xAF, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), + "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; +def IMUL32rr : I<0xAF, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), + "imul{l} {$src2, $dst|$dst, $src2}">, TB; +} +def IMUL16rm : I<0xAF, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), + "imul{w} {$src2, $dst|$dst, $src2}">, TB, OpSize; +def IMUL32rm : I<0xAF, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), + "imul{l} {$src2, $dst|$dst, $src2}">, TB; } // end Two Address instructions -// These are suprisingly enough not two address instructions! -def IMUL16rri : Ii16 <"imul", 0x69, MRMSrcReg>, OpSize; // R16 = R16*I16 -def IMUL32rri : Ii32 <"imul", 0x69, MRMSrcReg>; // R32 = R32*I32 -def IMUL16rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>, OpSize; // R16 = R16*I8 -def IMUL32rri8 : Ii8 <"imul", 0x6B, MRMSrcReg>; // R32 = R32*I8 -def IMUL16rmi : Im16i16<"imul",0x69, MRMSrcMem>, OpSize; // R16 = [mem16]*I16 -def IMUL32rmi : Im32i32<"imul",0x69, MRMSrcMem>; // R32 = [mem32]*I32 -def IMUL16rmi8 : Im16i8<"imul", 0x6B, MRMSrcMem>, OpSize; // R16 = [mem16]*I8 -def IMUL32rmi8 : Im32i8<"imul", 0x6B, MRMSrcMem>; // R32 = [mem32]*I8 +// Suprisingly enough, these are not two address instructions! +def IMUL16rri : Ii16<0x69, MRMSrcReg, // R16 = R16*I16 + (ops R16:$dst, R16:$src1, i16imm:$src2), + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, + OpSize; +def IMUL32rri : Ii32<0x69, MRMSrcReg, // R32 = R32*I32 + (ops R32:$dst, R32:$src1, i32imm:$src2), + "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; +def IMUL16rri8 : Ii8<0x6B, MRMSrcReg, // R16 = R16*I8 + (ops R16:$dst, R16:$src1, i8imm:$src2), + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; +def IMUL32rri8 : Ii8<0x6B, MRMSrcReg, // R32 = R32*I8 + (ops R32:$dst, R32:$src1, i8imm:$src2), + "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; + +def IMUL16rmi : Ii16<0x69, MRMSrcMem, // R16 = [mem16]*I16 + (ops R32:$dst, i16mem:$src1, i16imm:$src2), + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; +def IMUL32rmi : Ii32<0x69, MRMSrcMem, // R32 = [mem32]*I32 + (ops R32:$dst, i32mem:$src1, i32imm:$src2), + "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; +def IMUL16rmi8 : Ii8<0x6B, MRMSrcMem, // R16 = [mem16]*I8 + (ops R32:$dst, i16mem:$src1, i8imm :$src2), + "imul{w} {$src2, $src1, $dst|$dst, $src1, $src2}">, OpSize; +def IMUL32rmi8 : Ii8<0x6B, MRMSrcMem, // R32 = [mem32]*I8 + (ops R32:$dst, i32mem:$src1, i8imm: $src2), + "imul{l} {$src2, $src1, $dst|$dst, $src1, $src2}">; //===----------------------------------------------------------------------===// // Test instructions are just like AND, except they don't generate a result. -def TEST8rr : I <"test", 0x84, MRMDestReg>; // flags = R8 & R8 -def TEST16rr : I <"test", 0x85, MRMDestReg>, OpSize; // flags = R16 & R16 -def TEST32rr : I <"test", 0x85, MRMDestReg>; // flags = R32 & R32 -def TEST8mr : Im8 <"test", 0x84, MRMDestMem>; // flags = [mem8] & R8 -def TEST16mr : Im16 <"test", 0x85, MRMDestMem>, OpSize; // flags = [mem16] & R16 -def TEST32mr : Im32 <"test", 0x85, MRMDestMem>; // flags = [mem32] & R32 -def TEST8rm : Im8 <"test", 0x84, MRMSrcMem >; // flags = R8 & [mem8] -def TEST16rm : Im16 <"test", 0x85, MRMSrcMem >, OpSize; // flags = R16 & [mem16] -def TEST32rm : Im32 <"test", 0x85, MRMSrcMem >; // flags = R32 & [mem32] - -def TEST8ri : Ii8 <"test", 0xF6, MRM0r >; // flags = R8 & imm8 -def TEST16ri : Ii16 <"test", 0xF7, MRM0r >, OpSize; // flags = R16 & imm16 -def TEST32ri : Ii32 <"test", 0xF7, MRM0r >; // flags = R32 & imm32 -def TEST8mi : Im8i8 <"test", 0xF6, MRM0m >; // flags = [mem8] & imm8 -def TEST16mi : Im16i16<"test", 0xF7, MRM0m >, OpSize; // flags = [mem16] & imm16 -def TEST32mi : Im32i32<"test", 0xF7, MRM0m >; // flags = [mem32] & imm32 +// +let isCommutable = 1 in { // TEST X, Y --> TEST Y, X +def TEST8rr : I<0x84, MRMDestReg, (ops R8:$src1, R8:$src2), + "test{b} {$src2, $src1|$src1, $src2}">; +def TEST16rr : I<0x85, MRMDestReg, (ops R16:$src1, R16:$src2), + "test{w} {$src2, $src1|$src1, $src2}">, OpSize; +def TEST32rr : I<0x85, MRMDestReg, (ops R32:$src1, R32:$src2), + "test{l} {$src2, $src1|$src1, $src2}">; +} +def TEST8mr : I<0x84, MRMDestMem, (ops i8mem :$src1, R8 :$src2), + "test{b} {$src2, $src1|$src1, $src2}">; +def TEST16mr : I<0x85, MRMDestMem, (ops i16mem:$src1, R16:$src2), + "test{w} {$src2, $src1|$src1, $src2}">, OpSize; +def TEST32mr : I<0x85, MRMDestMem, (ops i32mem:$src1, R32:$src2), + "test{l} {$src2, $src1|$src1, $src2}">; +def TEST8rm : I<0x84, MRMSrcMem, (ops R8 :$src1, i8mem :$src2), + "test{b} {$src2, $src1|$src1, $src2}">; +def TEST16rm : I<0x85, MRMSrcMem, (ops R16:$src1, i16mem:$src2), + "test{w} {$src2, $src1|$src1, $src2}">, OpSize; +def TEST32rm : I<0x85, MRMSrcMem, (ops R32:$src1, i32mem:$src2), + "test{l} {$src2, $src1|$src1, $src2}">; + +def TEST8ri : Ii8 <0xF6, MRM0r, // flags = R8 & imm8 + (ops R8:$src1, i8imm:$src2), + "test{b} {$src2, $src1|$src1, $src2}">; +def TEST16ri : Ii16<0xF7, MRM0r, // flags = R16 & imm16 + (ops R16:$src1, i16imm:$src2), + "test{w} {$src2, $src1|$src1, $src2}">, OpSize; +def TEST32ri : Ii32<0xF7, MRM0r, // flags = R32 & imm32 + (ops R32:$src1, i32imm:$src2), + "test{l} {$src2, $src1|$src1, $src2}">; +def TEST8mi : Ii8 <0xF6, MRM0m, // flags = [mem8] & imm8 + (ops i32mem:$src1, i8imm:$src2), + "test{b} {$src2, $src1|$src1, $src2}">; +def TEST16mi : Ii16<0xF7, MRM0m, // flags = [mem16] & imm16 + (ops i16mem:$src1, i16imm:$src2), + "test{w} {$src2, $src1|$src1, $src2}">, OpSize; +def TEST32mi : Ii32<0xF7, MRM0m, // flags = [mem32] & imm32 + (ops i32mem:$src1, i32imm:$src2), + "test{l} {$src2, $src1|$src1, $src2}">; // Condition code ops, incl. set if equal/not equal/... -def SAHF : I <"sahf" , 0x9E, RawFrm>, Imp<[AH],[]>; // flags = AH -def LAHF : I <"lahf" , 0x9F, RawFrm>, Imp<[],[AH]>; // AH = flags - -def SETBr : I <"setb" , 0x92, MRM0r>, TB; // R8 = < unsign -def SETBm : Im8<"setb" , 0x92, MRM0m>, TB; // [mem8] = < unsign -def SETAEr : I <"setae", 0x93, MRM0r>, TB; // R8 = >= unsign -def SETAEm : Im8<"setae", 0x93, MRM0m>, TB; // [mem8] = >= unsign -def SETEr : I <"sete" , 0x94, MRM0r>, TB; // R8 = == -def SETEm : Im8<"sete" , 0x94, MRM0m>, TB; // [mem8] = == -def SETNEr : I <"setne", 0x95, MRM0r>, TB; // R8 = != -def SETNEm : Im8<"setne", 0x95, MRM0m>, TB; // [mem8] = != -def SETBEr : I <"setbe", 0x96, MRM0r>, TB; // R8 = <= unsign -def SETBEm : Im8<"setbe", 0x96, MRM0m>, TB; // [mem8] = <= unsign -def SETAr : I <"seta" , 0x97, MRM0r>, TB; // R8 = > signed -def SETAm : Im8<"seta" , 0x97, MRM0m>, TB; // [mem8] = > signed -def SETSr : I <"sets" , 0x98, MRM0r>, TB; // R8 = -def SETSm : Im8<"sets" , 0x98, MRM0m>, TB; // [mem8] = -def SETNSr : I <"setns", 0x99, MRM0r>, TB; // R8 = ! -def SETNSm : Im8<"setns", 0x99, MRM0m>, TB; // [mem8] = ! -def SETLr : I <"setl" , 0x9C, MRM0r>, TB; // R8 = < signed -def SETLm : Im8<"setl" , 0x9C, MRM0m>, TB; // [mem8] = < signed -def SETGEr : I <"setge", 0x9D, MRM0r>, TB; // R8 = >= signed -def SETGEm : Im8<"setge", 0x9D, MRM0m>, TB; // [mem8] = >= signed -def SETLEr : I <"setle", 0x9E, MRM0r>, TB; // R8 = <= signed -def SETLEm : Im8<"setle", 0x9E, MRM0m>, TB; // [mem8] = <= signed -def SETGr : I <"setg" , 0x9F, MRM0r>, TB; // R8 = < signed -def SETGm : Im8<"setg" , 0x9F, MRM0m>, TB; // [mem8] = < signed +def SAHF : I<0x9E, RawFrm, (ops), "sahf">, Imp<[AH],[]>; // flags = AH +def LAHF : I<0x9F, RawFrm, (ops), "lahf">, Imp<[],[AH]>; // AH = flags + +def SETBr : I<0x92, MRM0r, + (ops R8 :$dst), "setb $dst">, TB; // R8 = < unsign +def SETBm : I<0x92, MRM0m, + (ops i8mem:$dst), "setb $dst">, TB; // [mem8] = < unsign +def SETAEr : I<0x93, MRM0r, + (ops R8 :$dst), "setae $dst">, TB; // R8 = >= unsign +def SETAEm : I<0x93, MRM0m, + (ops i8mem:$dst), "setae $dst">, TB; // [mem8] = >= unsign +def SETEr : I<0x94, MRM0r, + (ops R8 :$dst), "sete $dst">, TB; // R8 = == +def SETEm : I<0x94, MRM0m, + (ops i8mem:$dst), "sete $dst">, TB; // [mem8] = == +def SETNEr : I<0x95, MRM0r, + (ops R8 :$dst), "setne $dst">, TB; // R8 = != +def SETNEm : I<0x95, MRM0m, + (ops i8mem:$dst), "setne $dst">, TB; // [mem8] = != +def SETBEr : I<0x96, MRM0r, + (ops R8 :$dst), "setbe $dst">, TB; // R8 = <= unsign +def SETBEm : I<0x96, MRM0m, + (ops i8mem:$dst), "setbe $dst">, TB; // [mem8] = <= unsign +def SETAr : I<0x97, MRM0r, + (ops R8 :$dst), "seta $dst">, TB; // R8 = > signed +def SETAm : I<0x97, MRM0m, + (ops i8mem:$dst), "seta $dst">, TB; // [mem8] = > signed +def SETSr : I<0x98, MRM0r, + (ops R8 :$dst), "sets $dst">, TB; // R8 = +def SETSm : I<0x98, MRM0m, + (ops i8mem:$dst), "sets $dst">, TB; // [mem8] = +def SETNSr : I<0x99, MRM0r, + (ops R8 :$dst), "setns $dst">, TB; // R8 = ! +def SETNSm : I<0x99, MRM0m, + (ops i8mem:$dst), "setns $dst">, TB; // [mem8] = ! +def SETPr : I<0x9A, MRM0r, + (ops R8 :$dst), "setp $dst">, TB; // R8 = parity +def SETPm : I<0x9A, MRM0m, + (ops i8mem:$dst), "setp $dst">, TB; // [mem8] = parity +def SETNPr : I<0x9B, MRM0r, + (ops R8 :$dst), "setnp $dst">, TB; // R8 = not parity +def SETNPm : I<0x9B, MRM0m, + (ops i8mem:$dst), "setnp $dst">, TB; // [mem8] = not parity +def SETLr : I<0x9C, MRM0r, + (ops R8 :$dst), "setl $dst">, TB; // R8 = < signed +def SETLm : I<0x9C, MRM0m, + (ops i8mem:$dst), "setl $dst">, TB; // [mem8] = < signed +def SETGEr : I<0x9D, MRM0r, + (ops R8 :$dst), "setge $dst">, TB; // R8 = >= signed +def SETGEm : I<0x9D, MRM0m, + (ops i8mem:$dst), "setge $dst">, TB; // [mem8] = >= signed +def SETLEr : I<0x9E, MRM0r, + (ops R8 :$dst), "setle $dst">, TB; // R8 = <= signed +def SETLEm : I<0x9E, MRM0m, + (ops i8mem:$dst), "setle $dst">, TB; // [mem8] = <= signed +def SETGr : I<0x9F, MRM0r, + (ops R8 :$dst), "setg $dst">, TB; // R8 = < signed +def SETGm : I<0x9F, MRM0m, + (ops i8mem:$dst), "setg $dst">, TB; // [mem8] = < signed // Integer comparisons -def CMP8rr : I <"cmp", 0x38, MRMDestReg>; // compare R8, R8 -def CMP16rr : I <"cmp", 0x39, MRMDestReg>, OpSize; // compare R16, R16 -def CMP32rr : I <"cmp", 0x39, MRMDestReg>, // compare R32, R32 - Pattern<(isVoid (unspec2 R32, R32))>; -def CMP8mr : Im8 <"cmp", 0x38, MRMDestMem>; // compare [mem8], R8 -def CMP16mr : Im16 <"cmp", 0x39, MRMDestMem>, OpSize; // compare [mem16], R16 -def CMP32mr : Im32 <"cmp", 0x39, MRMDestMem>; // compare [mem32], R32 -def CMP8rm : Im8 <"cmp", 0x3A, MRMSrcMem >; // compare R8, [mem8] -def CMP16rm : Im16 <"cmp", 0x3B, MRMSrcMem >, OpSize; // compare R16, [mem16] -def CMP32rm : Im32 <"cmp", 0x3B, MRMSrcMem >; // compare R32, [mem32] -def CMP8ri : Ii8 <"cmp", 0x80, MRM7r >; // compare R8, imm8 -def CMP16ri : Ii16 <"cmp", 0x81, MRM7r >, OpSize; // compare R16, imm16 -def CMP32ri : Ii32 <"cmp", 0x81, MRM7r >; // compare R32, imm32 -def CMP8mi : Im8i8 <"cmp", 0x80, MRM7m >; // compare [mem8], imm8 -def CMP16mi : Im16i16<"cmp", 0x81, MRM7m >, OpSize; // compare [mem16], imm16 -def CMP32mi : Im32i32<"cmp", 0x81, MRM7m >; // compare [mem32], imm32 +def CMP8rr : I<0x38, MRMDestReg, + (ops R8 :$src1, R8 :$src2), + "cmp{b} {$src2, $src1|$src1, $src2}">; +def CMP16rr : I<0x39, MRMDestReg, + (ops R16:$src1, R16:$src2), + "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; +def CMP32rr : I<0x39, MRMDestReg, + (ops R32:$src1, R32:$src2), + "cmp{l} {$src2, $src1|$src1, $src2}">; +def CMP8mr : I<0x38, MRMDestMem, + (ops i8mem :$src1, R8 :$src2), + "cmp{b} {$src2, $src1|$src1, $src2}">; +def CMP16mr : I<0x39, MRMDestMem, + (ops i16mem:$src1, R16:$src2), + "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; +def CMP32mr : I<0x39, MRMDestMem, + (ops i32mem:$src1, R32:$src2), + "cmp{l} {$src2, $src1|$src1, $src2}">; +def CMP8rm : I<0x3A, MRMSrcMem, + (ops R8 :$src1, i8mem :$src2), + "cmp{b} {$src2, $src1|$src1, $src2}">; +def CMP16rm : I<0x3B, MRMSrcMem, + (ops R16:$src1, i16mem:$src2), + "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; +def CMP32rm : I<0x3B, MRMSrcMem, + (ops R32:$src1, i32mem:$src2), + "cmp{l} {$src2, $src1|$src1, $src2}">; +def CMP8ri : Ii8<0x80, MRM7r, + (ops R16:$src1, i8imm:$src2), + "cmp{b} {$src2, $src1|$src1, $src2}">; +def CMP16ri : Ii16<0x81, MRM7r, + (ops R16:$src1, i16imm:$src2), + "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; +def CMP32ri : Ii32<0x81, MRM7r, + (ops R32:$src1, i32imm:$src2), + "cmp{l} {$src2, $src1|$src1, $src2}">; +def CMP8mi : Ii8 <0x80, MRM7m, + (ops i8mem :$src1, i8imm :$src2), + "cmp{b} {$src2, $src1|$src1, $src2}">; +def CMP16mi : Ii16<0x81, MRM7m, + (ops i16mem:$src1, i16imm:$src2), + "cmp{w} {$src2, $src1|$src1, $src2}">, OpSize; +def CMP32mi : Ii32<0x81, MRM7m, + (ops i32mem:$src1, i32imm:$src2), + "cmp{l} {$src2, $src1|$src1, $src2}">; // Sign/Zero extenders -def MOVSX16rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB, OpSize; // R16 = signext(R8) -def MOVSX32rr8 : I <"movsx", 0xBE, MRMSrcReg>, TB; // R32 = signext(R8) -def MOVSX32rr16: I <"movsx", 0xBF, MRMSrcReg>, TB; // R32 = signext(R16) -def MOVSX16rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB, OpSize; // R16 = signext([mem8]) -def MOVSX32rm8 : Im8 <"movsx", 0xBE, MRMSrcMem>, TB; // R32 = signext([mem8]) -def MOVSX32rm16: Im16<"movsx", 0xBF, MRMSrcMem>, TB; // R32 = signext([mem16]) - -def MOVZX16rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB, OpSize; // R16 = zeroext(R8) -def MOVZX32rr8 : I <"movzx", 0xB6, MRMSrcReg>, TB; // R32 = zeroext(R8) -def MOVZX32rr16: I <"movzx", 0xB7, MRMSrcReg>, TB; // R32 = zeroext(R16) -def MOVZX16rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB, OpSize; // R16 = zeroext([mem8]) -def MOVZX32rm8 : Im8 <"movzx", 0xB6, MRMSrcMem>, TB; // R32 = zeroext([mem8]) -def MOVZX32rm16: Im16<"movzx", 0xB7, MRMSrcMem>, TB; // R32 = zeroext([mem16]) - +def MOVSX16rr8 : I<0xBE, MRMSrcReg, (ops R16:$dst, R8 :$src), + "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVSX16rm8 : I<0xBE, MRMSrcMem, (ops R16:$dst, i8mem :$src), + "movs{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVSX32rr8 : I<0xBE, MRMSrcReg, (ops R32:$dst, R8 :$src), + "movs{bl|x} {$src, $dst|$dst, $src}">, TB; +def MOVSX32rm8 : I<0xBE, MRMSrcMem, (ops R32:$dst, i8mem :$src), + "movs{bl|x} {$src, $dst|$dst, $src}">, TB; +def MOVSX32rr16: I<0xBF, MRMSrcReg, (ops R32:$dst, R16:$src), + "movs{wl|x} {$src, $dst|$dst, $src}">, TB; +def MOVSX32rm16: I<0xBF, MRMSrcMem, (ops R32:$dst, i16mem:$src), + "movs{wl|x} {$src, $dst|$dst, $src}">, TB; + +def MOVZX16rr8 : I<0xB6, MRMSrcReg, (ops R16:$dst, R8 :$src), + "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVZX16rm8 : I<0xB6, MRMSrcMem, (ops R16:$dst, i8mem :$src), + "movz{bw|x} {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVZX32rr8 : I<0xB6, MRMSrcReg, (ops R32:$dst, R8 :$src), + "movz{bl|x} {$src, $dst|$dst, $src}">, TB; +def MOVZX32rm8 : I<0xB6, MRMSrcMem, (ops R32:$dst, i8mem :$src), + "movz{bl|x} {$src, $dst|$dst, $src}">, TB; +def MOVZX32rr16: I<0xB7, MRMSrcReg, (ops R32:$dst, R16:$src), + "movz{wl|x} {$src, $dst|$dst, $src}">, TB; +def MOVZX32rm16: I<0xB7, MRMSrcMem, (ops R32:$dst, i16mem:$src), + "movz{wl|x} {$src, $dst|$dst, $src}">, TB; //===----------------------------------------------------------------------===// -// Floating point support +// XMM Floating point support (requires SSE2) //===----------------------------------------------------------------------===// -// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP' +def MOVSSrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f32mem:$src), + "movss {$src, $dst|$dst, $src}">, XS; +def MOVSSmr : I<0x11, MRMDestMem, (ops f32mem:$dst, RXMM:$src), + "movss {$src, $dst|$dst, $src}">, XS; +def MOVSDrm : I<0x10, MRMSrcMem, (ops RXMM:$dst, f64mem:$src), + "movsd {$src, $dst|$dst, $src}">, XD; +def MOVSDmr : I<0x11, MRMDestMem, (ops f64mem:$dst, RXMM:$src), + "movsd {$src, $dst|$dst, $src}">, XD; +def MOVAPSrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "movaps {$src, $dst|$dst, $src}">, TB; +def MOVAPSrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f32mem:$src), + "movaps {$src, $dst|$dst, $src}">, TB; +def MOVAPSmr: I<0x29, MRMDestMem, (ops f32mem:$dst, RXMM:$src), + "movaps {$src, $dst|$dst, $src}">, TB; +def MOVAPDrr: I<0x28, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "movapd {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVAPDrm: I<0x28, MRMSrcMem, (ops RXMM:$dst, f64mem:$src), + "movapd {$src, $dst|$dst, $src}">, TB, OpSize; +def MOVAPDmr: I<0x29, MRMDestMem, (ops f64mem:$dst, RXMM:$src), + "movapd {$src, $dst|$dst, $src}">, TB, OpSize; + +def CVTTSD2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src), + "cvttsd2si {$src, $dst|$dst, $src}">, XD; +def CVTTSD2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f64mem:$src), + "cvttsd2si {$src, $dst|$dst, $src}">, XD; +def CVTTSS2SIrr: I<0x2C, MRMSrcReg, (ops R32:$dst, RXMM:$src), + "cvttss2si {$src, $dst|$dst, $src}">, XS; +def CVTTSS2SIrm: I<0x2C, MRMSrcMem, (ops R32:$dst, f32mem:$src), + "cvttss2si {$src, $dst|$dst, $src}">, XS; +def CVTSD2SSrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "cvtsd2ss {$src, $dst|$dst, $src}">, XS; +def CVTSD2SSrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f64mem:$src), + "cvtsd2ss {$src, $dst|$dst, $src}">, XS; +def CVTSS2SDrr: I<0x5A, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "cvtss2sd {$src, $dst|$dst, $src}">, XD; +def CVTSS2SDrm: I<0x5A, MRMSrcMem, (ops RXMM:$dst, f32mem:$src), + "cvtss2sd {$src, $dst|$dst, $src}">, XD; +def CVTSI2SSrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src), + "cvtsi2ss {$src, $dst|$dst, $src}">, XS; +def CVTSI2SSrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f32mem:$src), + "cvtsi2ss {$src, $dst|$dst, $src}">, XS; +def CVTSI2SDrr: I<0x2A, MRMSrcReg, (ops R32:$dst, RXMM:$src), + "cvtsi2sd {$src, $dst|$dst, $src}">, XD; +def CVTSI2SDrm: I<0x2A, MRMSrcMem, (ops R32:$dst, f64mem:$src), + "cvtsi2sd {$src, $dst|$dst, $src}">, XD; + +def SQRTSSrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f32mem:$src), + "subss {$src, $dst|$dst, $src}">, XS; +def SQRTSSrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "subss {$src, $dst|$dst, $src}">, XS; +def SQRTSDrm : I<0x51, MRMSrcMem, (ops RXMM:$dst, f64mem:$src), + "subsd {$src, $dst|$dst, $src}">, XD; +def SQRTSDrr : I<0x51, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "subsd {$src, $dst|$dst, $src}">, XD; + +def UCOMISDrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize; +def UCOMISDrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f64mem:$src), + "ucomisd {$src, $dst|$dst, $src}">, TB, OpSize; +def UCOMISSrr: I<0x2E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src), + "ucomiss {$src, $dst|$dst, $src}">, TB; +def UCOMISSrm: I<0x2E, MRMSrcMem, (ops RXMM:$dst, f32mem:$src), + "ucomiss {$src, $dst|$dst, $src}">, TB; -// Floating point instruction templates -class FPInst o, Format F, FPFormat fp, MemType m, ImmType i> - : X86Inst { let FPForm = fp; let FPFormBits = FPForm.Value; } +let isTwoAddress = 1 in { +let isCommutable = 1 in { +def ADDSSrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "addss {$src, $dst|$dst, $src}">, XS; +def ADDSDrr : I<0x58, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "addsd {$src, $dst|$dst, $src}">, XD; +def ANDPSrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "andps {$src, $dst|$dst, $src}">, TB; +def ANDPDrr : I<0x54, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "andpd {$src, $dst|$dst, $src}">, TB, OpSize; +def MULSSrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "mulss {$src, $dst|$dst, $src}">, XS; +def MULSDrr : I<0x59, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "mulsd {$src, $dst|$dst, $src}">, XD; +def ORPSrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "orps {$src, $dst|$dst, $src}">, TB; +def ORPDrr : I<0x56, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "orpd {$src, $dst|$dst, $src}">, TB, OpSize; +} +def ANDNPSrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "andnps {$src, $dst|$dst, $src}">, TB; +def ANDNPDrr : I<0x55, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "andnpd {$src, $dst|$dst, $src}">, TB, OpSize; +def ADDSSrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src), + "addss {$src, $dst|$dst, $src}">, XS; +def ADDSDrm : I<0x58, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src), + "addsd {$src, $dst|$dst, $src}">, XD; +def MULSSrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src), + "mulss {$src, $dst|$dst, $src}">, XS; +def MULSDrm : I<0x59, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src), + "mulsd {$src, $dst|$dst, $src}">, XD; + +def DIVSSrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src), + "divss {$src, $dst|$dst, $src}">, XS; +def DIVSSrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "divss {$src, $dst|$dst, $src}">, XS; +def DIVSDrm : I<0x5E, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src), + "divsd {$src, $dst|$dst, $src}">, XD; +def DIVSDrr : I<0x5E, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "divsd {$src, $dst|$dst, $src}">, XD; + +def SUBSSrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f32mem:$src), + "subss {$src, $dst|$dst, $src}">, XS; +def SUBSSrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "subss {$src, $dst|$dst, $src}">, XS; +def SUBSDrm : I<0x5C, MRMSrcMem, (ops RXMM:$dst, RXMM:$src1, f64mem:$src), + "subsd {$src, $dst|$dst, $src}">, XD; +def SUBSDrr : I<0x5C, MRMSrcReg, (ops RXMM:$dst, RXMM:$src1, RXMM:$src), + "subsd {$src, $dst|$dst, $src}">, XD; + +def CMPSSrr : I<0xC2, MRMSrcReg, + (ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc), + "cmp${cc}ss {$src, $dst|$dst, $src}">, XS; +def CMPSSrm : I<0xC2, MRMSrcMem, + (ops RXMM:$dst, RXMM:$src1, f32mem:$src, SSECC:$cc), + "cmp${cc}ss {$src, $dst|$dst, $src}">, XS; +def CMPSDrr : I<0xC2, MRMSrcReg, + (ops RXMM:$dst, RXMM:$src1, RXMM:$src, SSECC:$cc), + "cmp${cc}sd {$src, $dst|$dst, $src}">, XD; +def CMPSDrm : I<0xC2, MRMSrcMem, + (ops RXMM:$dst, RXMM:$src1, f64mem:$src, SSECC:$cc), + "cmp${cc}sd {$src, $dst|$dst, $src}">, XD; +} -class FPI o, Format F, FPFormat fp> : FPInst; +//===----------------------------------------------------------------------===// +// Stack-based Floating point support +//===----------------------------------------------------------------------===// -class FPIM o, Format F, FPFormat fp, MemType m> : FPInst; +// FIXME: These need to indicate mod/ref sets for FP regs... & FP 'TOP' -class FPI16m o, Format F, FPFormat fp> : FPIM; -class FPI32m o, Format F, FPFormat fp> : FPIM; -class FPI64m o, Format F, FPFormat fp> : FPIM; -class FPI80m o, Format F, FPFormat fp> : FPIM; +// Floating point instruction template +class FPI o, Format F, FPFormat fp, dag ops, string asm> + : X86Inst { + let FPForm = fp; let FPFormBits = FPForm.Value; +} // Pseudo instructions for floating point. We use these pseudo instructions // because they can be expanded by the fp spackifier into one of many different // forms of instructions for doing these operations. Until the stackifier runs, // we prefer to be abstract. -def FpMOV : FPI<"FMOV", 0, Pseudo, SpecialFP>; // f1 = fmov f2 -def FpADD : FPI<"FADD", 0, Pseudo, TwoArgFP>; // f1 = fadd f2, f3 -def FpSUB : FPI<"FSUB", 0, Pseudo, TwoArgFP>; // f1 = fsub f2, f3 -def FpMUL : FPI<"FMUL", 0, Pseudo, TwoArgFP>; // f1 = fmul f2, f3 -def FpDIV : FPI<"FDIV", 0, Pseudo, TwoArgFP>; // f1 = fdiv f2, f3 - -def FpUCOM : FPI<"FUCOM", 0, Pseudo, TwoArgFP>; // FPSW = fucom f1, f2 -def FpGETRESULT : FPI<"FGETRESULT",0, Pseudo, SpecialFP>; // FPR = ST(0) -def FpSETRESULT : FPI<"FSETRESULT",0, Pseudo, SpecialFP>; // ST(0) = FPR - -// FADD reg, mem: Before stackification, these are represented by: R1 = FADD* R2, [mem] -def FADD32m : FPI32m<"fadd", 0xD8, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32real] -def FADD64m : FPI64m<"fadd", 0xDC, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem64real] -def FIADD16m : FPI16m<"fiadd", 0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int] -def FIADD32m : FPI32m<"fiadd", 0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int] - -// FMUL reg, mem: Before stackification, these are represented by: R1 = FMUL* R2, [mem] -def FMUL32m : FPI32m<"fmul", 0xD8, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32real] -def FMUL64m : FPI64m<"fmul", 0xDC, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem64real] -def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem16int] -def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; // ST(0) = ST(0) * [mem32int] - -// FSUB reg, mem: Before stackification, these are represented by: R1 = FSUB* R2, [mem] -def FSUB32m : FPI32m<"fsub", 0xD8, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32real] -def FSUB64m : FPI64m<"fsub", 0xDC, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem64real] -def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem16int] -def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; // ST(0) = ST(0) - [mem32int] - -// FSUBR reg, mem: Before stackification, these are represented by: R1 = FSUBR* R2, [mem] -// Note that the order of operands does not reflect the operation being performed. -def FSUBR32m : FPI32m<"fsubr", 0xD8, MRM5m, OneArgFPRW>; // ST(0) = [mem32real] - ST(0) -def FSUBR64m : FPI64m<"fsubr", 0xDC, MRM5m, OneArgFPRW>; // ST(0) = [mem64real] - ST(0) -def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; // ST(0) = [mem16int] - ST(0) -def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; // ST(0) = [mem32int] - ST(0) - -// FDIV reg, mem: Before stackification, these are represented by: R1 = FDIV* R2, [mem] -def FDIV32m : FPI32m<"fdiv", 0xD8, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32real] -def FDIV64m : FPI64m<"fdiv", 0xDC, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem64real] -def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem16int] -def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; // ST(0) = ST(0) / [mem32int] - -// FDIVR reg, mem: Before stackification, these are represented by: R1 = FDIVR* R2, [mem] -// Note that the order of operands does not reflect the operation being performed. -def FDIVR32m : FPI32m<"fdivr", 0xD8, MRM7m, OneArgFPRW>; // ST(0) = [mem32real] / ST(0) -def FDIVR64m : FPI64m<"fdivr", 0xDC, MRM7m, OneArgFPRW>; // ST(0) = [mem64real] / ST(0) -def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; // ST(0) = [mem16int] / ST(0) -def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // ST(0) = [mem32int] / ST(0) +def FpMOV : FPI<0, Pseudo, SpecialFP, + (ops RFP, RFP), "">; // f1 = fmov f2 +def FpADD : FPI<0, Pseudo, TwoArgFP , + (ops RFP, RFP, RFP), "">; // f1 = fadd f2, f3 +def FpSUB : FPI<0, Pseudo, TwoArgFP , + (ops RFP, RFP, RFP), "">; // f1 = fsub f2, f3 +def FpMUL : FPI<0, Pseudo, TwoArgFP , + (ops RFP, RFP, RFP), "">; // f1 = fmul f2, f3 +def FpDIV : FPI<0, Pseudo, TwoArgFP , + (ops RFP, RFP, RFP), "">; // f1 = fdiv f2, f3 + +def FpGETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, + Imp<[ST0], []>; // FPR = ST(0) + +def FpSETRESULT : FPI<0, Pseudo, SpecialFP, (ops RFP), "">, + Imp<[], [ST0]>; // ST(0) = FPR + +// FADD reg, mem: Before stackification, these are represented by: +// R1 = FADD* R2, [mem] +def FADD32m : FPI<0xD8, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem32real] + (ops f32mem:$src), "fadd{s} $src">; +def FADD64m : FPI<0xDC, MRM0m, OneArgFPRW, // ST(0) = ST(0) + [mem64real] + (ops f64mem:$src), "fadd{l} $src">; +//def FIADD16m : FPI<0xDE, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem16int] +//def FIADD32m : FPI<0xDA, MRM0m, OneArgFPRW>; // ST(0) = ST(0) + [mem32int] + +// FMUL reg, mem: Before stackification, these are represented by: +// R1 = FMUL* R2, [mem] +def FMUL32m : FPI<0xD8, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem32real] + (ops f32mem:$src), "fmul{s} $src">; +def FMUL64m : FPI<0xDC, MRM1m, OneArgFPRW, // ST(0) = ST(0) * [mem64real] + (ops f64mem:$src), "fmul{l} $src">; +// ST(0) = ST(0) * [mem16int] +//def FIMUL16m : FPI16m<"fimul", 0xDE, MRM1m, OneArgFPRW>; +// ST(0) = ST(0) * [mem32int] +//def FIMUL32m : FPI32m<"fimul", 0xDA, MRM1m, OneArgFPRW>; + +// FSUB reg, mem: Before stackification, these are represented by: +// R1 = FSUB* R2, [mem] +def FSUB32m : FPI<0xD8, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem32real] + (ops f32mem:$src), "fsub{s} $src">; +def FSUB64m : FPI<0xDC, MRM4m, OneArgFPRW, // ST(0) = ST(0) - [mem64real] + (ops f64mem:$src), "fsub{l} $src">; +// ST(0) = ST(0) - [mem16int] +//def FISUB16m : FPI16m<"fisub", 0xDE, MRM4m, OneArgFPRW>; +// ST(0) = ST(0) - [mem32int] +//def FISUB32m : FPI32m<"fisub", 0xDA, MRM4m, OneArgFPRW>; + +// FSUBR reg, mem: Before stackification, these are represented by: +// R1 = FSUBR* R2, [mem] + +// Note that the order of operands does not reflect the operation being +// performed. +def FSUBR32m : FPI<0xD8, MRM5m, OneArgFPRW, // ST(0) = [mem32real] - ST(0) + (ops f32mem:$src), "fsubr{s} $src">; +def FSUBR64m : FPI<0xDC, MRM5m, OneArgFPRW, // ST(0) = [mem64real] - ST(0) + (ops f64mem:$src), "fsubr{l} $src">; +// ST(0) = [mem16int] - ST(0) +//def FISUBR16m : FPI16m<"fisubr", 0xDE, MRM5m, OneArgFPRW>; +// ST(0) = [mem32int] - ST(0) +//def FISUBR32m : FPI32m<"fisubr", 0xDA, MRM5m, OneArgFPRW>; + +// FDIV reg, mem: Before stackification, these are represented by: +// R1 = FDIV* R2, [mem] +def FDIV32m : FPI<0xD8, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem32real] + (ops f32mem:$src), "fdiv{s} $src">; +def FDIV64m : FPI<0xDC, MRM6m, OneArgFPRW, // ST(0) = ST(0) / [mem64real] + (ops f64mem:$src), "fdiv{l} $src">; +// ST(0) = ST(0) / [mem16int] +//def FIDIV16m : FPI16m<"fidiv", 0xDE, MRM6m, OneArgFPRW>; +// ST(0) = ST(0) / [mem32int] +//def FIDIV32m : FPI32m<"fidiv", 0xDA, MRM6m, OneArgFPRW>; + +// FDIVR reg, mem: Before stackification, these are represented by: +// R1 = FDIVR* R2, [mem] +// Note that the order of operands does not reflect the operation being +// performed. +def FDIVR32m : FPI<0xD8, MRM7m, OneArgFPRW, // ST(0) = [mem32real] / ST(0) + (ops f32mem:$src), "fdivr{s} $src">; +def FDIVR64m : FPI<0xDC, MRM7m, OneArgFPRW, // ST(0) = [mem64real] / ST(0) + (ops f64mem:$src), "fdivr{l} $src">; +// ST(0) = [mem16int] / ST(0) +//def FIDIVR16m : FPI16m<"fidivr", 0xDE, MRM7m, OneArgFPRW>; +// ST(0) = [mem32int] / ST(0) +//def FIDIVR32m : FPI32m<"fidivr", 0xDA, MRM7m, OneArgFPRW>; // Floating point cmovs... -let isTwoAddress = 1, Uses = [ST0], Defs = [ST0], printImplicitUsesBefore = 1 in { - def FCMOVB : FPI <"fcmovb" , 0xC0, AddRegFrm, CondMovFP>, DA; // fcmovb ST(i) -> ST(0) - def FCMOVBE : FPI <"fcmovbe", 0xD0, AddRegFrm, CondMovFP>, DA; // fcmovbe ST(i) -> ST(0) - def FCMOVE : FPI <"fcmove" , 0xC8, AddRegFrm, CondMovFP>, DA; // fcmove ST(i) -> ST(0) - def FCMOVAE : FPI <"fcmovae", 0xC0, AddRegFrm, CondMovFP>, DB; // fcmovae ST(i) -> ST(0) - def FCMOVA : FPI <"fcmova" , 0xD0, AddRegFrm, CondMovFP>, DB; // fcmova ST(i) -> ST(0) - def FCMOVNE : FPI <"fcmovne", 0xC8, AddRegFrm, CondMovFP>, DB; // fcmovne ST(i) -> ST(0) +let isTwoAddress = 1, Uses = [ST0], Defs = [ST0] in { + def FCMOVB : FPI<0xC0, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovb {$op, %ST(0)|%ST(0), $op}">, DA; + def FCMOVBE : FPI<0xD0, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovbe {$op, %ST(0)|%ST(0), $op}">, DA; + def FCMOVE : FPI<0xC8, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmove {$op, %ST(0)|%ST(0), $op}">, DA; + def FCMOVP : FPI<0xD8, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovu {$op, %ST(0)|%ST(0), $op}">, DA; + def FCMOVAE : FPI<0xC0, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovae {$op, %ST(0)|%ST(0), $op}">, DB; + def FCMOVA : FPI<0xD0, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmova {$op, %ST(0)|%ST(0), $op}">, DB; + def FCMOVNE : FPI<0xC8, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovne {$op, %ST(0)|%ST(0), $op}">, DB; + def FCMOVNP : FPI<0xD8, AddRegFrm, CondMovFP, + (ops RST:$op), "fcmovnu {$op, %ST(0)|%ST(0), $op}">, DB; } // Floating point loads & stores... -def FLDrr : FPI <"fld" , 0xC0, AddRegFrm, NotFP>, D9; // push(ST(i)) -def FLD32m : FPI32m <"fld" , 0xD9, MRM0m , ZeroArgFP>; // load float -def FLD64m : FPI64m <"fld" , 0xDD, MRM0m , ZeroArgFP>; // load double -def FLD80m : FPI80m <"fld" , 0xDB, MRM5m , ZeroArgFP>; // load extended -def FILD16m : FPI16m <"fild" , 0xDF, MRM0m , ZeroArgFP>; // load signed short -def FILD32m : FPI32m <"fild" , 0xDB, MRM0m , ZeroArgFP>; // load signed int -def FILD64m : FPI64m <"fild" , 0xDF, MRM5m , ZeroArgFP>; // load signed long - -def FSTrr : FPI <"fst" , 0xD0, AddRegFrm, NotFP >, DD; // ST(i) = ST(0) -def FSTPrr : FPI <"fstp", 0xD8, AddRegFrm, NotFP >, DD; // ST(i) = ST(0), pop -def FST32m : FPI32m <"fst" , 0xD9, MRM2m , OneArgFP>; // store float -def FST64m : FPI64m <"fst" , 0xDD, MRM2m , OneArgFP>; // store double -def FSTP32m : FPI32m <"fstp", 0xD9, MRM3m , OneArgFP>; // store float, pop -def FSTP64m : FPI64m <"fstp", 0xDD, MRM3m , OneArgFP>; // store double, pop -def FSTP80m : FPI80m <"fstp", 0xDB, MRM7m , OneArgFP>; // store extended, pop - -def FIST16m : FPI16m <"fist", 0xDF, MRM2m , OneArgFP>; // store signed short -def FIST32m : FPI32m <"fist", 0xDB, MRM2m , OneArgFP>; // store signed int -def FISTP16m : FPI16m <"fistp", 0xDF, MRM3m , NotFP >; // store signed short, pop -def FISTP32m : FPI32m <"fistp", 0xDB, MRM3m , NotFP >; // store signed int, pop -def FISTP64m : FPI64m <"fistpll", 0xDF, MRM7m , OneArgFP>; // store signed long, pop - -def FXCH : FPI <"fxch", 0xC8, AddRegFrm, NotFP>, D9; // fxch ST(i), ST(0) +def FLDrr : FPI<0xC0, AddRegFrm, NotFP, (ops RST:$src), "fld $src">, D9; +def FLD32m : FPI<0xD9, MRM0m, ZeroArgFP, (ops f32mem:$src), "fld{s} $src">; +def FLD64m : FPI<0xDD, MRM0m, ZeroArgFP, (ops f64mem:$src), "fld{l} $src">; +def FLD80m : FPI<0xDB, MRM5m, ZeroArgFP, (ops f80mem:$src), "fld{t} $src">; +def FILD16m : FPI<0xDF, MRM0m, ZeroArgFP, (ops i16mem:$src), "fild{s} $src">; +def FILD32m : FPI<0xDB, MRM0m, ZeroArgFP, (ops i32mem:$src), "fild{l} $src">; +def FILD64m : FPI<0xDF, MRM5m, ZeroArgFP, (ops i64mem:$src), "fild{ll} $src">; + +def FSTrr : FPI<0xD0, AddRegFrm, NotFP, (ops RST:$op), "fst $op">, DD; +def FSTPrr : FPI<0xD8, AddRegFrm, NotFP, (ops RST:$op), "fstp $op">, DD; +def FST32m : FPI<0xD9, MRM2m, OneArgFP, (ops f32mem:$op), "fst{s} $op">; +def FST64m : FPI<0xDD, MRM2m, OneArgFP, (ops f64mem:$op), "fst{l} $op">; +def FSTP32m : FPI<0xD9, MRM3m, OneArgFP, (ops f32mem:$op), "fstp{s} $op">; +def FSTP64m : FPI<0xDD, MRM3m, OneArgFP, (ops f64mem:$op), "fstp{l} $op">; +def FSTP80m : FPI<0xDB, MRM7m, OneArgFP, (ops f80mem:$op), "fstp{t} $op">; + +def FIST16m : FPI<0xDF, MRM2m , OneArgFP, (ops i16mem:$op), "fist{s} $op">; +def FIST32m : FPI<0xDB, MRM2m , OneArgFP, (ops i32mem:$op), "fist{l} $op">; +def FISTP16m : FPI<0xDF, MRM3m , NotFP , (ops i16mem:$op), "fistp{s} $op">; +def FISTP32m : FPI<0xDB, MRM3m , NotFP , (ops i32mem:$op), "fistp{l} $op">; +def FISTP64m : FPI<0xDF, MRM7m , OneArgFP, (ops i64mem:$op), "fistp{ll} $op">; + +def FXCH : FPI<0xC8, AddRegFrm, NotFP, + (ops RST:$op), "fxch $op">, D9; // fxch ST(i), ST(0) // Floating point constant loads... -def FLD0 : FPI<"fldz", 0xEE, RawFrm, ZeroArgFP>, D9; -def FLD1 : FPI<"fld1", 0xE8, RawFrm, ZeroArgFP>, D9; +def FLD0 : FPI<0xEE, RawFrm, ZeroArgFP, (ops), "fldz">, D9; +def FLD1 : FPI<0xE8, RawFrm, ZeroArgFP, (ops), "fld1">, D9; // Unary operations... -def FCHS : FPI<"fchs", 0xE0, RawFrm, OneArgFPRW>, D9; // f1 = fchs f2 -def FTST : FPI<"ftst", 0xE4, RawFrm, OneArgFP>, D9; // ftst ST(0) +def FCHS : FPI<0xE0, RawFrm, OneArgFPRW, (ops), "fchs" >, D9; // f1 = fchs f2 +def FABS : FPI<0xE1, RawFrm, OneArgFPRW, (ops), "fabs" >, D9; // f1 = fabs f2 +def FSQRT : FPI<0xFA, RawFrm, OneArgFPRW, (ops), "fsqrt">, D9; // fsqrt ST(0) +def FSIN : FPI<0xFE, RawFrm, OneArgFPRW, (ops), "fsin" >, D9; // fsin ST(0) +def FCOS : FPI<0xFF, RawFrm, OneArgFPRW, (ops), "fcos" >, D9; // fcos ST(0) +def FTST : FPI<0xE4, RawFrm, OneArgFP , (ops), "ftst" >, D9; // ftst ST(0) // Binary arithmetic operations... -class FPST0rInst o> : I, D8 { +class FPST0rInst o, dag ops, string asm> + : I, D8 { list Uses = [ST0]; list Defs = [ST0]; } -class FPrST0Inst o> : I, DC { - bit printImplicitUsesAfter = 1; +class FPrST0Inst o, dag ops, string asm> + : I, DC { list Uses = [ST0]; } -class FPrST0PInst o> : I, DE { +class FPrST0PInst o, dag ops, string asm> + : I, DE { list Uses = [ST0]; } -def FADDST0r : FPST0rInst <"fadd", 0xC0>; -def FADDrST0 : FPrST0Inst <"fadd", 0xC0>; -def FADDPrST0 : FPrST0PInst<"faddp", 0xC0>; - -def FSUBRST0r : FPST0rInst <"fsubr", 0xE8>; -def FSUBrST0 : FPrST0Inst <"fsub", 0xE8>; -def FSUBPrST0 : FPrST0PInst<"fsubp", 0xE8>; - -def FSUBST0r : FPST0rInst <"fsub", 0xE0>; -def FSUBRrST0 : FPrST0Inst <"fsubr", 0xE0>; -def FSUBRPrST0 : FPrST0PInst<"fsubrp", 0xE0>; - -def FMULST0r : FPST0rInst <"fmul", 0xC8>; -def FMULrST0 : FPrST0Inst <"fmul", 0xC8>; -def FMULPrST0 : FPrST0PInst<"fmulp", 0xC8>; - -def FDIVRST0r : FPST0rInst <"fdivr", 0xF8>; -def FDIVrST0 : FPrST0Inst <"fdiv", 0xF8>; -def FDIVPrST0 : FPrST0PInst<"fdivp", 0xF8>; - -def FDIVST0r : FPST0rInst <"fdiv", 0xF0>; // ST(0) = ST(0) / ST(i) -def FDIVRrST0 : FPrST0Inst <"fdivr", 0xF0>; // ST(i) = ST(0) / ST(i) -def FDIVRPrST0 : FPrST0PInst<"fdivrp", 0xF0>; // ST(i) = ST(0) / ST(i), pop +def FADDST0r : FPST0rInst <0xC0, (ops RST:$op), + "fadd $op">; +def FADDrST0 : FPrST0Inst <0xC0, (ops RST:$op), + "fadd {%ST(0), $op|$op, %ST(0)}">; +def FADDPrST0 : FPrST0PInst<0xC0, (ops RST:$op), + "faddp $op">; + +// NOTE: GAS and apparently all other AT&T style assemblers have a broken notion +// of some of the 'reverse' forms of the fsub and fdiv instructions. As such, +// we have to put some 'r's in and take them out of weird places. +def FSUBRST0r : FPST0rInst <0xE8, (ops RST:$op), + "fsubr $op">; +def FSUBrST0 : FPrST0Inst <0xE8, (ops RST:$op), + "fsub{r} {%ST(0), $op|$op, %ST(0)}">; +def FSUBPrST0 : FPrST0PInst<0xE8, (ops RST:$op), + "fsub{r}p $op">; + +def FSUBST0r : FPST0rInst <0xE0, (ops RST:$op), + "fsub $op">; +def FSUBRrST0 : FPrST0Inst <0xE0, (ops RST:$op), + "fsub{|r} {%ST(0), $op|$op, %ST(0)}">; +def FSUBRPrST0 : FPrST0PInst<0xE0, (ops RST:$op), + "fsub{|r}p $op">; + +def FMULST0r : FPST0rInst <0xC8, (ops RST:$op), + "fmul $op">; +def FMULrST0 : FPrST0Inst <0xC8, (ops RST:$op), + "fmul {%ST(0), $op|$op, %ST(0)}">; +def FMULPrST0 : FPrST0PInst<0xC8, (ops RST:$op), + "fmulp $op">; + +def FDIVRST0r : FPST0rInst <0xF8, (ops RST:$op), + "fdivr $op">; +def FDIVrST0 : FPrST0Inst <0xF8, (ops RST:$op), + "fdiv{r} {%ST(0), $op|$op, %ST(0)}">; +def FDIVPrST0 : FPrST0PInst<0xF8, (ops RST:$op), + "fdiv{r}p $op">; + +def FDIVST0r : FPST0rInst <0xF0, (ops RST:$op), // ST(0) = ST(0) / ST(i) + "fdiv $op">; +def FDIVRrST0 : FPrST0Inst <0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i) + "fdiv{|r} {%ST(0), $op|$op, %ST(0)}">; +def FDIVRPrST0 : FPrST0PInst<0xF0, (ops RST:$op), // ST(i) = ST(0) / ST(i), pop + "fdiv{|r}p $op">; // Floating point compares -def FUCOMr : I<"fucom" , 0xE0, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i) -def FUCOMPr : I<"fucomp" , 0xE8, AddRegFrm>, DD, Imp<[ST0],[]>; // FPSW = compare ST(0) with ST(i), pop -def FUCOMPPr : I<"fucompp", 0xE9, RawFrm >, DA, Imp<[ST0],[]>; // compare ST(0) with ST(1), pop, pop +def FUCOMr : FPI<0xE0, AddRegFrm, CompareFP, // FPSW = cmp ST(0) with ST(i) + (ops RST:$reg), + "fucom $reg">, DD, Imp<[ST0],[]>; +def FUCOMPr : I<0xE8, AddRegFrm, + (ops RST:$reg), // FPSW = cmp ST(0) with ST(i), pop + "fucomp $reg">, DD, Imp<[ST0],[]>; +def FUCOMPPr : I<0xE9, RawFrm, + (ops), // cmp ST(0) with ST(1), pop, pop + "fucompp">, DA, Imp<[ST0],[]>; + +def FUCOMIr : FPI<0xE8, AddRegFrm, CompareFP, // CC = cmp ST(0) with ST(i) + (ops RST:$reg), + "fucomi {$reg, %ST(0)|%ST(0), $reg}">, DB, Imp<[ST0],[]>; +def FUCOMIPr : I<0xE8, AddRegFrm, // CC = cmp ST(0) with ST(i), pop + (ops RST:$reg), + "fucomip {$reg, %ST(0)|%ST(0), $reg}">, DF, Imp<[ST0],[]>; -let printImplicitUsesBefore = 1 in { - def FUCOMIr : FPI<"fucomi", 0xE8, AddRegFrm, TwoArgFP>, DB, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i) - def FUCOMIPr : I<"fucomip" , 0xE8, AddRegFrm>, DF, Imp<[ST0],[]>; // CC = compare ST(0) with ST(i), pop -} // Floating point flag ops -def FNSTSW8r : I <"fnstsw" , 0xE0, RawFrm>, DF, Imp<[],[AX]>; // AX = fp flags -def FNSTCW16m : Im16<"fnstcw" , 0xD9, MRM7m >; // [mem16] = X87 control world -def FLDCW16m : Im16<"fldcw" , 0xD9, MRM5m >; // X87 control world = [mem16] - - -//===----------------------------------------------------------------------===// -// Instruction Expanders -// - -def RET_R32 : Expander<(ret R32:$reg), - [(MOV32rr EAX, R32:$reg), - (RET)]>; - -// FIXME: This should eventually just be implemented by defining a frameidx as a -// value address for a load. -def LOAD_FI16 : Expander<(set R16:$dest, (load frameidx:$fi)), - [(MOV16rm R16:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>; - -def LOAD_FI32 : Expander<(set R32:$dest, (load frameidx:$fi)), - [(MOV32rm R32:$dest, frameidx:$fi, 1, 0/*NoReg*/, 0)]>; - - -def LOAD_R16 : Expander<(set R16:$dest, (load R32:$src)), - [(MOV16rm R16:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>; - -def LOAD_R32 : Expander<(set R32:$dest, (load R32:$src)), - [(MOV32rm R32:$dest, R32:$src, 1, 0/*NoReg*/, 0)]>; +def FNSTSW8r : I<0xE0, RawFrm, // AX = fp flags + (ops), "fnstsw">, DF, Imp<[],[AX]>; -def BR_EQ : Expander<(brcond (seteq R32:$a1, R32:$a2), - basicblock:$d1, basicblock:$d2), - [(CMP32rr R32:$a1, R32:$a2), - (JE basicblock:$d1), - (JMP basicblock:$d2)]>; +def FNSTCW16m : I<0xD9, MRM7m, // [mem16] = X87 control world + (ops i16mem:$dst), "fnstcw $dst">; +def FLDCW16m : I<0xD9, MRM5m, // X87 control world = [mem16] + (ops i16mem:$dst), "fldcw $dst">;