X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86RegisterInfo.cpp;h=310290213f72084971d4a364ea61ab874a7c4801;hb=92722533819ab838d958966d0e40a60030bb3c16;hp=1e5441794a614a4cda1da9a3b950970715ef4d80;hpb=69244300b8a0112efb44b6273ecea4ca6264b8cf;p=oota-llvm.git diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp index 1e5441794a6..310290213f7 100644 --- a/lib/Target/X86/X86RegisterInfo.cpp +++ b/lib/Target/X86/X86RegisterInfo.cpp @@ -7,8 +7,9 @@ // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. This -// file is responsible for the frame pointer elimination optimization on X86. +// This file contains the X86 implementation of the TargetRegisterInfo class. +// This file is responsible for the frame pointer elimination optimization +// on X86. // //===----------------------------------------------------------------------===// @@ -24,6 +25,7 @@ #include "llvm/CodeGen/ValueTypes.h" #include "llvm/CodeGen/MachineInstrBuilder.h" #include "llvm/CodeGen/MachineFunction.h" +#include "llvm/CodeGen/MachineFunctionPass.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineLocation.h" #include "llvm/CodeGen/MachineModuleInfo.h" @@ -35,15 +37,22 @@ #include "llvm/Target/TargetOptions.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/STLExtras.h" +#include "llvm/Support/Compiler.h" using namespace llvm; X86RegisterInfo::X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii) - : X86GenRegisterInfo(X86::ADJCALLSTACKDOWN, X86::ADJCALLSTACKUP), + : X86GenRegisterInfo(tm.getSubtarget().is64Bit() ? + X86::ADJCALLSTACKDOWN64 : + X86::ADJCALLSTACKDOWN32, + tm.getSubtarget().is64Bit() ? + X86::ADJCALLSTACKUP64 : + X86::ADJCALLSTACKUP32), TM(tm), TII(tii) { // Cache some information. const X86Subtarget *Subtarget = &TM.getSubtarget(); Is64Bit = Subtarget->is64Bit(); + IsWin64 = Subtarget->isTargetWin64(); StackAlign = TM.getFrameInfo()->getStackAlignment(); if (Is64Bit) { SlotSize = 8; @@ -64,12 +73,15 @@ int X86RegisterInfo::getDwarfRegNum(unsigned RegNo, bool isEH) const { unsigned Flavour = DWARFFlavour::X86_64; if (!Subtarget->is64Bit()) { if (Subtarget->isTargetDarwin()) { - Flavour = DWARFFlavour::X86_32_Darwin; + if (isEH) + Flavour = DWARFFlavour::X86_32_DarwinEH; + else + Flavour = DWARFFlavour::X86_32_Generic; } else if (Subtarget->isTargetCygMing()) { // Unsupported by now, just quick fallback - Flavour = DWARFFlavour::X86_32_ELF; + Flavour = DWARFFlavour::X86_32_Generic; } else { - Flavour = DWARFFlavour::X86_32_ELF; + Flavour = DWARFFlavour::X86_32_Generic; } } @@ -139,46 +151,35 @@ unsigned X86RegisterInfo::getX86RegNum(unsigned RegNo) { } } +const TargetRegisterClass *X86RegisterInfo::getPointerRegClass() const { + const X86Subtarget *Subtarget = &TM.getSubtarget(); + if (Subtarget->is64Bit()) + return &X86::GR64RegClass; + else + return &X86::GR32RegClass; +} + const TargetRegisterClass * X86RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const { - if (RC == &X86::CCRRegClass) + if (RC == &X86::CCRRegClass) { if (Is64Bit) return &X86::GR64RegClass; else return &X86::GR32RegClass; - return NULL; -} - -void X86RegisterInfo::reMaterialize(MachineBasicBlock &MBB, - MachineBasicBlock::iterator I, - unsigned DestReg, - const MachineInstr *Orig) const { - // MOV32r0 etc. are implemented with xor which clobbers condition code. - // Re-materialize them as movri instructions to avoid side effects. - switch (Orig->getOpcode()) { - case X86::MOV8r0: - BuildMI(MBB, I, TII.get(X86::MOV8ri), DestReg).addImm(0); - break; - case X86::MOV16r0: - BuildMI(MBB, I, TII.get(X86::MOV16ri), DestReg).addImm(0); - break; - case X86::MOV32r0: - BuildMI(MBB, I, TII.get(X86::MOV32ri), DestReg).addImm(0); - break; - case X86::MOV64r0: - BuildMI(MBB, I, TII.get(X86::MOV64ri32), DestReg).addImm(0); - break; - default: { - MachineInstr *MI = Orig->clone(); - MI->getOperand(0).setReg(DestReg); - MBB.insert(I, MI); - break; - } } + return NULL; } const unsigned * X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { + bool callsEHReturn = false; + + if (MF) { + const MachineFrameInfo *MFI = MF->getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + callsEHReturn = (MMI ? MMI->callsEHReturn() : false); + } + static const unsigned CalleeSavedRegs32Bit[] = { X86::ESI, X86::EDI, X86::EBX, X86::EBP, 0 }; @@ -191,21 +192,39 @@ X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const { X86::RBX, X86::R12, X86::R13, X86::R14, X86::R15, X86::RBP, 0 }; - if (Is64Bit) - return CalleeSavedRegs64Bit; - else { - if (MF) { - MachineFrameInfo *MFI = MF->getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - if (MMI && MMI->callsEHReturn()) - return CalleeSavedRegs32EHRet; - } - return CalleeSavedRegs32Bit; + static const unsigned CalleeSavedRegs64EHRet[] = { + X86::RAX, X86::RDX, X86::RBX, X86::R12, + X86::R13, X86::R14, X86::R15, X86::RBP, 0 + }; + + static const unsigned CalleeSavedRegsWin64[] = { + X86::RBX, X86::RBP, X86::RDI, X86::RSI, + X86::R12, X86::R13, X86::R14, X86::R15, + X86::XMM6, X86::XMM7, X86::XMM8, X86::XMM9, + X86::XMM10, X86::XMM11, X86::XMM12, X86::XMM13, + X86::XMM14, X86::XMM15, 0 + }; + + if (Is64Bit) { + if (IsWin64) + return CalleeSavedRegsWin64; + else + return (callsEHReturn ? CalleeSavedRegs64EHRet : CalleeSavedRegs64Bit); + } else { + return (callsEHReturn ? CalleeSavedRegs32EHRet : CalleeSavedRegs32Bit); } } const TargetRegisterClass* const* X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { + bool callsEHReturn = false; + + if (MF) { + const MachineFrameInfo *MFI = MF->getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + callsEHReturn = (MMI ? MMI->callsEHReturn() : false); + } + static const TargetRegisterClass * const CalleeSavedRegClasses32Bit[] = { &X86::GR32RegClass, &X86::GR32RegClass, &X86::GR32RegClass, &X86::GR32RegClass, 0 @@ -220,33 +239,62 @@ X86RegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const { &X86::GR64RegClass, &X86::GR64RegClass, &X86::GR64RegClass, &X86::GR64RegClass, 0 }; + static const TargetRegisterClass * const CalleeSavedRegClasses64EHRet[] = { + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, 0 + }; + static const TargetRegisterClass * const CalleeSavedRegClassesWin64[] = { + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::GR64RegClass, &X86::GR64RegClass, + &X86::VR128RegClass, &X86::VR128RegClass, + &X86::VR128RegClass, &X86::VR128RegClass, + &X86::VR128RegClass, &X86::VR128RegClass, + &X86::VR128RegClass, &X86::VR128RegClass, + &X86::VR128RegClass, &X86::VR128RegClass, 0 + }; - if (Is64Bit) - return CalleeSavedRegClasses64Bit; - else { - if (MF) { - MachineFrameInfo *MFI = MF->getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - if (MMI && MMI->callsEHReturn()) - return CalleeSavedRegClasses32EHRet; - } - return CalleeSavedRegClasses32Bit; + if (Is64Bit) { + if (IsWin64) + return CalleeSavedRegClassesWin64; + else + return (callsEHReturn ? + CalleeSavedRegClasses64EHRet : CalleeSavedRegClasses64Bit); + } else { + return (callsEHReturn ? + CalleeSavedRegClasses32EHRet : CalleeSavedRegClasses32Bit); } - } BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { BitVector Reserved(getNumRegs()); + // Set the stack-pointer register and its aliases as reserved. Reserved.set(X86::RSP); Reserved.set(X86::ESP); Reserved.set(X86::SP); Reserved.set(X86::SPL); + // Set the frame-pointer register and its aliases as reserved if needed. if (hasFP(MF)) { Reserved.set(X86::RBP); Reserved.set(X86::EBP); Reserved.set(X86::BP); Reserved.set(X86::BPL); } + // Mark the x87 stack registers as reserved, since they don't + // behave normally with respect to liveness. We don't fully + // model the effects of x87 stack pushes and pops after + // stackification. + Reserved.set(X86::ST0); + Reserved.set(X86::ST1); + Reserved.set(X86::ST2); + Reserved.set(X86::ST3); + Reserved.set(X86::ST4); + Reserved.set(X86::ST5); + Reserved.set(X86::ST6); + Reserved.set(X86::ST7); return Reserved; } @@ -254,24 +302,82 @@ BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const { // Stack Frame Processing methods //===----------------------------------------------------------------------===// +static unsigned calculateMaxStackAlignment(const MachineFrameInfo *FFI) { + unsigned MaxAlign = 0; + for (int i = FFI->getObjectIndexBegin(), + e = FFI->getObjectIndexEnd(); i != e; ++i) { + if (FFI->isDeadObjectIndex(i)) + continue; + unsigned Align = FFI->getObjectAlignment(i); + MaxAlign = std::max(MaxAlign, Align); + } + + return MaxAlign; +} + // hasFP - Return true if the specified function should have a dedicated frame // pointer register. This is true if the function has variable sized allocas or // if frame pointer elimination is disabled. // bool X86RegisterInfo::hasFP(const MachineFunction &MF) const { - MachineFrameInfo *MFI = MF.getFrameInfo(); - MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + const MachineFrameInfo *MFI = MF.getFrameInfo(); + const MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); - return (NoFramePointerElim || + return (NoFramePointerElim || + needsStackRealignment(MF) || MFI->hasVarSizedObjects() || + MFI->isFrameAddressTaken() || MF.getInfo()->getForceFramePointer() || (MMI && MMI->callsUnwindInit())); } +bool X86RegisterInfo::needsStackRealignment(const MachineFunction &MF) const { + const MachineFrameInfo *MFI = MF.getFrameInfo(); + + // FIXME: Currently we don't support stack realignment for functions with + // variable-sized allocas + return (RealignStack && + (MFI->getMaxAlignment() > StackAlign && + !MFI->hasVarSizedObjects())); +} + bool X86RegisterInfo::hasReservedCallFrame(MachineFunction &MF) const { return !MF.getFrameInfo()->hasVarSizedObjects(); } +int +X86RegisterInfo::getFrameIndexOffset(MachineFunction &MF, int FI) const { + int Offset = MF.getFrameInfo()->getObjectOffset(FI) + SlotSize; + uint64_t StackSize = MF.getFrameInfo()->getStackSize(); + + if (needsStackRealignment(MF)) { + if (FI < 0) + // Skip the saved EBP + Offset += SlotSize; + else { + unsigned Align = MF.getFrameInfo()->getObjectAlignment(FI); + assert( (-(Offset + StackSize)) % Align == 0); + Align = 0; + return Offset + StackSize; + } + + // FIXME: Support tail calls + } else { + if (!hasFP(MF)) + return Offset + StackSize; + + // Skip the saved EBP + Offset += SlotSize; + + // Skip the RETADDR move area + X86MachineFunctionInfo *X86FI = MF.getInfo(); + int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); + if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta; + } + + return Offset; +} + void X86RegisterInfo:: eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const { @@ -289,11 +395,12 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, Amount = (Amount+StackAlign-1)/StackAlign*StackAlign; MachineInstr *New = 0; - if (Old->getOpcode() == X86::ADJCALLSTACKDOWN) { - New=BuildMI(TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), StackPtr) - .addReg(StackPtr).addImm(Amount); + if (Old->getOpcode() == getCallFrameSetupOpcode()) { + New = BuildMI(MF, Old->getDebugLoc(), + TII.get(Is64Bit ? X86::SUB64ri32 : X86::SUB32ri), + StackPtr).addReg(StackPtr).addImm(Amount); } else { - assert(Old->getOpcode() == X86::ADJCALLSTACKUP); + assert(Old->getOpcode() == getCallFrameDestroyOpcode()); // factor out the amount the callee already popped. uint64_t CalleeAmt = Old->getOperand(1).getImm(); Amount -= CalleeAmt; @@ -301,14 +408,20 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Opc = (Amount < 128) ? (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri); - New = BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(Amount); + New = BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), StackPtr) + .addReg(StackPtr).addImm(Amount); } } - // Replace the pseudo instruction with a new instruction... - if (New) MBB.insert(I, New); + if (New) { + // The EFLAGS implicit def is dead. + New->getOperand(3).setIsDead(); + + // Replace the pseudo instruction with a new instruction... + MBB.insert(I, New); + } } - } else if (I->getOpcode() == X86::ADJCALLSTACKUP) { + } else if (I->getOpcode() == getCallFrameDestroyOpcode()) { // If we are performing frame pointer elimination and if the callee pops // something off the stack pointer, add it back. We do this until we have // more advanced stack pointer tracking ability. @@ -316,8 +429,13 @@ eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, unsigned Opc = (CalleeAmt < 128) ? (Is64Bit ? X86::SUB64ri8 : X86::SUB32ri8) : (Is64Bit ? X86::SUB64ri32 : X86::SUB32ri); + MachineInstr *Old = I; MachineInstr *New = - BuildMI(TII.get(Opc), StackPtr).addReg(StackPtr).addImm(CalleeAmt); + BuildMI(MF, Old->getDebugLoc(), TII.get(Opc), + StackPtr).addReg(StackPtr).addImm(CalleeAmt); + // The EFLAGS implicit def is dead. + New->getOperand(3).setIsDead(); + MBB.insert(I, New); } } @@ -332,31 +450,49 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II, unsigned i = 0; MachineInstr &MI = *II; MachineFunction &MF = *MI.getParent()->getParent(); - while (!MI.getOperand(i).isFrameIndex()) { + while (!MI.getOperand(i).isFI()) { ++i; assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!"); } int FrameIndex = MI.getOperand(i).getIndex(); + + unsigned BasePtr; + if (needsStackRealignment(MF)) + BasePtr = (FrameIndex < 0 ? FramePtr : StackPtr); + else + BasePtr = (hasFP(MF) ? FramePtr : StackPtr); + // This must be part of a four operand memory reference. Replace the // FrameIndex with base register with EBP. Add an offset to the offset. - MI.getOperand(i).ChangeToRegister(hasFP(MF) ? FramePtr : StackPtr, false); + MI.getOperand(i).ChangeToRegister(BasePtr, false); // Now add the frame object offset to the offset from EBP. - int64_t Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) + - MI.getOperand(i+3).getImm()+SlotSize; - - if (!hasFP(MF)) - Offset += MF.getFrameInfo()->getStackSize(); - else { - Offset += SlotSize; // Skip the saved EBP - // Skip the RETADDR move area - X86MachineFunctionInfo *X86FI = MF.getInfo(); - int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - if (TailCallReturnAddrDelta < 0) Offset -= TailCallReturnAddrDelta; - } + if (MI.getOperand(i+3).isImm()) { + // Offset is a 32-bit integer. + int Offset = getFrameIndexOffset(MF, FrameIndex) + + (int)(MI.getOperand(i+3).getImm()); - MI.getOperand(i+3).ChangeToImmediate(Offset); + MI.getOperand(i+3).ChangeToImmediate(Offset); + } else { + // Offset is symbolic. This is extremely rare. + uint64_t Offset = getFrameIndexOffset(MF, FrameIndex) + + (uint64_t)MI.getOperand(i+3).getOffset(); + MI.getOperand(i+3).setOffset(Offset); + } +} + +void +X86RegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS) const { + MachineFrameInfo *FFI = MF.getFrameInfo(); + + // Calculate and set max stack object alignment early, so we can decide + // whether we will need stack realignment (and thus FP). + unsigned MaxAlign = std::max(FFI->getMaxAlignment(), + calculateMaxStackAlignment(FFI)); + + FFI->setMaxAlignment(MaxAlign); } void @@ -386,6 +522,7 @@ X86RegisterInfo::processFunctionBeforeFrameFinalized(MachineFunction &MF) const{ TailCallReturnAddrDelta); assert(FrameIdx == MF.getFrameInfo()->getObjectIndexBegin() && "Slot for EBP register must be last in order to be found!"); + FrameIdx = 0; } } @@ -405,10 +542,16 @@ void emitSPUpdate(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, (Is64Bit ? X86::ADD64ri8 : X86::ADD32ri8) : (Is64Bit ? X86::ADD64ri32 : X86::ADD32ri)); uint64_t Chunk = (1LL << 31) - 1; + DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() : + DebugLoc::getUnknownLoc()); while (Offset) { uint64_t ThisVal = (Offset > Chunk) ? Chunk : Offset; - BuildMI(MBB, MBBI, TII.get(Opc), StackPtr).addReg(StackPtr).addImm(ThisVal); + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, TII.get(Opc), StackPtr) + .addReg(StackPtr).addImm(ThisVal); + // The EFLAGS implicit def is dead. + MI->getOperand(3).setIsDead(); Offset -= ThisVal; } } @@ -418,7 +561,7 @@ static void mergeSPUpdatesUp(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, uint64_t *NumBytes = NULL) { if (MBBI == MBB.begin()) return; - + MachineBasicBlock::iterator PI = prior(MBBI); unsigned Opc = PI->getOpcode(); if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || @@ -442,12 +585,12 @@ void mergeSPUpdatesDown(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, unsigned StackPtr, uint64_t *NumBytes = NULL) { return; - + if (MBBI == MBB.end()) return; - + MachineBasicBlock::iterator NI = next(MBBI); if (NI == MBB.end()) return; - + unsigned Opc = NI->getOpcode(); if ((Opc == X86::ADD64ri32 || Opc == X86::ADD64ri8 || Opc == X86::ADD32ri || Opc == X86::ADD32ri8) && @@ -467,12 +610,12 @@ void mergeSPUpdatesDown(MachineBasicBlock &MBB, } /// mergeSPUpdates - Checks the instruction before/after the passed -/// instruction. If it is an ADD/SUB instruction it is deleted +/// instruction. If it is an ADD/SUB instruction it is deleted /// argument and the stack adjustment is returned as a positive value for ADD -/// and a negative for SUB. +/// and a negative for SUB. static int mergeSPUpdates(MachineBasicBlock &MBB, MachineBasicBlock::iterator &MBBI, - unsigned StackPtr, + unsigned StackPtr, bool doMergeWithPrevious) { if ((doMergeWithPrevious && MBBI == MBB.begin()) || @@ -496,11 +639,85 @@ static int mergeSPUpdates(MachineBasicBlock &MBB, Offset -= PI->getOperand(2).getImm(); MBB.erase(PI); if (!doMergeWithPrevious) MBBI = NI; - } + } return Offset; } +void X86RegisterInfo::emitFrameMoves(MachineFunction &MF, + unsigned FrameLabelId, + unsigned ReadyLabelId) const { + MachineFrameInfo *MFI = MF.getFrameInfo(); + MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); + if (!MMI) + return; + + uint64_t StackSize = MFI->getStackSize(); + std::vector &Moves = MMI->getFrameMoves(); + const TargetData *TD = MF.getTarget().getTargetData(); + + // Calculate amount of bytes used for return address storing + int stackGrowth = + (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == + TargetFrameInfo::StackGrowsUp ? + TD->getPointerSize() : -TD->getPointerSize()); + + if (StackSize) { + // Show update of SP. + if (hasFP(MF)) { + // Adjust SP + MachineLocation SPDst(MachineLocation::VirtualFP); + MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth); + Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); + } else { + MachineLocation SPDst(MachineLocation::VirtualFP); + MachineLocation SPSrc(MachineLocation::VirtualFP, + -StackSize+stackGrowth); + Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); + } + } else { + //FIXME: Verify & implement for FP + MachineLocation SPDst(StackPtr); + MachineLocation SPSrc(StackPtr, stackGrowth); + Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); + } + + // Add callee saved registers to move list. + const std::vector &CSI = MFI->getCalleeSavedInfo(); + + // FIXME: This is dirty hack. The code itself is pretty mess right now. + // It should be rewritten from scratch and generalized sometimes. + + // Determine maximum offset (minumum due to stack growth) + int64_t MaxOffset = 0; + for (unsigned I = 0, E = CSI.size(); I!=E; ++I) + MaxOffset = std::min(MaxOffset, + MFI->getObjectOffset(CSI[I].getFrameIdx())); + + // Calculate offsets + int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth; + for (unsigned I = 0, E = CSI.size(); I!=E; ++I) { + int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); + unsigned Reg = CSI[I].getReg(); + Offset = (MaxOffset-Offset+saveAreaOffset); + MachineLocation CSDst(MachineLocation::VirtualFP, Offset); + MachineLocation CSSrc(Reg); + Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); + } + + if (hasFP(MF)) { + // Save FP + MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth); + MachineLocation FPSrc(FramePtr); + Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); + } + + MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr); + MachineLocation FPSrc(MachineLocation::VirtualFP); + Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); +} + + void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineBasicBlock &MBB = MF.front(); // Prolog goes in entry BB MachineFrameInfo *MFI = MF.getFrameInfo(); @@ -509,54 +726,105 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MachineModuleInfo *MMI = MFI->getMachineModuleInfo(); X86MachineFunctionInfo *X86FI = MF.getInfo(); MachineBasicBlock::iterator MBBI = MBB.begin(); - + bool needsFrameMoves = (MMI && MMI->hasDebugInfo()) || + !Fn->doesNotThrow() || + UnwindTablesMandatory; + DebugLoc DL = (MBBI != MBB.end() ? MBBI->getDebugLoc() : + DebugLoc::getUnknownLoc()); + // Prepare for frame info. unsigned FrameLabelId = 0; - + // Get the number of bytes to allocate from the FrameInfo. uint64_t StackSize = MFI->getStackSize(); + + // Get desired stack alignment + uint64_t MaxAlign = MFI->getMaxAlignment(); + // Add RETADDR move area to callee saved frame size. int TailCallReturnAddrDelta = X86FI->getTCReturnAddrDelta(); - if (TailCallReturnAddrDelta < 0) + if (TailCallReturnAddrDelta < 0) X86FI->setCalleeSavedFrameSize( X86FI->getCalleeSavedFrameSize() +(-TailCallReturnAddrDelta)); - uint64_t NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); + + // If this is x86-64 and the Red Zone is not disabled, if we are a leaf + // function, and use up to 128 bytes of stack space, don't have a frame + // pointer, calls, or dynamic alloca then we do not need to adjust the + // stack pointer (we fit in the Red Zone). + if (Is64Bit && !DisableRedZone && + !needsStackRealignment(MF) && + !MFI->hasVarSizedObjects() && // No dynamic alloca. + !MFI->hasCalls()) { // No calls. + uint64_t MinSize = X86FI->getCalleeSavedFrameSize(); + if (hasFP(MF)) MinSize += SlotSize; + StackSize = std::max(MinSize, + StackSize > 128 ? StackSize - 128 : 0); + MFI->setStackSize(StackSize); + } // Insert stack pointer adjustment for later moving of return addr. Only // applies to tail call optimized functions where the callee argument stack // size is bigger than the callers. if (TailCallReturnAddrDelta < 0) { - BuildMI(MBB, MBBI, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), - StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit? X86::SUB64ri32 : X86::SUB32ri), + StackPtr).addReg(StackPtr).addImm(-TailCallReturnAddrDelta); + // The EFLAGS implicit def is dead. + MI->getOperand(3).setIsDead(); } + uint64_t NumBytes = 0; if (hasFP(MF)) { + // Calculate required stack adjustment + uint64_t FrameSize = StackSize - SlotSize; + if (needsStackRealignment(MF)) + FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; + + NumBytes = FrameSize - X86FI->getCalleeSavedFrameSize(); + // Get the offset of the stack slot for the EBP register... which is // guaranteed to be the last slot by processFunctionBeforeFrameFinalized. // Update the frame offset adjustment. - MFI->setOffsetAdjustment(SlotSize-NumBytes); + MFI->setOffsetAdjustment(-NumBytes); // Save EBP into the appropriate stack slot... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) - .addReg(FramePtr); - NumBytes -= SlotSize; + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::PUSH64r : X86::PUSH32r)) + .addReg(FramePtr, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); - if (MMI && MMI->needsFrameInfo()) { + if (needsFrameMoves) { // Mark effective beginning of when frame pointer becomes valid. FrameLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(FrameLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(FrameLabelId); } // Update EBP with the new base value... - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) - .addReg(StackPtr); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), FramePtr) + .addReg(StackPtr); + + // Mark the FramePtr as live-in in every block except the entry. + for (MachineFunction::iterator I = next(MF.begin()), E = MF.end(); + I != E; ++I) + I->addLiveIn(FramePtr); + + // Realign stack + if (needsStackRealignment(MF)) { + MachineInstr *MI = + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::AND64ri32 : X86::AND32ri), + StackPtr).addReg(StackPtr).addImm(-MaxAlign); + // The EFLAGS implicit def is dead. + MI->getOperand(3).setIsDead(); + } + } else { + NumBytes = StackSize - X86FI->getCalleeSavedFrameSize(); } - + unsigned ReadyLabelId = 0; - if (MMI && MMI->needsFrameInfo()) { + if (needsFrameMoves) { // Mark effective beginning of when frame pointer is ready. ReadyLabelId = MMI->NextLabelID(); - BuildMI(MBB, MBBI, TII.get(X86::LABEL)).addImm(ReadyLabelId); + BuildMI(MBB, MBBI, DL, TII.get(X86::DBG_LABEL)).addImm(ReadyLabelId); } // Skip the callee-saved push instructions. @@ -565,6 +833,9 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { MBBI->getOpcode() == X86::PUSH64r)) ++MBBI; + if (MBBI != MBB.end()) + DL = MBBI->getDebugLoc(); + if (NumBytes) { // adjust stack pointer: ESP -= numbytes if (NumBytes >= 4096 && Subtarget->isTargetCygMing()) { // Check, whether EAX is livein for this function @@ -577,25 +848,29 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { Reg == X86::AH || Reg == X86::AL); } - // Function prologue calls _alloca to probe the stack when allocating - // more than 4k bytes in one go. Touching the stack at 4K increments is + // Function prologue calls _alloca to probe the stack when allocating + // more than 4k bytes in one go. Touching the stack at 4K increments is // necessary to ensure that the guard pages used by the OS virtual memory // manager are allocated in correct sequence. if (!isEAXAlive) { - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI, DL, TII.get(X86::MOV32ri), X86::EAX) + .addImm(NumBytes); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); } else { // Save EAX - BuildMI(MBB, MBBI, TII.get(X86::PUSH32r), X86::EAX); + BuildMI(MBB, MBBI, DL, TII.get(X86::PUSH32r)) + .addReg(X86::EAX, /*isDef=*/false, /*isImp=*/false, /*isKill=*/true); // Allocate NumBytes-4 bytes on stack. We'll also use 4 already // allocated bytes for EAX. - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)) + BuildMI(MBB, MBBI, DL, + TII.get(X86::MOV32ri), X86::EAX).addImm(NumBytes-4); + BuildMI(MBB, MBBI, DL, TII.get(X86::CALLpcrel32)) .addExternalSymbol("_alloca"); // Restore EAX - MachineInstr *MI = addRegOffset(BuildMI(TII.get(X86::MOV32rm),X86::EAX), - StackPtr, NumBytes-4); + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(X86::MOV32rm), + X86::EAX), + StackPtr, false, NumBytes-4); MBB.insert(MBBI, MI); } } else { @@ -606,97 +881,23 @@ void X86RegisterInfo::emitPrologue(MachineFunction &MF) const { // If there is an ADD32ri or SUB32ri of ESP immediately after this // instruction, merge the two instructions. mergeSPUpdatesDown(MBB, MBBI, StackPtr, &NumBytes); - + if (NumBytes) emitSPUpdate(MBB, MBBI, StackPtr, -(int64_t)NumBytes, Is64Bit, TII); } } - if (MMI && MMI->needsFrameInfo()) { - std::vector &Moves = MMI->getFrameMoves(); - const TargetData *TD = MF.getTarget().getTargetData(); - - // Calculate amount of bytes used for return address storing - int stackGrowth = - (MF.getTarget().getFrameInfo()->getStackGrowthDirection() == - TargetFrameInfo::StackGrowsUp ? - TD->getPointerSize() : -TD->getPointerSize()); - - if (StackSize) { - // Show update of SP. - if (hasFP(MF)) { - // Adjust SP - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, 2*stackGrowth); - Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); - } else { - MachineLocation SPDst(MachineLocation::VirtualFP); - MachineLocation SPSrc(MachineLocation::VirtualFP, - -StackSize+stackGrowth); - Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); - } - } else { - //FIXME: Verify & implement for FP - MachineLocation SPDst(StackPtr); - MachineLocation SPSrc(StackPtr, stackGrowth); - Moves.push_back(MachineMove(FrameLabelId, SPDst, SPSrc)); - } - - // Add callee saved registers to move list. - const std::vector &CSI = MFI->getCalleeSavedInfo(); - - // FIXME: This is dirty hack. The code itself is pretty mess right now. - // It should be rewritten from scratch and generalized sometimes. - - // Determine maximum offset (minumum due to stack growth) - int64_t MaxOffset = 0; - for (unsigned I = 0, E = CSI.size(); I!=E; ++I) - MaxOffset = std::min(MaxOffset, - MFI->getObjectOffset(CSI[I].getFrameIdx())); - - // Calculate offsets - int64_t saveAreaOffset = (hasFP(MF) ? 3 : 2)*stackGrowth; - for (unsigned I = 0, E = CSI.size(); I!=E; ++I) { - int64_t Offset = MFI->getObjectOffset(CSI[I].getFrameIdx()); - unsigned Reg = CSI[I].getReg(); - Offset = (MaxOffset-Offset+saveAreaOffset); - MachineLocation CSDst(MachineLocation::VirtualFP, Offset); - MachineLocation CSSrc(Reg); - Moves.push_back(MachineMove(FrameLabelId, CSDst, CSSrc)); - } - - if (hasFP(MF)) { - // Save FP - MachineLocation FPDst(MachineLocation::VirtualFP, 2*stackGrowth); - MachineLocation FPSrc(FramePtr); - Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); - } - - MachineLocation FPDst(hasFP(MF) ? FramePtr : StackPtr); - MachineLocation FPSrc(MachineLocation::VirtualFP); - Moves.push_back(MachineMove(ReadyLabelId, FPDst, FPSrc)); - } - - // If it's main() on Cygwin\Mingw32 we should align stack as well - if (Fn->hasExternalLinkage() && Fn->getName() == "main" && - Subtarget->isTargetCygMing()) { - BuildMI(MBB, MBBI, TII.get(X86::AND32ri), X86::ESP) - .addReg(X86::ESP).addImm(-StackAlign); - - // Probe the stack - BuildMI(MBB, MBBI, TII.get(X86::MOV32ri), X86::EAX).addImm(StackAlign); - BuildMI(MBB, MBBI, TII.get(X86::CALLpcrel32)).addExternalSymbol("_alloca"); - } + if (needsFrameMoves) + emitFrameMoves(MF, FrameLabelId, ReadyLabelId); } void X86RegisterInfo::emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); - const Function* Fn = MF.getFunction(); X86MachineFunctionInfo *X86FI = MF.getInfo(); - const X86Subtarget* Subtarget = &MF.getTarget().getSubtarget(); MachineBasicBlock::iterator MBBI = prior(MBB.end()); unsigned RetOpcode = MBBI->getOpcode(); + DebugLoc DL = MBBI->getDebugLoc(); switch (RetOpcode) { case X86::RET: @@ -706,6 +907,7 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, case X86::TCRETURNri64: case X86::TCRETURNdi64: case X86::EH_RETURN: + case X86::EH_RETURN64: case X86::TAILJMPd: case X86::TAILJMPr: case X86::TAILJMPm: break; // These are ok @@ -715,68 +917,89 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, // Get the number of bytes to allocate from the FrameInfo uint64_t StackSize = MFI->getStackSize(); + uint64_t MaxAlign = MFI->getMaxAlignment(); unsigned CSSize = X86FI->getCalleeSavedFrameSize(); - uint64_t NumBytes = StackSize - CSSize; + uint64_t NumBytes = 0; if (hasFP(MF)) { + // Calculate required stack adjustment + uint64_t FrameSize = StackSize - SlotSize; + if (needsStackRealignment(MF)) + FrameSize = (FrameSize + MaxAlign - 1)/MaxAlign*MaxAlign; + + NumBytes = FrameSize - CSSize; + // pop EBP. - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); - NumBytes -= SlotSize; + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::POP64r : X86::POP32r), FramePtr); + } else { + NumBytes = StackSize - CSSize; } // Skip the callee-saved pop instructions. + MachineBasicBlock::iterator LastCSPop = MBBI; while (MBBI != MBB.begin()) { MachineBasicBlock::iterator PI = prior(MBBI); unsigned Opc = PI->getOpcode(); if (Opc != X86::POP32r && Opc != X86::POP64r && - !PI->getDesc()->isTerminator()) + !PI->getDesc().isTerminator()) break; --MBBI; } + DL = MBBI->getDebugLoc(); + // If there is an ADD32ri or SUB32ri of ESP immediately before this // instruction, merge the two instructions. if (NumBytes || MFI->hasVarSizedObjects()) mergeSPUpdatesUp(MBB, MBBI, StackPtr, &NumBytes); // If dynamic alloca is used, then reset esp to point to the last callee-saved - // slot before popping them off! Also, if it's main() on Cygwin/Mingw32 we - // aligned stack in the prologue, - revert stack changes back. Note: we're - // assuming, that frame pointer was forced for main() - if (MFI->hasVarSizedObjects() || - (Fn->hasExternalLinkage() && Fn->getName() == "main" && - Subtarget->isTargetCygMing())) { - unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; + // slot before popping them off! Same applies for the case, when stack was + // realigned + if (needsStackRealignment(MF)) { + // We cannot use LEA here, because stack pointer was realigned. We need to + // deallocate local frame back if (CSSize) { - MachineInstr *MI = addRegOffset(BuildMI(TII.get(Opc), StackPtr), - FramePtr, -CSSize); + emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); + MBBI = prior(LastCSPop); + } + + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), + StackPtr).addReg(FramePtr); + } else if (MFI->hasVarSizedObjects()) { + if (CSSize) { + unsigned Opc = Is64Bit ? X86::LEA64r : X86::LEA32r; + MachineInstr *MI = addRegOffset(BuildMI(MF, DL, TII.get(Opc), StackPtr), + FramePtr, false, -CSSize); MBB.insert(MBBI, MI); } else - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). - addReg(FramePtr); + BuildMI(MBB, MBBI, DL, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), + StackPtr).addReg(FramePtr); - NumBytes = 0; + } else { + // adjust stack pointer back: ESP += numbytes + if (NumBytes) + emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); } - // adjust stack pointer back: ESP += numbytes - if (NumBytes) - emitSPUpdate(MBB, MBBI, StackPtr, NumBytes, Is64Bit, TII); - // We're returning from function via eh_return. - if (RetOpcode == X86::EH_RETURN) { + if (RetOpcode == X86::EH_RETURN || RetOpcode == X86::EH_RETURN64) { MBBI = prior(MBB.end()); MachineOperand &DestAddr = MBBI->getOperand(0); - assert(DestAddr.isRegister() && "Offset should be in register!"); - BuildMI(MBB, MBBI, TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr),StackPtr). - addReg(DestAddr.getReg()); + assert(DestAddr.isReg() && "Offset should be in register!"); + BuildMI(MBB, MBBI, DL, + TII.get(Is64Bit ? X86::MOV64rr : X86::MOV32rr), + StackPtr).addReg(DestAddr.getReg()); // Tail call return: adjust the stack pointer and jump to callee } else if (RetOpcode == X86::TCRETURNri || RetOpcode == X86::TCRETURNdi || RetOpcode== X86::TCRETURNri64 || RetOpcode == X86::TCRETURNdi64) { MBBI = prior(MBB.end()); MachineOperand &JumpTarget = MBBI->getOperand(0); MachineOperand &StackAdjust = MBBI->getOperand(1); - assert( StackAdjust.isImmediate() && "Expecting immediate value."); - + assert(StackAdjust.isImm() && "Expecting immediate value."); + // Adjust stack pointer. int StackAdj = StackAdjust.getImm(); int MaxTCDelta = X86FI->getTCReturnAddrDelta(); @@ -785,22 +1008,25 @@ void X86RegisterInfo::emitEpilogue(MachineFunction &MF, // Incoporate the retaddr area. Offset = StackAdj-MaxTCDelta; assert(Offset >= 0 && "Offset should never be negative"); + if (Offset) { // Check for possible merge with preceeding ADD instruction. Offset += mergeSPUpdates(MBB, MBBI, StackPtr, true); emitSPUpdate(MBB, MBBI, StackPtr, Offset, Is64Bit, TII); - } + } + // Jump to label or value in register. if (RetOpcode == X86::TCRETURNdi|| RetOpcode == X86::TCRETURNdi64) - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPd)). + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPd)). addGlobalAddress(JumpTarget.getGlobal(), JumpTarget.getOffset()); - else if (RetOpcode== X86::TCRETURNri64) { - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); - } else - BuildMI(MBB, MBBI, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + else if (RetOpcode== X86::TCRETURNri64) + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr64), JumpTarget.getReg()); + else + BuildMI(MBB, MBBI, DL, TII.get(X86::TAILJMPr), JumpTarget.getReg()); + // Delete the pseudo instruction TCRETURN. MBB.erase(MBBI); - } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && + } else if ((RetOpcode == X86::RET || RetOpcode == X86::RETI) && (X86FI->getTCReturnAddrDelta() < 0)) { // Add the return addr area delta back since we are not tail calling. int delta = -1*X86FI->getTCReturnAddrDelta(); @@ -849,8 +1075,8 @@ unsigned X86RegisterInfo::getEHHandlerRegister() const { } namespace llvm { -unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { - switch (VT) { +unsigned getX86SubSuperRegister(unsigned Reg, MVT VT, bool High) { + switch (VT.getSimpleVT()) { default: return Reg; case MVT::i8: if (High) { @@ -1018,3 +1244,37 @@ unsigned getX86SubSuperRegister(unsigned Reg, MVT::ValueType VT, bool High) { #include "X86GenRegisterInfo.inc" +namespace { + struct VISIBILITY_HIDDEN MSAC : public MachineFunctionPass { + static char ID; + MSAC() : MachineFunctionPass(&ID) {} + + virtual bool runOnMachineFunction(MachineFunction &MF) { + MachineFrameInfo *FFI = MF.getFrameInfo(); + MachineRegisterInfo &RI = MF.getRegInfo(); + + // Calculate max stack alignment of all already allocated stack objects. + unsigned MaxAlign = calculateMaxStackAlignment(FFI); + + // Be over-conservative: scan over all vreg defs and find, whether vector + // registers are used. If yes - there is probability, that vector register + // will be spilled and thus stack needs to be aligned properly. + for (unsigned RegNum = TargetRegisterInfo::FirstVirtualRegister; + RegNum < RI.getLastVirtReg(); ++RegNum) + MaxAlign = std::max(MaxAlign, RI.getRegClass(RegNum)->getAlignment()); + + FFI->setMaxAlignment(MaxAlign); + + return false; + } + + virtual const char *getPassName() const { + return "X86 Maximal Stack Alignment Calculator"; + } + }; + + char MSAC::ID = 0; +} + +FunctionPass* +llvm::createX86MaxStackAlignmentCalculatorPass() { return new MSAC(); }