X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86RegisterInfo.h;h=eac8426a980ea0628069962694176c31c0f2fa24;hb=281bada3b03b97dad0ac9890706a057ab31a5dd3;hp=c21868c626fa01ca929866c88e1cdda09776bf68;hpb=f0a0cddbcda344a90b7217b744c78dccec71851c;p=oota-llvm.git diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h index c21868c626f..eac8426a980 100644 --- a/lib/Target/X86/X86RegisterInfo.h +++ b/lib/Target/X86/X86RegisterInfo.h @@ -2,21 +2,19 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This file contains the X86 implementation of the MRegisterInfo class. +// This file contains the X86 implementation of the TargetRegisterInfo class. // //===----------------------------------------------------------------------===// #ifndef X86REGISTERINFO_H #define X86REGISTERINFO_H -#include "llvm/ADT/DenseMap.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/Target/MRegisterInfo.h" +#include "llvm/Target/TargetRegisterInfo.h" #include "X86GenRegisterInfo.h.inc" namespace llvm { @@ -32,6 +30,23 @@ namespace N86 { }; } +namespace X86 { + /// SubregIndex - The index of various sized subregister classes. Note that + /// these indices must be kept in sync with the class indices in the + /// X86RegisterInfo.td file. + enum SubregIndex { + SUBREG_8BIT = 1, SUBREG_8BIT_HI = 2, SUBREG_16BIT = 3, SUBREG_32BIT = 4 + }; +} + +/// DWARFFlavour - Flavour of dwarf regnumbers +/// +namespace DWARFFlavour { + enum { + X86_64 = 0, X86_32_DarwinEH = 1, X86_32_Generic = 2 + }; +} + class X86RegisterInfo : public X86GenRegisterInfo { public: X86TargetMachine &TM; @@ -42,10 +57,18 @@ private: /// bool Is64Bit; + /// IsWin64 - Is the target on of win64 flavours + /// + bool IsWin64; + /// SlotSize - Stack slot size in bytes. /// unsigned SlotSize; + /// StackAlign - Default stack alignment. + /// + unsigned StackAlign; + /// StackPtr - X86 physical register used as stack ptr. /// unsigned StackPtr; @@ -54,100 +77,32 @@ private: /// unsigned FramePtr; - /// RegOp2MemOpTable2Addr, RegOp2MemOpTable0, RegOp2MemOpTable1, - /// RegOp2MemOpTable2 - Load / store folding opcode maps. - /// - DenseMap RegOp2MemOpTable2Addr; - DenseMap RegOp2MemOpTable0; - DenseMap RegOp2MemOpTable1; - DenseMap RegOp2MemOpTable2; - - /// MemOp2RegOpTable - Load / store unfolding opcode map. - /// - DenseMap > MemOp2RegOpTable; - public: X86RegisterInfo(X86TargetMachine &tm, const TargetInstrInfo &tii); /// getX86RegNum - Returns the native X86 register number for the given LLVM /// register identifier. - unsigned getX86RegNum(unsigned RegNo); + static unsigned getX86RegNum(unsigned RegNo); + + unsigned getStackAlignment() const { return StackAlign; } + + /// getDwarfRegNum - allows modification of X86GenRegisterInfo::getDwarfRegNum + /// (created by TableGen) for target dependencies. + int getDwarfRegNum(unsigned RegNum, bool isEH) const; /// Code Generation virtual methods... - /// - bool spillCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - - bool restoreCalleeSavedRegisters(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - const std::vector &CSI) const; - - void storeRegToStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned SrcReg, int FrameIndex, - const TargetRegisterClass *RC) const; - - void storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const; - - void loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIndex, - const TargetRegisterClass *RC) const; - - void loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl &Addr, - const TargetRegisterClass *RC, - SmallVectorImpl &NewMIs) const; - - void copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const; - + /// + + /// getPointerRegClass - Returns a TargetRegisterClass used for pointer + /// values. + const TargetRegisterClass *getPointerRegClass() const; + + /// getCrossCopyRegClass - Returns a legal register class to copy a register + /// in the specified class to or from. Returns NULL if it is possible to copy + /// between a two registers of the specified class. const TargetRegisterClass * getCrossCopyRegClass(const TargetRegisterClass *RC) const; - void reMaterialize(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI, - unsigned DestReg, const MachineInstr *Orig) const; - - /// foldMemoryOperand - If this target supports it, fold a load or store of - /// the specified stack slot into the specified machine instruction for the - /// specified operand. If this is possible, the target should perform the - /// folding and return true, otherwise it should return false. If it folds - /// the instruction, it is likely that the MachineInstruction the iterator - /// references has been changed. - MachineInstr* foldMemoryOperand(MachineInstr* MI, - unsigned OpNum, - int FrameIndex) const; - - /// foldMemoryOperand - Same as the previous version except it allows folding - /// of any load and store from / to any address, not just from a specific - /// stack slot. - MachineInstr* foldMemoryOperand(MachineInstr* MI, - unsigned OpNum, - MachineInstr* LoadMI) const; - - /// unfoldMemoryOperand - Separate a single instruction which folded a load or - /// a store or a load and a store into two or more instruction. If this is - /// possible, returns true as well as the new instructions by reference. - bool unfoldMemoryOperand(MachineFunction &MF, MachineInstr *MI, - unsigned Reg, bool UnfoldLoad, bool UnfoldStore, - SmallVectorImpl &NewMIs) const; - - bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N, - SmallVectorImpl &NewNodes) const; - - /// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new - /// instruction after load / store are unfolded from the specified opcode. - /// It returns zero if the specified unfolding is impossible. - unsigned getOpcodeAfterMemoryUnfold(unsigned Opc, - bool UnfoldLoad, bool UnfoldStore) const; - /// getCalleeSavedRegs - Return a null-terminated list of all of the /// callee-save registers on this target. const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const; @@ -166,8 +121,13 @@ public: bool hasFP(const MachineFunction &MF) const; + bool needsStackRealignment(const MachineFunction &MF) const; + bool hasReservedCallFrame(MachineFunction &MF) const; + bool hasReservedSpillSlot(MachineFunction &MF, unsigned Reg, + int &FrameIdx) const; + void eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB, MachineBasicBlock::iterator MI) const; @@ -175,30 +135,29 @@ public: void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj, RegScavenger *RS = NULL) const; - void processFunctionBeforeFrameFinalized(MachineFunction &MF) const; + void processFunctionBeforeCalleeSavedScan(MachineFunction &MF, + RegScavenger *RS = NULL) const; + void emitCalleeSavedFrameMoves(MachineFunction &MF, unsigned LabelId, + unsigned FramePtr) const; void emitPrologue(MachineFunction &MF) const; void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const; // Debug information queries. unsigned getRARegister() const; unsigned getFrameRegister(MachineFunction &MF) const; + int getFrameIndexOffset(MachineFunction &MF, int FI) const; void getInitialFrameState(std::vector &Moves) const; // Exception handling queries. unsigned getEHExceptionRegister() const; unsigned getEHHandlerRegister() const; - -private: - MachineInstr* foldMemoryOperand(MachineInstr* MI, - unsigned OpNum, - SmallVector &MOs) const; }; // getX86SubSuperRegister - X86 utility function. It returns the sub or super // register of a specific X86 register. // e.g. getX86SubSuperRegister(X86::EAX, MVT::i16) return X86:AX -unsigned getX86SubSuperRegister(unsigned, MVT::ValueType, bool High=false); +unsigned getX86SubSuperRegister(unsigned, MVT, bool High=false); } // End llvm namespace