X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86ScheduleAtom.td;h=4c559c9c1798da2ef7dc7e17cfd8946db627fe71;hb=68cb3950c097e41c9ebb41fe0855bdf52e1cbe87;hp=5fc08ed735c910779a69654cd4244624d75e1f94;hpb=95f0cf0438f7da130910ee9c5d82e04f9c8471ab;p=oota-llvm.git diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td index 5fc08ed735c..4c559c9c179 100644 --- a/lib/Target/X86/X86ScheduleAtom.td +++ b/lib/Target/X86/X86ScheduleAtom.td @@ -7,8 +7,8 @@ // //===----------------------------------------------------------------------===// // -// This file defines the itinerary class data for the Intel Atom (Bonnell) -// processors. +// This file defines the itinerary class data for the Intel Atom +// in order (Saltwell-32nm/Bonnell-45nm) processors. // //===----------------------------------------------------------------------===// @@ -33,7 +33,6 @@ def AtomItineraries : ProcessorItineraries< // InstrItinData, InstrStage] >, // // Default is 1 cycle, port0 or port1 - InstrItinData] >, InstrItinData] >, InstrItinData] >, InstrItinData] >, @@ -80,9 +79,12 @@ def AtomItineraries : ProcessorItineraries< // neg/not/inc/dec InstrItinData] >, InstrItinData] >, - // add/sub/and/or/xor/adc/sbc/cmp/test + // add/sub/and/or/xor/cmp/test InstrItinData] >, InstrItinData] >, + // adc/sbc + InstrItinData] >, + InstrItinData] >, // shift/rotate InstrItinData] >, // shift double @@ -106,7 +108,7 @@ def AtomItineraries : ProcessorItineraries< InstrItinData] >, InstrItinData] >, // set - InstrItinData] >, + InstrItinData] >, InstrItinData] >, // jcc InstrItinData] >, @@ -204,18 +206,28 @@ def AtomItineraries : ProcessorItineraries< InstrItinData] >, InstrItinData] >, - InstrItinData] >, - InstrItinData] >, + InstrItinData] >, InstrItinData] >, - InstrItinData] >, + InstrItinData] >, + InstrItinData] >, InstrItinData] >, - InstrItinData] >, - InstrItinData] >, - InstrItinData] >, - InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, InstrItinData] >, InstrItinData] >, @@ -274,7 +286,8 @@ def AtomItineraries : ProcessorItineraries< InstrItinData] >, InstrItinData] >, - InstrItinData] >, + InstrItinData] >, + InstrItinData] >, InstrItinData] >, InstrItinData] >, @@ -294,6 +307,45 @@ def AtomItineraries : ProcessorItineraries< InstrItinData] >, InstrItinData] >, + // MMX MOVs + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // other MMX + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // conversions + // from/to PD + InstrItinData] >, + InstrItinData] >, + // from/to PI + InstrItinData] >, + InstrItinData, + InstrStage<5, [Port1]>]>, + InstrItinData] >, InstrItinData] >, InstrItinData] >, @@ -339,7 +391,159 @@ def AtomItineraries : ProcessorItineraries< InstrItinData] >, InstrItinData] >, InstrItinData] >, - InstrItinData, InstrStage<1, [Port1]>] > - + InstrItinData, InstrStage<1, [Port1]>] >, + + // System instructions + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + // worst case for mov REG_CRx + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // LAR + InstrItinData] >, + InstrItinData] >, + // LSL + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // push control register, segment registers + InstrItinData] >, + InstrItinData] >, + // pop control register, segment registers + InstrItinData] >, + InstrItinData] >, + // VERR, VERW + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // WRMSR, RDMSR + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + // SMSW, LMSW + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData, + InstrStage<1, [Port1]>] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData, + InstrStage<1, [Port1]>] >, + InstrItinData] >, + InstrItinData, + InstrStage<1, [Port1]>] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + InstrItinData] >, + + InstrItinData] > ]>; +// Atom machine model. +def AtomModel : SchedMachineModel { + let IssueWidth = 2; // Allows 2 instructions per scheduling group. + let MicroOpBufferSize = 0; // In-order execution, always hide latency. + let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles. + let HighLatency = 30;// Expected, may be overriden by OperandCycles. + + // On the Atom, the throughput for taken branches is 2 cycles. For small + // simple loops, expand by a small factor to hide the backedge cost. + let LoopMicroOpBufferSize = 10; + let PostRAScheduler = 1; + + let Itineraries = AtomItineraries; +}