X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=lib%2FTarget%2FX86%2FX86TargetMachine.h;h=174d3918318d4eb4c7e774324a655d35fff83079;hb=017d8a3e23b719ece59f2498582db7f25d65c1b9;hp=fc043500a05a165ef86d1b1c23c5216f21cf8110;hpb=1e60a9165dc4d6ce5650dacc026f2942696af920;p=oota-llvm.git

diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h
index fc043500a05..174d3918318 100644
--- a/lib/Target/X86/X86TargetMachine.h
+++ b/lib/Target/X86/X86TargetMachine.h
@@ -1,12 +1,12 @@
 //===-- X86TargetMachine.h - Define TargetMachine for the X86 ---*- C++ -*-===//
-// 
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
-// 
+//
 // This file declares the X86 specific subclass of TargetMachine.
 //
 //===----------------------------------------------------------------------===//
@@ -14,46 +14,122 @@
 #ifndef X86TARGETMACHINE_H
 #define X86TARGETMACHINE_H
 
-#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetFrameInfo.h"
-#include "llvm/PassManager.h"
+#include "X86.h"
+#include "X86FrameLowering.h"
+#include "X86ISelLowering.h"
 #include "X86InstrInfo.h"
 #include "X86JITInfo.h"
+#include "X86SelectionDAGInfo.h"
+#include "X86Subtarget.h"
+#include "llvm/IR/DataLayout.h"
+#include "llvm/Target/TargetFrameLowering.h"
+#include "llvm/Target/TargetMachine.h"
 
 namespace llvm {
 
-class X86TargetMachine : public TargetMachine {
-  X86InstrInfo    InstrInfo;
-  TargetFrameInfo FrameInfo;
-  X86JITInfo      JITInfo;
+class StringRef;
+
+class X86TargetMachine : public LLVMTargetMachine {
+  X86Subtarget       Subtarget;
+  X86FrameLowering   FrameLowering;
+  InstrItineraryData InstrItins;
+
 public:
-  X86TargetMachine(const Module &M);
+  X86TargetMachine(const Target &T, StringRef TT,
+                   StringRef CPU, StringRef FS, const TargetOptions &Options,
+                   Reloc::Model RM, CodeModel::Model CM,
+                   CodeGenOpt::Level OL,
+                   bool is64Bit);
 
-  virtual const X86InstrInfo     &getInstrInfo() const { return InstrInfo; }
-  virtual const TargetFrameInfo  &getFrameInfo() const { return FrameInfo; }
-  virtual const MRegisterInfo *getRegisterInfo() const {
-    return &InstrInfo.getRegisterInfo();
+  virtual const X86InstrInfo     *getInstrInfo() const {
+    llvm_unreachable("getInstrInfo not implemented");
   }
-
-  virtual TargetJITInfo *getJITInfo() {
-    return &JITInfo;
+  virtual const TargetFrameLowering  *getFrameLowering() const {
+    return &FrameLowering;
+  }
+  virtual       X86JITInfo       *getJITInfo()         {
+    llvm_unreachable("getJITInfo not implemented");
+  }
+  virtual const X86Subtarget     *getSubtargetImpl() const{ return &Subtarget; }
+  virtual const X86TargetLowering *getTargetLowering() const {
+    llvm_unreachable("getTargetLowering not implemented");
+  }
+  virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
+    llvm_unreachable("getSelectionDAGInfo not implemented");
   }
+  virtual const X86RegisterInfo  *getRegisterInfo() const {
+    return &getInstrInfo()->getRegisterInfo();
+  }
+  virtual const InstrItineraryData *getInstrItineraryData() const {
+    return &InstrItins;
+  }
+
+  /// \brief Register X86 analysis passes with a pass manager.
+  virtual void addAnalysisPasses(PassManagerBase &PM);
 
+  // Set up the pass pipeline.
+  virtual TargetPassConfig *createPassConfig(PassManagerBase &PM);
 
-  virtual const TargetSchedInfo &getSchedInfo()  const { abort(); }
-  virtual const TargetRegInfo   &getRegInfo()    const { abort(); }
-  virtual const TargetCacheInfo  &getCacheInfo() const { abort(); }
+  virtual bool addCodeEmitter(PassManagerBase &PM,
+                              JITCodeEmitter &JCE);
+};
 
-  /// addPassesToEmitMachineCode - Add passes to the specified pass manager to
-  /// get machine code emitted.  This uses a MachineCodeEmitter object to handle
-  /// actually outputting the machine code and resolving things like the address
-  /// of functions.  This method should returns true if machine code emission is
-  /// not supported.
-  ///
-  virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
-                                          MachineCodeEmitter &MCE);
-  
-  virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
+/// X86_32TargetMachine - X86 32-bit target machine.
+///
+class X86_32TargetMachine : public X86TargetMachine {
+  virtual void anchor();
+  const DataLayout  DL; // Calculates type size & alignment
+  X86InstrInfo      InstrInfo;
+  X86TargetLowering TLInfo;
+  X86SelectionDAGInfo TSInfo;
+  X86JITInfo        JITInfo;
+public:
+  X86_32TargetMachine(const Target &T, StringRef TT,
+                      StringRef CPU, StringRef FS, const TargetOptions &Options,
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
+  virtual const DataLayout *getDataLayout() const { return &DL; }
+  virtual const X86TargetLowering *getTargetLowering() const {
+    return &TLInfo;
+  }
+  virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
+    return &TSInfo;
+  }
+  virtual const X86InstrInfo     *getInstrInfo() const {
+    return &InstrInfo;
+  }
+  virtual       X86JITInfo       *getJITInfo()         {
+    return &JITInfo;
+  }
+};
+
+/// X86_64TargetMachine - X86 64-bit target machine.
+///
+class X86_64TargetMachine : public X86TargetMachine {
+  virtual void anchor();
+  const DataLayout  DL; // Calculates type size & alignment
+  X86InstrInfo      InstrInfo;
+  X86TargetLowering TLInfo;
+  X86SelectionDAGInfo TSInfo;
+  X86JITInfo        JITInfo;
+public:
+  X86_64TargetMachine(const Target &T, StringRef TT,
+                      StringRef CPU, StringRef FS, const TargetOptions &Options,
+                      Reloc::Model RM, CodeModel::Model CM,
+                      CodeGenOpt::Level OL);
+  virtual const DataLayout *getDataLayout() const { return &DL; }
+  virtual const X86TargetLowering *getTargetLowering() const {
+    return &TLInfo;
+  }
+  virtual const X86SelectionDAGInfo *getSelectionDAGInfo() const {
+    return &TSInfo;
+  }
+  virtual const X86InstrInfo     *getInstrInfo() const {
+    return &InstrInfo;
+  }
+  virtual       X86JITInfo       *getJITInfo()         {
+    return &JITInfo;
+  }
 };
 
 } // End llvm namespace