X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FARM%2Fcoalesce-subregs.ll;h=72fefeacfc5b7b5036897ef691001b3859add5bc;hb=0cf3a4e4fee5bb456dc02a393ed4fcb559b7f824;hp=238ba24a79702c9300537f468f24f9bf8f29ee64;hpb=d86296a4aea7ebac9c8ef8ba92642b64545dec95;p=oota-llvm.git diff --git a/test/CodeGen/ARM/coalesce-subregs.ll b/test/CodeGen/ARM/coalesce-subregs.ll index 238ba24a797..72fefeacfc5 100644 --- a/test/CodeGen/ARM/coalesce-subregs.ll +++ b/test/CodeGen/ARM/coalesce-subregs.ll @@ -16,7 +16,7 @@ entry: %0 = bitcast float* %p to i8* %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 - %add.ptr = getelementptr inbounds float* %p, i32 8 + %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* tail call void @llvm.arm.neon.vst2.v4f32(i8* %1, <4 x float> %vld221, <4 x float> undef, i32 4) ret void @@ -29,7 +29,7 @@ entry: %0 = bitcast float* %p to i8* %vld2 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %0, i32 4) %vld221 = extractvalue { <4 x float>, <4 x float> } %vld2, 1 - %add.ptr = getelementptr inbounds float* %p, i32 8 + %add.ptr = getelementptr inbounds float, float* %p, i32 8 %1 = bitcast float* %add.ptr to i8* %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 @@ -50,7 +50,7 @@ do.body: ; preds = %do.body, %entry %qq0.0.1.0 = phi <4 x float> [ %vld224, %entry ], [ %vld2216, %do.body ] %c.addr.0 = phi i32 [ %c, %entry ], [ %dec, %do.body ] %p.addr.0 = phi float* [ %p, %entry ], [ %add.ptr, %do.body ] - %add.ptr = getelementptr inbounds float* %p.addr.0, i32 8 + %add.ptr = getelementptr inbounds float, float* %p.addr.0, i32 8 %1 = bitcast float* %add.ptr to i8* %vld22 = tail call { <4 x float>, <4 x float> } @llvm.arm.neon.vld2.v4f32(i8* %1, i32 4) %vld2215 = extractvalue { <4 x float>, <4 x float> } %vld22, 0 @@ -85,29 +85,29 @@ declare void @llvm.arm.neon.vst2.v4f32(i8*, <4 x float>, <4 x float>, i32) nounw ; CHECK-NOT: vorr define void @f3(float* %p, float* %q) nounwind ssp { entry: - %arrayidx = getelementptr inbounds float* %p, i32 3 - %0 = load float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, float* %p, i32 3 + %0 = load float, float* %arrayidx, align 4 %vecins = insertelement <2 x float> undef, float %0, i32 1 %tobool = icmp eq float* %q, null br i1 %tobool, label %if.else, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 - %arrayidx2 = getelementptr inbounds float* %q, i32 1 - %2 = load float* %arrayidx2, align 4 + %1 = load float, float* %q, align 4 + %arrayidx2 = getelementptr inbounds float, float* %q, i32 1 + %2 = load float, float* %arrayidx2, align 4 %add = fadd float %1, %2 %vecins3 = insertelement <2 x float> %vecins, float %add, i32 0 br label %if.end if.else: ; preds = %entry - %arrayidx4 = getelementptr inbounds float* %p, i32 2 - %3 = load float* %arrayidx4, align 4 + %arrayidx4 = getelementptr inbounds float, float* %p, i32 2 + %3 = load float, float* %arrayidx4, align 4 %vecins5 = insertelement <2 x float> %vecins, float %3, i32 0 br label %if.end if.end: ; preds = %if.else, %if.then %x.0 = phi <2 x float> [ %vecins3, %if.then ], [ %vecins5, %if.else ] - %add.ptr = getelementptr inbounds float* %p, i32 4 + %add.ptr = getelementptr inbounds float, float* %p, i32 4 %4 = bitcast float* %add.ptr to i8* tail call void @llvm.arm.neon.vst1.v2f32(i8* %4, <2 x float> %x.0, i32 4) ret void @@ -129,9 +129,9 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %1 = load float* %q, align 4 - %arrayidx1 = getelementptr inbounds float* %q, i32 1 - %2 = load float* %arrayidx1, align 4 + %1 = load float, float* %q, align 4 + %arrayidx1 = getelementptr inbounds float, float* %q, i32 1 + %2 = load float, float* %arrayidx1, align 4 %add = fadd float %1, %2 %vecins = insertelement <2 x float> %vld1, float %add, i32 1 br label %if.end @@ -147,7 +147,7 @@ if.end: ; preds = %entry, %if.then ; CHECK: vmov.f32 {{.*}}, #1.0 ; CHECK-NOT: vmov ; CHECK-NOT: vorr -; CHECK: %if.end +; CHECK: bx ; We may leave the last insertelement in the if.end block. ; It is inserting the %add value into a dead lane, but %add causes interference ; in the entry block, and we don't do dead lane checks across basic blocks. @@ -164,13 +164,13 @@ entry: br i1 %tobool, label %if.end, label %if.then if.then: ; preds = %entry - %arrayidx = getelementptr inbounds float* %q, i32 1 - %1 = load float* %arrayidx, align 4 + %arrayidx = getelementptr inbounds float, float* %q, i32 1 + %1 = load float, float* %arrayidx, align 4 %add4 = fadd float %vecext, %1 - %2 = load float* %q, align 4 + %2 = load float, float* %q, align 4 %add6 = fadd float %vecext1, %2 - %arrayidx7 = getelementptr inbounds float* %q, i32 2 - %3 = load float* %arrayidx7, align 4 + %arrayidx7 = getelementptr inbounds float, float* %q, i32 2 + %3 = load float, float* %arrayidx7, align 4 %add8 = fadd float %vecext2, %3 br label %if.end @@ -231,7 +231,7 @@ bb3: ; preds = %bb12, %bb br i1 undef, label %bb10, label %bb12 bb10: ; preds = %bb3 - %tmp11 = load <4 x float>* undef, align 8 + %tmp11 = load <4 x float>, <4 x float>* undef, align 8 br label %bb12 bb12: ; preds = %bb10, %bb3 @@ -289,3 +289,71 @@ bb: %tmp18 = insertvalue %struct.wombat.5 %tmp17, <4 x float> undef, 3, 0 ret %struct.wombat.5 %tmp18 } + +; CHECK: adjustCopiesBackFrom +; The shuffle in if.else3 must be preserved even though adjustCopiesBackFrom +; is tempted to remove it. +; CHECK: vorr d +define internal void @adjustCopiesBackFrom(<2 x i64>* noalias nocapture sret %agg.result, <2 x i64> %in) { +entry: + %0 = extractelement <2 x i64> %in, i32 0 + %cmp = icmp slt i64 %0, 1 + %.in = select i1 %cmp, <2 x i64> , <2 x i64> %in + %1 = extractelement <2 x i64> %in, i32 1 + %cmp1 = icmp slt i64 %1, 1 + br i1 %cmp1, label %if.then2, label %if.else3 + +if.then2: ; preds = %entry + %2 = insertelement <2 x i64> %.in, i64 0, i32 1 + br label %if.end4 + +if.else3: ; preds = %entry + %3 = shufflevector <2 x i64> %.in, <2 x i64> %in, <2 x i32> + br label %if.end4 + +if.end4: ; preds = %if.else3, %if.then2 + %result.2 = phi <2 x i64> [ %2, %if.then2 ], [ %3, %if.else3 ] + store <2 x i64> %result.2, <2 x i64>* %agg.result, align 128 + ret void +} + +; +; RegisterCoalescer::updateRegDefsUses() could visit an instruction more than +; once under rare circumstances. When widening a register from QPR to DTriple +; with the original virtual register in dsub_1_dsub_2, the double rewrite would +; produce an invalid sub-register. +; +; This is because dsub_1_dsub_2 is not an idempotent sub-register index. +; It will translate %vr:dsub_0 -> %vr:dsub_1. +define hidden fastcc void @radar12758887() nounwind optsize ssp { +entry: + br i1 undef, label %for.body, label %for.end70 + +for.body: ; preds = %for.end, %entry + br i1 undef, label %for.body29, label %for.end + +for.body29: ; preds = %for.body29, %for.body + %0 = load <2 x double>, <2 x double>* null, align 1 + %splat40 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> zeroinitializer + %mul41 = fmul <2 x double> undef, %splat40 + %add42 = fadd <2 x double> undef, %mul41 + %splat44 = shufflevector <2 x double> %0, <2 x double> undef, <2 x i32> + %mul45 = fmul <2 x double> undef, %splat44 + %add46 = fadd <2 x double> undef, %mul45 + br i1 undef, label %for.end, label %for.body29 + +for.end: ; preds = %for.body29, %for.body + %accumR2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add42, %for.body29 ] + %accumI2.0.lcssa = phi <2 x double> [ zeroinitializer, %for.body ], [ %add46, %for.body29 ] + %1 = shufflevector <2 x double> %accumI2.0.lcssa, <2 x double> undef, <2 x i32> + %add58 = fadd <2 x double> undef, %1 + %mul61 = fmul <2 x double> %add58, undef + %add63 = fadd <2 x double> undef, %mul61 + %add64 = fadd <2 x double> undef, %add63 + %add67 = fadd <2 x double> undef, %add64 + store <2 x double> %add67, <2 x double>* undef, align 1 + br i1 undef, label %for.end70, label %for.body + +for.end70: ; preds = %for.end, %entry + ret void +}