X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FPowerPC%2Feqv-andc-orc-nor.ll;h=f90eccb359a89feef7c7bbc4bfed2f5bd755ece0;hb=0e1e8e2f620a3ff0d397b30ef0fc2c8e8d8f1aaf;hp=558fd1b3199b4d5345a4383db01f21b2c8eb81f4;hpb=fce288fc9134f0f1055caf0342c023225bd5c379;p=oota-llvm.git

diff --git a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
index 558fd1b3199..f90eccb359a 100644
--- a/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
+++ b/test/CodeGen/PowerPC/eqv-andc-orc-nor.ll
@@ -9,69 +9,69 @@
 ; RUN: llc < %s -march=ppc32 | \
 ; RUN:   grep nand | count 1
 
-define i32 @EQV1(i32 %X, i32 %Y) {
+define i32 @EQV1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, %Y		; <i32> [#uses=1]
 	%B = xor i32 %A, -1		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @EQV2(i32 %X, i32 %Y) {
+define i32 @EQV2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = xor i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @EQV3(i32 %X, i32 %Y) {
+define i32 @EQV3(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = xor i32 %Y, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ANDC1(i32 %X, i32 %Y) {
+define i32 @ANDC1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %Y, -1		; <i32> [#uses=1]
 	%B = and i32 %X, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ANDC2(i32 %X, i32 %Y) {
+define i32 @ANDC2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = and i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ORC1(i32 %X, i32 %Y) {
+define i32 @ORC1(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %Y, -1		; <i32> [#uses=1]
 	%B = or i32 %X, %A		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @ORC2(i32 %X, i32 %Y) {
+define i32 @ORC2(i32 %X, i32 %Y) nounwind {
 	%A = xor i32 %X, -1		; <i32> [#uses=1]
 	%B = or i32 %A, %Y		; <i32> [#uses=1]
 	ret i32 %B
 }
 
-define i32 @NOR1(i32 %X) {
+define i32 @NOR1(i32 %X) nounwind {
 	%Y = xor i32 %X, -1		; <i32> [#uses=1]
 	ret i32 %Y
 }
 
-define i32 @NOR2(i32 %X, i32 %Y) {
+define i32 @NOR2(i32 %X, i32 %Y) nounwind {
 	%Z = or i32 %X, %Y		; <i32> [#uses=1]
 	%R = xor i32 %Z, -1		; <i32> [#uses=1]
 	ret i32 %R
 }
 
-define i32 @NAND1(i32 %X, i32 %Y) {
+define i32 @NAND1(i32 %X, i32 %Y) nounwind {
 	%Z = and i32 %X, %Y		; <i32> [#uses=1]
 	%W = xor i32 %Z, -1		; <i32> [#uses=1]
 	ret i32 %W
 }
 
-define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
-	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
+define void @VNOR(<4 x float>* %P, <4 x float>* %Q) nounwind {
+	%tmp = load <4 x float>, <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.1 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]
+	%tmp2 = load <4 x float>, <4 x float>* %Q		; <<4 x float>> [#uses=1]
 	%tmp2.upgrd.2 = bitcast <4 x float> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp3 = or <4 x i32> %tmp.upgrd.1, %tmp2.upgrd.2		; <<4 x i32>> [#uses=1]
 	%tmp4 = xor <4 x i32> %tmp3, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
@@ -80,10 +80,10 @@ define void @VNOR(<4 x float>* %P, <4 x float>* %Q) {
 	ret void
 }
 
-define void @VANDC(<4 x float>* %P, <4 x float>* %Q) {
-	%tmp = load <4 x float>* %P		; <<4 x float>> [#uses=1]
+define void @VANDC(<4 x float>* %P, <4 x float>* %Q) nounwind {
+	%tmp = load <4 x float>, <4 x float>* %P		; <<4 x float>> [#uses=1]
 	%tmp.upgrd.4 = bitcast <4 x float> %tmp to <4 x i32>		; <<4 x i32>> [#uses=1]
-	%tmp2 = load <4 x float>* %Q		; <<4 x float>> [#uses=1]
+	%tmp2 = load <4 x float>, <4 x float>* %Q		; <<4 x float>> [#uses=1]
 	%tmp2.upgrd.5 = bitcast <4 x float> %tmp2 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp4 = xor <4 x i32> %tmp2.upgrd.5, < i32 -1, i32 -1, i32 -1, i32 -1 >		; <<4 x i32>> [#uses=1]
 	%tmp3 = and <4 x i32> %tmp.upgrd.4, %tmp4		; <<4 x i32>> [#uses=1]