X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FPowerPC%2Fvec_constants.ll;h=45df814365ec46f641e75f84301cd8649a46ecca;hb=0e1e8e2f620a3ff0d397b30ef0fc2c8e8d8f1aaf;hp=56b41b0f895582954846d2a3a75be6b71325adfd;hpb=abc402886e407e21d845cccc15723cffd6e2dc20;p=oota-llvm.git

diff --git a/test/CodeGen/PowerPC/vec_constants.ll b/test/CodeGen/PowerPC/vec_constants.ll
index 56b41b0f895..45df814365e 100644
--- a/test/CodeGen/PowerPC/vec_constants.ll
+++ b/test/CodeGen/PowerPC/vec_constants.ll
@@ -1,27 +1,30 @@
-; RUN: llc < %s -march=ppc32 -mcpu=g5 | FileCheck %s
+; RUN: llc -O0 -mcpu=pwr7 < %s | FileCheck %s
+
+target datalayout = "E-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-f128:128:128-v128:128:128-n32:64"
+target triple = "powerpc64-unknown-linux-gnu"
 
 define void @test1(<4 x i32>* %P1, <4 x i32>* %P2, <4 x float>* %P3) nounwind {
-	%tmp = load <4 x i32>* %P1		; <<4 x i32>> [#uses=1]
+	%tmp = load <4 x i32>, <4 x i32>* %P1		; <<4 x i32>> [#uses=1]
 	%tmp4 = and <4 x i32> %tmp, < i32 -2147483648, i32 -2147483648, i32 -2147483648, i32 -2147483648 >		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %tmp4, <4 x i32>* %P1
-	%tmp7 = load <4 x i32>* %P2		; <<4 x i32>> [#uses=1]
+	%tmp7 = load <4 x i32>, <4 x i32>* %P2		; <<4 x i32>> [#uses=1]
 	%tmp9 = and <4 x i32> %tmp7, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >		; <<4 x i32>> [#uses=1]
 	store <4 x i32> %tmp9, <4 x i32>* %P2
-	%tmp.upgrd.1 = load <4 x float>* %P3		; <<4 x float>> [#uses=1]
+	%tmp.upgrd.1 = load <4 x float>, <4 x float>* %P3		; <<4 x float>> [#uses=1]
 	%tmp11 = bitcast <4 x float> %tmp.upgrd.1 to <4 x i32>		; <<4 x i32>> [#uses=1]
 	%tmp12 = and <4 x i32> %tmp11, < i32 2147483647, i32 2147483647, i32 2147483647, i32 2147483647 >		; <<4 x i32>> [#uses=1]
 	%tmp13 = bitcast <4 x i32> %tmp12 to <4 x float>		; <<4 x float>> [#uses=1]
 	store <4 x float> %tmp13, <4 x float>* %P3
 	ret void
 
-; CHECK: test1:
+; CHECK-LABEL: test1:
 ; CHECK-NOT: CPI
 }
 
 define <4 x i32> @test_30() nounwind {
 	ret <4 x i32> < i32 30, i32 30, i32 30, i32 30 >
 
-; CHECK: test_30:
+; CHECK-LABEL: test_30:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vadduwm
 ; CHECK-NEXT: blr
@@ -30,7 +33,7 @@ define <4 x i32> @test_30() nounwind {
 define <4 x i32> @test_29() nounwind {
 	ret <4 x i32> < i32 29, i32 29, i32 29, i32 29 >
 
-; CHECK: test_29:
+; CHECK-LABEL: test_29:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vspltisw
 ; CHECK-NEXT: vsubuwm
@@ -40,7 +43,7 @@ define <4 x i32> @test_29() nounwind {
 define <8 x i16> @test_n30() nounwind {
 	ret <8 x i16> < i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30, i16 -30 >
 
-; CHECK: test_n30:
+; CHECK-LABEL: test_n30:
 ; CHECK: vspltish
 ; CHECK-NEXT: vadduhm
 ; CHECK-NEXT: blr
@@ -49,7 +52,7 @@ define <8 x i16> @test_n30() nounwind {
 define <16 x i8> @test_n104() nounwind {
 	ret <16 x i8> < i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104, i8 -104 >
 
-; CHECK: test_n104:
+; CHECK-LABEL: test_n104:
 ; CHECK: vspltisb
 ; CHECK-NEXT: vslb
 ; CHECK-NEXT: blr
@@ -58,7 +61,7 @@ define <16 x i8> @test_n104() nounwind {
 define <4 x i32> @test_vsldoi() nounwind {
 	ret <4 x i32> < i32 512, i32 512, i32 512, i32 512 >
 
-; CHECK: test_vsldoi:
+; CHECK-LABEL: test_vsldoi:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -67,7 +70,7 @@ define <4 x i32> @test_vsldoi() nounwind {
 define <8 x i16> @test_vsldoi_65023() nounwind {
 	ret <8 x i16> < i16 65023, i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023,i16 65023 >
 
-; CHECK: test_vsldoi_65023:
+; CHECK-LABEL: test_vsldoi_65023:
 ; CHECK: vspltish
 ; CHECK-NEXT: vsldoi
 ; CHECK-NEXT: blr
@@ -76,7 +79,7 @@ define <8 x i16> @test_vsldoi_65023() nounwind {
 define <4 x i32> @test_rol() nounwind {
 	ret <4 x i32> < i32 -11534337, i32 -11534337, i32 -11534337, i32 -11534337 >
 
-; CHECK: test_rol:
+; CHECK-LABEL: test_rol:
 ; CHECK: vspltisw
 ; CHECK-NEXT: vrlw
 ; CHECK-NEXT: blr