X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FSPARC%2F64cond.ll;h=e491d61aad27f1320568413bed6a2344bfc7d971;hb=00552e3875ee5f382db6c98286a241a7d0efe1b8;hp=88b476d1a24261dc859ca2036f16c9aca98556c1;hpb=65ca7aa57d5e9b391f02a5686e7622deaac146f9;p=oota-llvm.git

diff --git a/test/CodeGen/SPARC/64cond.ll b/test/CodeGen/SPARC/64cond.ll
index 88b476d1a24..e491d61aad2 100644
--- a/test/CodeGen/SPARC/64cond.ll
+++ b/test/CodeGen/SPARC/64cond.ll
@@ -2,8 +2,8 @@
 ; Testing 64-bit conditionals. The sparc64 triple is an alias for sparcv9.
 
 ; CHECK: cmpri
-; CHECK: subcc %i1, 1
-; CHECK: bpe %xcc,
+; CHECK: cmp %i1, 1
+; CHECK: be %xcc,
 define void @cmpri(i64* %p, i64 %x) {
 entry:
   %tobool = icmp eq i64 %x, 1
@@ -18,8 +18,8 @@ if.end:
 }
 
 ; CHECK: cmprr
-; CHECK: subcc %i1, %i2
-; CHECK: bpgu %xcc,
+; CHECK: cmp %i1, %i2
+; CHECK: bgu %xcc,
 define void @cmprr(i64* %p, i64 %x, i64 %y) {
 entry:
   %tobool = icmp ugt i64 %x, %y
@@ -34,7 +34,7 @@ if.end:
 }
 
 ; CHECK: selecti32_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %xcc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i32 @selecti32_xcc(i64 %x, i64 %y, i32 %a, i32 %b) {
@@ -45,7 +45,7 @@ entry:
 }
 
 ; CHECK: selecti64_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %xcc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i64 @selecti64_xcc(i64 %x, i64 %y, i64 %a, i64 %b) {
@@ -56,7 +56,7 @@ entry:
 }
 
 ; CHECK: selecti64_icc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: movg %icc, %i2, %i3
 ; CHECK: restore %g0, %i3, %o0
 define i64 @selecti64_icc(i32 %x, i32 %y, i64 %a, i64 %b) {
@@ -78,9 +78,9 @@ entry:
 }
 
 ; CHECK: selectf32_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: fmovsg %xcc, %f5, %f7
-; CHECK: fmovs %f7, %f1
+; CHECK: fmovs %f7, %f0
 define float @selectf32_xcc(i64 %x, i64 %y, float %a, float %b) {
 entry:
   %tobool = icmp sgt i64 %x, %y
@@ -89,7 +89,7 @@ entry:
 }
 
 ; CHECK: selectf64_xcc
-; CHECK: subcc %i0, %i1
+; CHECK: cmp %i0, %i1
 ; CHECK: fmovdg %xcc, %f4, %f6
 ; CHECK: fmovd %f6, %f0
 define double @selectf64_xcc(i64 %x, i64 %y, double %a, double %b) {
@@ -101,11 +101,30 @@ entry:
 
 ; The MOVXCC instruction can't use %g0 for its tied operand.
 ; CHECK: select_consti64_xcc
-; CHECK: subcc
-; CHECK: movg %xcc, 123, %i0
+; CHECK: cmp
+; CHECK: movg %xcc, 123, %i{{[0-2]}}
 define i64 @select_consti64_xcc(i64 %x, i64 %y) {
 entry:
   %tobool = icmp sgt i64 %x, %y
   %rv = select i1 %tobool, i64 123, i64 0
   ret i64 %rv
 }
+
+; CHECK-LABEL: setcc_resultty
+; CHECK-DAG:       srax %i0, 63, %o0
+; CHECK-DAG:       mov %i0, %o1
+; CHECK-DAG:       mov 0, %o2
+; CHECK-DAG:       mov 32, %o3
+; CHECK-DAG:       call __multi3
+; CHECK:       cmp
+; CHECK:       movne %xcc, 1, [[R:%[gilo][0-7]]]
+; CHECK:       or [[R]], %i1, %i0
+
+define i1 @setcc_resultty(i64 %a, i1 %b) {
+  %a0 = tail call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %a, i64 32)
+  %a1 = extractvalue { i64, i1 } %a0, 1
+  %a4 = or i1 %a1, %b
+  ret i1 %a4
+}
+
+declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64)