X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=test%2FCodeGen%2FThumb2%2Fmachine-licm.ll;h=c57274ea55992313c67d7a6bfda118c587054432;hb=HEAD;hp=98acc2803f05132d74dac755c73838df1a91b337;hpb=9085f98b32775aa0190eac221a58350d837ae2c3;p=oota-llvm.git diff --git a/test/CodeGen/Thumb2/machine-licm.ll b/test/CodeGen/Thumb2/machine-licm.ll index 98acc2803f0..c57274ea559 100644 --- a/test/CodeGen/Thumb2/machine-licm.ll +++ b/test/CodeGen/Thumb2/machine-licm.ll @@ -1,46 +1,42 @@ -; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -disable-fp-elim | FileCheck %s +; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=dynamic-no-pic -disable-fp-elim | FileCheck %s ; RUN: llc < %s -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -relocation-model=pic -disable-fp-elim | FileCheck %s --check-prefix=PIC ; rdar://7353541 ; rdar://7354376 -; The generated code is no where near ideal. It's not recognizing the two -; constantpool entries being loaded can be merged into one. - @GV = external global i32 ; [#uses=2] -define arm_apcscc void @t1(i32* nocapture %vals, i32 %c) nounwind { +define void @t1(i32* nocapture %vals, i32 %c) nounwind { entry: -; CHECK: t1: -; CHECK: cbz +; CHECK-LABEL: t1: +; CHECK: bxeq lr + %0 = icmp eq i32 %c, 0 ; [#uses=1] br i1 %0, label %return, label %bb.nph bb.nph: ; preds = %entry -; CHECK: BB#1 -; CHECK: ldr.n r2, LCPI0_0 -; CHECK: ldr r2, [r2] -; CHECK: ldr r3, [r2] -; CHECK: LBB0_2 -; CHECK: LCPI0_0: -; CHECK-NOT: LCPI0_1: - -; PIC: BB#1 -; PIC: ldr.n r2, LCPI0_0 -; PIC: add r2, pc -; PIC: ldr r2, [r2] -; PIC: ldr r3, [r2] -; PIC: LBB0_2 -; PIC: LCPI0_0: -; PIC-NOT: LCPI0_1: +; CHECK: movw r[[R2:[0-9]+]], :lower16:L_GV$non_lazy_ptr +; CHECK: movt r[[R2]], :upper16:L_GV$non_lazy_ptr +; CHECK: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; CHECK: ldr{{.*}}, [r[[R2b]] +; CHECK: LBB0_ +; CHECK-NOT: LCPI0_0: + +; PIC: movw r[[R2:[0-9]+]], :lower16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: movt r[[R2]], :upper16:(L_GV$non_lazy_ptr-(LPC0_0+4)) +; PIC: add r[[R2]], pc +; PIC: ldr{{(.w)?}} r[[R2b:[0-9]+]], [r[[R2]] +; PIC: ldr{{.*}}, [r[[R2b]] +; PIC: LBB0_ +; PIC-NOT: LCPI0_0: ; PIC: .section - %.pre = load i32* @GV, align 4 ; [#uses=1] + %.pre = load i32, i32* @GV, align 4 ; [#uses=1] br label %bb bb: ; preds = %bb, %bb.nph %1 = phi i32 [ %.pre, %bb.nph ], [ %3, %bb ] ; [#uses=1] %i.03 = phi i32 [ 0, %bb.nph ], [ %4, %bb ] ; [#uses=2] - %scevgep = getelementptr i32* %vals, i32 %i.03 ; [#uses=1] - %2 = load i32* %scevgep, align 4 ; [#uses=1] + %scevgep = getelementptr i32, i32* %vals, i32 %i.03 ; [#uses=1] + %2 = load i32, i32* %scevgep, align 4 ; [#uses=1] %3 = add nsw i32 %1, %2 ; [#uses=2] store i32 %3, i32* @GV, align 4 %4 = add i32 %i.03, 1 ; [#uses=2] @@ -52,22 +48,21 @@ return: ; preds = %bb, %entry } ; rdar://8001136 -define arm_apcscc void @t2(i8* %ptr1, i8* %ptr2) nounwind { +define void @t2(i8* %ptr1, i8* %ptr2) nounwind { entry: -; CHECK: t2: -; CHECK: adr r{{.}}, #LCPI1_0 -; CHECK: vldmia r3, {d0,d1} +; CHECK-LABEL: t2: +; CHECK: vmov.f32 q{{.*}}, #1.000000e+00 br i1 undef, label %bb1, label %bb2 bb1: -; CHECK-NEXT: %bb1 +; CHECK: %bb1 %indvar = phi i32 [ %indvar.next, %bb1 ], [ 0, %entry ] %tmp1 = shl i32 %indvar, 2 - %gep1 = getelementptr i8* %ptr1, i32 %tmp1 - %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32(i8* %gep1) + %gep1 = getelementptr i8, i8* %ptr1, i32 %tmp1 + %tmp2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %gep1, i32 1) %tmp3 = call <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float> , <4 x float> %tmp2) - %gep2 = getelementptr i8* %ptr2, i32 %tmp1 - call void @llvm.arm.neon.vst1.v4f32(i8* %gep2, <4 x float> %tmp3) + %gep2 = getelementptr i8, i8* %ptr2, i32 %tmp1 + call void @llvm.arm.neon.vst1.p0i8.v4f32(i8* %gep2, <4 x float> %tmp3, i32 1) %indvar.next = add i32 %indvar, 1 %cond = icmp eq i32 %indvar.next, 10 br i1 %cond, label %bb2, label %bb1 @@ -76,11 +71,50 @@ bb2: ret void } -; CHECK: LCPI1_0: -; CHECK: .section +; CHECK-NOT: LCPI1_0: -declare <4 x float> @llvm.arm.neon.vld1.v4f32(i8*) nounwind readonly +declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly -declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>) nounwind +declare void @llvm.arm.neon.vst1.p0i8.v4f32(i8*, <4 x float>, i32) nounwind declare <4 x float> @llvm.arm.neon.vmaxs.v4f32(<4 x float>, <4 x float>) nounwind readnone + +; rdar://8241368 +; isel should not fold immediate into eor's which would have prevented LICM. +define zeroext i16 @t3(i8 zeroext %data, i16 zeroext %crc) nounwind readnone { +; CHECK-LABEL: t3: +bb.nph: +; CHECK: bb.nph +; CHECK: movw {{(r[0-9])|(lr)}}, #32768 +; CHECK: movs {{(r[0-9]+)|(lr)}}, #0 +; CHECK: movw [[REGISTER:(r[0-9]+)|(lr)]], #16386 +; CHECK: movw {{(r[0-9]+)|(lr)}}, #65534 +; CHECK: movt {{(r[0-9]+)|(lr)}}, #65535 + br label %bb + +bb: ; preds = %bb, %bb.nph +; CHECK: bb +; CHECK: eor.w +; CHECK: eorne.w {{(r[0-9])|(lr)}}, {{(r[0-9])|(lr)}}, [[REGISTER]] +; CHECK-NOT: eor +; CHECK: and + %data_addr.013 = phi i8 [ %data, %bb.nph ], [ %8, %bb ] ; [#uses=2] + %crc_addr.112 = phi i16 [ %crc, %bb.nph ], [ %crc_addr.2, %bb ] ; [#uses=3] + %i.011 = phi i8 [ 0, %bb.nph ], [ %7, %bb ] ; [#uses=1] + %0 = trunc i16 %crc_addr.112 to i8 ; [#uses=1] + %1 = xor i8 %data_addr.013, %0 ; [#uses=1] + %2 = and i8 %1, 1 ; [#uses=1] + %3 = icmp eq i8 %2, 0 ; [#uses=2] + %4 = xor i16 %crc_addr.112, 16386 ; [#uses=1] + %crc_addr.0 = select i1 %3, i16 %crc_addr.112, i16 %4 ; [#uses=1] + %5 = lshr i16 %crc_addr.0, 1 ; [#uses=2] + %6 = or i16 %5, -32768 ; [#uses=1] + %crc_addr.2 = select i1 %3, i16 %5, i16 %6 ; [#uses=2] + %7 = add i8 %i.011, 1 ; [#uses=2] + %8 = lshr i8 %data_addr.013, 1 ; [#uses=1] + %exitcond = icmp eq i8 %7, 8 ; [#uses=1] + br i1 %exitcond, label %bb8, label %bb + +bb8: ; preds = %bb + ret i16 %crc_addr.2 +}