X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FARMDecoderEmitter.cpp;h=e48ac1e67882b930fc363bc93da7c422e4030b96;hb=234823297e0fc0babddd2ab84054bf68f64a54d1;hp=b174fa961add9a3aa290191d19e244e308716e70;hpb=e6d69e7dbee88a0a88f252a3e1e3f5f81472cf4b;p=oota-llvm.git diff --git a/utils/TableGen/ARMDecoderEmitter.cpp b/utils/TableGen/ARMDecoderEmitter.cpp index b174fa961ad..e48ac1e6788 100644 --- a/utils/TableGen/ARMDecoderEmitter.cpp +++ b/utils/TableGen/ARMDecoderEmitter.cpp @@ -1382,7 +1382,7 @@ bool ARMFilterChooser::emit(raw_ostream &o, unsigned &Indentation) { // 2. source registers are identical => VMOVQ; otherwise => VORRq // 3. LDR, LDRcp => return LDR for now. // FIXME: How can we distinguish between LDR and LDRcp? Do we need to? - // 4. tLDM, tLDM_UPD => Rn = Inst{10-8}, reglist = Inst{7-0}, + // 4. tLDMIA, tLDMIA_UPD => Rn = Inst{10-8}, reglist = Inst{7-0}, // wback = registers = 0 // NOTE: (tLDM, tLDM_UPD) resolution must come before Advanced SIMD // addressing mode resolution!!! @@ -1423,7 +1423,7 @@ bool ARMFilterChooser::emit(raw_ostream &o, unsigned &Indentation) { << "; // Returning LDR for {LDR, LDRcp}\n"; return true; } - if (name1 == "tLDM" && name2 == "tLDM_UPD") { + if (name1 == "tLDMIA" && name2 == "tLDMIA_UPD") { // Inserting the opening curly brace for this case block. --Indentation; --Indentation; o.indent(Indentation) << "{\n"; @@ -1615,6 +1615,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, if (!thumbInstruction(Form)) return false; + // A8.6.189 STM / STMIA / STMEA -- Encoding T1 + // There's only STMIA_UPD for Thumb1. + if (Name == "tSTMIA") + return false; + // On Darwin R9 is call-clobbered. Ignore the non-Darwin counterparts. if (Name == "tBL" || Name == "tBLXi" || Name == "tBLXr") return false; @@ -1627,6 +1632,11 @@ ARMDEBackend::populateInstruction(const CodeGenInstruction &CGI, if (Name == "tADR") return false; + // Delegate t2ADR disassembly to the more generic t2ADDri12/t2SUBri12 + // instructions. + if (Name == "t2ADR") + return false; + // Ignore tADDrSP, tADDspr, and tPICADD, prefer the generic tADDhirr. // Ignore t2SUBrSPs, prefer the t2SUB[S]r[r|s]. // Ignore t2ADDrSPs, prefer the t2ADD[S]r[r|s].