X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FAsmMatcherEmitter.cpp;h=1fb92ee733ae1000a0bffb02bd0b007ea9fa8401;hb=bea6f615eefae279e53bbb63a31d2c3c67274c45;hp=23d370c506e3fd91271b98d72a661b479f7c7fa4;hpb=5bde7345980587284bda6d42a68cdb151fbf5d6b;p=oota-llvm.git diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index 23d370c506e..1fb92ee733a 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -8,7 +8,11 @@ //===----------------------------------------------------------------------===// // // This tablegen backend emits a target specifier matcher for converting parsed -// assembly operands in the MCInst structures. +// assembly operands in the MCInst structures. It also emits a matcher for +// custom operand parsing. +// +// Converting assembly operands into MCInst structures +// --------------------------------------------------- // // The input to the target specific matcher is a list of literal tokens and // operands. The target specific parser should generally eliminate any syntax @@ -68,10 +72,33 @@ // instruction (we currently ignore cases where this isn't true, whee!!!), // which we can emit a simple matcher for. // +// Custom Operand Parsing +// ---------------------- +// +// Some targets need a custom way to parse operands, some specific instructions +// can contain arguments that can represent processor flags and other kinds of +// identifiers that need to be mapped to specific valeus in the final encoded +// instructions. The target specific custom operand parsing works in the +// following way: +// +// 1. A operand match table is built, each entry contains a mnemonic, an +// operand class, a mask for all operand positions for that same +// class/mnemonic and target features to be checked while trying to match. +// +// 2. The operand matcher will try every possible entry with the same +// mnemonic and will check if the target feature for this mnemonic also +// matches. After that, if the operand to be matched has its index +// present in the mask, a successful match occurs. Otherwise, fallback +// to the regular operand parsing. +// +// 3. For a match success, each operand class that has a 'ParserMethod' +// becomes part of a switch from where the custom method is called. +// //===----------------------------------------------------------------------===// #include "AsmMatcherEmitter.h" #include "CodeGenTarget.h" +#include "Error.h" #include "Record.h" #include "StringMatcher.h" #include "llvm/ADT/OwningPtr.h" @@ -90,9 +117,8 @@ static cl::opt MatchPrefix("match-prefix", cl::init(""), cl::desc("Only match instructions with the given prefix")); - namespace { - class AsmMatcherInfo; +class AsmMatcherInfo; struct SubtargetFeatureInfo; /// ClassInfo - Helper class for storing the information about a particular @@ -142,6 +168,10 @@ struct ClassInfo { /// MCInst; this is not valid for Token or register kinds. std::string RenderMethod; + /// ParserMethod - The name of the operand method to do a target specific + /// parsing on the operand. + std::string ParserMethod; + /// For register classes, the records for all the registers in this class. std::set Registers; @@ -229,7 +259,7 @@ public: return ValueName < RHS.ValueName; default: - // This class preceeds the RHS if it is a proper subset of the RHS. + // This class precedes the RHS if it is a proper subset of the RHS. if (isSubsetOf(RHS)) return true; if (RHS.isSubsetOf(*this)) @@ -247,16 +277,19 @@ struct MatchableInfo { struct AsmOperand { /// Token - This is the token that the operand came from. StringRef Token; - + /// The unique class instance this operand should match. ClassInfo *Class; /// The operand name this is, if anything. StringRef SrcOpName; - - explicit AsmOperand(StringRef T) : Token(T), Class(0) {} + + /// The suboperand index within SrcOpName, or -1 for the entire operand. + int SubOpIdx; + + explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {} }; - + /// ResOperand - This represents a single operand in the result instruction /// generated by the match. In cases (like addressing modes) where a single /// assembler operand expands to multiple MCOperands, this represents the @@ -267,41 +300,68 @@ struct MatchableInfo { /// generated by calling the render method on the assembly operand. The /// corresponding AsmOperand is specified by AsmOperandNum. RenderAsmOperand, - + /// TiedOperand - This represents a result operand that is a duplicate of /// a previous result operand. - TiedOperand + TiedOperand, + + /// ImmOperand - This represents an immediate value that is dumped into + /// the operand. + ImmOperand, + + /// RegOperand - This represents a fixed register that is dumped in. + RegOperand } Kind; - + union { /// This is the operand # in the AsmOperands list that this should be /// copied from. unsigned AsmOperandNum; - + /// TiedOperandNum - This is the (earlier) result operand that should be /// copied from. unsigned TiedOperandNum; + + /// ImmVal - This is the immediate value added to the instruction. + int64_t ImmVal; + + /// Register - This is the register record. + Record *Register; }; - - /// OpInfo - This is the information about the instruction operand that is - /// being populated. - const CGIOperandList::OperandInfo *OpInfo; - - static ResOperand getRenderedOp(unsigned AsmOpNum, - const CGIOperandList::OperandInfo *Op) { + + /// MINumOperands - The number of MCInst operands populated by this + /// operand. + unsigned MINumOperands; + + static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) { ResOperand X; X.Kind = RenderAsmOperand; X.AsmOperandNum = AsmOpNum; - X.OpInfo = Op; + X.MINumOperands = NumOperands; return X; } - - static ResOperand getTiedOp(unsigned TiedOperandNum, - const CGIOperandList::OperandInfo *Op) { + + static ResOperand getTiedOp(unsigned TiedOperandNum) { ResOperand X; X.Kind = TiedOperand; X.TiedOperandNum = TiedOperandNum; - X.OpInfo = Op; + X.MINumOperands = 1; + return X; + } + + static ResOperand getImmOp(int64_t Val) { + ResOperand X; + X.Kind = ImmOperand; + X.ImmVal = Val; + X.MINumOperands = 1; + return X; + } + + static ResOperand getRegOp(Record *Reg) { + ResOperand X; + X.Kind = RegOperand; + X.Register = Reg; + X.MINumOperands = 1; return X; } }; @@ -309,16 +369,16 @@ struct MatchableInfo { /// TheDef - This is the definition of the instruction or InstAlias that this /// matchable came from. Record *const TheDef; - + /// DefRec - This is the definition that it came from. PointerUnion DefRec; - + const CodeGenInstruction *getResultInst() const { if (DefRec.is()) return DefRec.get(); return DefRec.get()->ResultInst; } - + /// ResOperands - This is the operand list that should be built for the result /// MCInst. std::vector ResOperands; @@ -330,7 +390,7 @@ struct MatchableInfo { /// Mnemonic - This is the first token of the matched instruction, its /// mnemonic. StringRef Mnemonic; - + /// AsmOperands - The textual operands that this instruction matches, /// annotated with a class and where in the OperandList they were defined. /// This directly corresponds to the tokenized AsmString after the mnemonic is @@ -344,7 +404,7 @@ struct MatchableInfo { /// ConvertToMCInst to convert parsed operands into an MCInst for this /// function. std::string ConversionFnKind; - + MatchableInfo(const CodeGenInstruction &CGI) : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { } @@ -352,26 +412,38 @@ struct MatchableInfo { MatchableInfo(const CodeGenInstAlias *Alias) : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) { } - + void Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters); - + /// Validate - Return true if this matchable is a valid thing to match against /// and perform a bunch of validity checking. bool Validate(StringRef CommentDelimiter, bool Hack) const; - + /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the Record for it, otherwise return null. Record *getSingletonRegisterForAsmOperand(unsigned i, - const AsmMatcherInfo &Info) const; + const AsmMatcherInfo &Info) const; + /// FindAsmOperand - Find the AsmOperand with the specified name and + /// suboperand index. + int FindAsmOperand(StringRef N, int SubOpIdx) const { + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (N == AsmOperands[i].SrcOpName && + SubOpIdx == AsmOperands[i].SubOpIdx) + return i; + return -1; + } + + /// FindAsmOperandNamed - Find the first AsmOperand with the specified name. + /// This does not check the suboperand index. int FindAsmOperandNamed(StringRef N) const { for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) if (N == AsmOperands[i].SrcOpName) return i; return -1; } - + void BuildInstructionResultOperands(); void BuildAliasResultOperands(); @@ -385,7 +457,7 @@ struct MatchableInfo { return AsmOperands.size() < RHS.AsmOperands.size(); // Compare lexicographically by operand. The matcher validates that other - // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith(). + // orderings wouldn't be ambiguous using \see CouldMatchAmbiguouslyWith(). for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) return true; @@ -396,14 +468,14 @@ struct MatchableInfo { return false; } - /// CouldMatchAmiguouslyWith - Check whether this matchable could + /// CouldMatchAmbiguouslyWith - Check whether this matchable could /// ambiguously match the same set of operands as \arg RHS (without being a /// strictly superior match). - bool CouldMatchAmiguouslyWith(const MatchableInfo &RHS) { + bool CouldMatchAmbiguouslyWith(const MatchableInfo &RHS) { // The primary comparator is the instruction mnemonic. if (Mnemonic != RHS.Mnemonic) return false; - + // The number of operands is unambiguous. if (AsmOperands.size() != RHS.AsmOperands.size()) return false; @@ -436,7 +508,7 @@ struct MatchableInfo { } void dump(); - + private: void TokenizeAsmString(const AsmMatcherInfo &Info); }; @@ -451,15 +523,34 @@ struct SubtargetFeatureInfo { unsigned Index; SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} - + /// \brief The name of the enumerated constant identifying this feature. std::string getEnumName() const { return "Feature_" + TheDef->getName(); } }; +struct OperandMatchEntry { + unsigned OperandMask; + MatchableInfo* MI; + ClassInfo *CI; + + static OperandMatchEntry Create(MatchableInfo* mi, ClassInfo *ci, + unsigned opMask) { + OperandMatchEntry X; + X.OperandMask = opMask; + X.CI = ci; + X.MI = mi; + return X; + } +}; + + class AsmMatcherInfo { public: + /// Tracked Records + RecordKeeper &Records; + /// The tablegen AsmParser record. Record *AsmParser; @@ -475,12 +566,15 @@ public: /// The information on the matchables to match. std::vector Matchables; + /// Info for custom matching operands by user defined methods. + std::vector OperandMatchInfo; + /// Map of Register records to their class information. std::map RegisterClasses; /// Map of Predicate records to their subtarget information. std::map SubtargetFeatures; - + private: /// Map of token to class information which has already been constructed. std::map TokenClasses; @@ -496,7 +590,8 @@ private: ClassInfo *getTokenClass(StringRef Token); /// getOperandClass - Lookup or create the class for the given operand. - ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI); + ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI, + int SubOpIdx = -1); /// BuildRegisterClasses - Build the ClassInfo* instances for register /// classes. @@ -506,19 +601,23 @@ private: /// operand classes. void BuildOperandClasses(); - void BuildInstructionOperandReference(MatchableInfo *II, - StringRef OpName, - MatchableInfo::AsmOperand &Op); - void BuildAliasOperandReference(MatchableInfo *II, - StringRef OpName, + void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName, + unsigned AsmOpIdx); + void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName, MatchableInfo::AsmOperand &Op); - + public: - AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); + AsmMatcherInfo(Record *AsmParser, + CodeGenTarget &Target, + RecordKeeper &Records); /// BuildInfo - Construct the various tables used during matching. void BuildInfo(); - + + /// BuildOperandMatchInfo - Build the necessary information to handle user + /// defined operand parsing methods. + void BuildOperandMatchInfo(); + /// getSubtargetFeature - Lookup or create the subtarget feature info for the /// given operand. SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { @@ -527,6 +626,10 @@ public: SubtargetFeatures.find(Def); return I == SubtargetFeatures.end() ? 0 : I->second; } + + RecordKeeper &getRecords() const { + return Records; + } }; } @@ -538,16 +641,6 @@ void MatchableInfo::dump() { AsmOperand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; errs() << '\"' << Op.Token << "\"\n"; -#if 0 - if (!Op.OperandInfo) { - errs() << "(singleton register)\n"; - continue; - } - - const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; - errs() << OI.Name << " " << OI.Rec->getName() - << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; -#endif } } @@ -555,16 +648,16 @@ void MatchableInfo::Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters) { // TODO: Eventually support asmparser for Variant != 0. AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); - + TokenizeAsmString(Info); - + // Compute the require features. std::vector Predicates =TheDef->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) if (SubtargetFeatureInfo *Feature = Info.getSubtargetFeature(Predicates[i])) RequiredFeatures.push_back(Feature); - + // Collect singleton registers, if used. for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) @@ -607,21 +700,17 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { break; case '$': { + if (InTok) { + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + InTok = false; + } + // If this isn't "${", treat like a normal token. if (i + 1 == String.size() || String[i + 1] != '{') { - if (InTok) { - AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); - InTok = false; - } Prev = i; break; } - if (InTok) { - AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); - InTok = false; - } - StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); assert(End != String.end() && "Missing brace in operand reference!"); size_t EndPos = End - String.begin(); @@ -644,7 +733,7 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { } if (InTok && Prev != String.size()) AsmOperands.push_back(AsmOperand(String.substr(Prev))); - + // The first token of the instruction is the mnemonic, which must be a // simple string, not a $foo variable or a singleton register. assert(!AsmOperands.empty() && "Instruction has no tokens?"); @@ -652,25 +741,23 @@ void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) throw TGError(TheDef->getLoc(), "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); - + // Remove the first operand, it is tracked in the mnemonic field. AsmOperands.erase(AsmOperands.begin()); } - - bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { // Reject matchables with no .s string. if (AsmString.empty()) throw TGError(TheDef->getLoc(), "instruction with empty asm string"); - + // Reject any matchables with a newline in them, they should be marked // isCodeGenOnly if they are pseudo instructions. if (AsmString.find('\n') != std::string::npos) throw TGError(TheDef->getLoc(), "multiline instruction is not valid for the asmparser, " "mark it isCodeGenOnly"); - + // Remove comments from the asm string. We know that the asmstring only // has one line. if (!CommentDelimiter.empty() && @@ -678,10 +765,10 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { throw TGError(TheDef->getLoc(), "asmstring for instruction has comment character in it, " "mark it isCodeGenOnly"); - + // Reject matchables with operand modifiers, these aren't something we can - /// handle, the target should be refactored to use operands instead of - /// modifiers. + // handle, the target should be refactored to use operands instead of + // modifiers. // // Also, check for instructions which reference the operand multiple times; // this implies a constraint we would not honor. @@ -692,7 +779,7 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { throw TGError(TheDef->getLoc(), "matchable with operand modifier '" + Tok.str() + "' not supported by asm matcher. Mark isCodeGenOnly!"); - + // Verify that any operand is only mentioned once. // We reject aliases and ignore instructions for now. if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { @@ -710,11 +797,10 @@ bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { return false; } } - + return true; } - /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the register name, otherwise return a null StringRef. Record *MatchableInfo:: @@ -722,16 +808,16 @@ getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ StringRef Tok = AsmOperands[i].Token; if (!Tok.startswith(Info.RegisterPrefix)) return 0; - + StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) return Reg->TheDef; - + // If there is no register prefix (i.e. "%" in "%eax"), then this may // be some random non-register token, just ignore it. if (Info.RegisterPrefix.empty()) return 0; - + // Otherwise, we have something invalid prefixed with the register prefix, // such as %foo. std::string Err = "unable to find register for '" + RegName.str() + @@ -739,7 +825,6 @@ getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ throw TGError(TheDef->getLoc(), Err); } - static std::string getEnumNameForToken(StringRef Str) { std::string Res; @@ -748,6 +833,8 @@ static std::string getEnumNameForToken(StringRef Str) { case '*': Res += "_STAR_"; break; case '%': Res += "_PCT_"; break; case ':': Res += "_COLON_"; break; + case '!': Res += "_EXCLAIM_"; break; + case '.': Res += "_DOT_"; break; default: if (isalnum(*it)) Res += *it; @@ -770,6 +857,7 @@ ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { Entry->ValueName = Token; Entry->PredicateMethod = ""; Entry->RenderMethod = ""; + Entry->ParserMethod = ""; Classes.push_back(Entry); } @@ -777,24 +865,55 @@ ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { } ClassInfo * -AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI) { - if (OI.Rec->isSubClassOf("RegisterClass")) { - if (ClassInfo *CI = RegisterClassClasses[OI.Rec]) +AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, + int SubOpIdx) { + Record *Rec = OI.Rec; + if (SubOpIdx != -1) + Rec = dynamic_cast(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); + + if (Rec->isSubClassOf("RegisterOperand")) { + // RegisterOperand may have an associated ParserMatchClass. If it does, + // use it, else just fall back to the underlying register class. + const RecordVal *R = Rec->getValue("ParserMatchClass"); + if (R == 0 || R->getValue() == 0) + throw "Record `" + Rec->getName() + + "' does not have a ParserMatchClass!\n"; + + if (DefInit *DI= dynamic_cast(R->getValue())) { + Record *MatchClass = DI->getDef(); + if (ClassInfo *CI = AsmOperandClasses[MatchClass]) + return CI; + } + + // No custom match class. Just use the register class. + Record *ClassRec = Rec->getValueAsDef("RegClass"); + if (!ClassRec) + throw TGError(Rec->getLoc(), "RegisterOperand `" + Rec->getName() + + "' has no associated register class!\n"); + if (ClassInfo *CI = RegisterClassClasses[ClassRec]) return CI; - throw TGError(OI.Rec->getLoc(), "register class has no class info!"); + throw TGError(Rec->getLoc(), "register class has no class info!"); } - assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!"); - Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass"); + + if (Rec->isSubClassOf("RegisterClass")) { + if (ClassInfo *CI = RegisterClassClasses[Rec]) + return CI; + throw TGError(Rec->getLoc(), "register class has no class info!"); + } + + assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); + Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); if (ClassInfo *CI = AsmOperandClasses[MatchClass]) return CI; - throw TGError(OI.Rec->getLoc(), "operand has no match class!"); + throw TGError(Rec->getLoc(), "operand has no match class!"); } void AsmMatcherInfo:: BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { - const std::vector &Registers = Target.getRegisters(); + const std::vector &Registers = + Target.getRegBank().getRegisters(); const std::vector &RegClassList = Target.getRegisterClasses(); @@ -804,8 +923,8 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { // Gather the defined sets. for (std::vector::const_iterator it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) - RegisterSets.insert(std::set(it->Elements.begin(), - it->Elements.end())); + RegisterSets.insert(std::set(it->getOrder().begin(), + it->getOrder().end())); // Add any required singleton sets. for (SmallPtrSet::iterator it = SingletonRegisters.begin(), @@ -818,9 +937,9 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { // a unique register set class), and build the mapping of registers to the set // they should classify to. std::map > RegisterMap; - for (std::vector::const_iterator it = Registers.begin(), + for (std::vector::const_iterator it = Registers.begin(), ie = Registers.end(); it != ie; ++it) { - const CodeGenRegister &CGR = *it; + const CodeGenRegister &CGR = **it; // Compute the intersection of all sets containing this register. std::set ContainingSet; @@ -833,7 +952,7 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { ContainingSet = *it; continue; } - + std::set Tmp; std::swap(Tmp, ContainingSet); std::insert_iterator< std::set > II(ContainingSet, @@ -879,8 +998,8 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { // Name the register classes which correspond to a user defined RegisterClass. for (std::vector::const_iterator it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { - ClassInfo *CI = RegisterSetClasses[std::set(it->Elements.begin(), - it->Elements.end())]; + ClassInfo *CI = RegisterSetClasses[std::set(it->getOrder().begin(), + it->getOrder().end())]; if (CI->ValueName.empty()) { CI->ClassName = it->getName(); CI->Name = "MCK_" + it->getName(); @@ -965,16 +1084,56 @@ void AsmMatcherInfo::BuildOperandClasses() { CI->RenderMethod = "add" + CI->ClassName + "Operands"; } + // Get the parse method name or leave it as empty. + Init *PRMName = (*it)->getValueInit("ParserMethod"); + if (StringInit *SI = dynamic_cast(PRMName)) + CI->ParserMethod = SI->getValue(); + AsmOperandClasses[*it] = CI; Classes.push_back(CI); } } -AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target) - : AsmParser(asmParser), Target(target), +AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, + CodeGenTarget &target, + RecordKeeper &records) + : Records(records), AsmParser(asmParser), Target(target), RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { } +/// BuildOperandMatchInfo - Build the necessary information to handle user +/// defined operand parsing methods. +void AsmMatcherInfo::BuildOperandMatchInfo() { + + /// Map containing a mask with all operands indicies that can be found for + /// that class inside a instruction. + std::map OpClassMask; + + for (std::vector::const_iterator it = + Matchables.begin(), ie = Matchables.end(); + it != ie; ++it) { + MatchableInfo &II = **it; + OpClassMask.clear(); + + // Keep track of all operands of this instructions which belong to the + // same class. + for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { + MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; + if (Op.Class->ParserMethod.empty()) + continue; + unsigned &OperandMask = OpClassMask[Op.Class]; + OperandMask |= (1 << i); + } + + // Generate operand match info for each mnemonic/operand class pair. + for (std::map::iterator iit = OpClassMask.begin(), + iie = OpClassMask.end(); iit != iie; ++iit) { + unsigned OpMask = iit->second; + ClassInfo *CI = iit->first; + OperandMatchInfo.push_back(OperandMatchEntry::Create(&II, CI, OpMask)); + } + } +} void AsmMatcherInfo::BuildInfo() { // Build information about all of the AssemblerPredicates. @@ -985,17 +1144,17 @@ void AsmMatcherInfo::BuildInfo() { // Ignore predicates that are not intended for the assembler. if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) continue; - + if (Pred->getName().empty()) throw TGError(Pred->getLoc(), "Predicate has no name!"); - + unsigned FeatureNo = SubtargetFeatures.size(); SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); assert(FeatureNo < 32 && "Too many subtarget features!"); } StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); - + // Parse the instructions; we need to do this first so that we can gather the // singleton register classes. SmallPtrSet SingletonRegisters; @@ -1011,15 +1170,15 @@ void AsmMatcherInfo::BuildInfo() { // Ignore "codegen only" instructions. if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) continue; - + // Validate the operand list to ensure we can handle this instruction. for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; - + // Validate tied operands. if (OI.getTiedRegister() != -1) { - // If we have a tied operand that consists of multiple MCOperands, reject - // it. We reject aliases and ignore instructions for now. + // If we have a tied operand that consists of multiple MCOperands, + // reject it. We reject aliases and ignore instructions for now. if (OI.MINumOperands != 1) { // FIXME: Should reject these. The ARM backend hits this with $lane // in a bunch of instructions. It is unclear what the right answer is. @@ -1032,26 +1191,26 @@ void AsmMatcherInfo::BuildInfo() { } } } - + OwningPtr II(new MatchableInfo(CGI)); II->Initialize(*this, SingletonRegisters); - + // Ignore instructions which shouldn't be matched and diagnose invalid // instruction definitions with an error. if (!II->Validate(CommentDelimiter, true)) continue; - + // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. // // FIXME: This is a total hack. if (StringRef(II->TheDef->getName()).startswith("Int_") || StringRef(II->TheDef->getName()).endswith("_Int")) continue; - + Matchables.push_back(II.take()); } - + // Parse all of the InstAlias definitions and stick them in the list of // matchables. std::vector AllInstAliases = @@ -1059,13 +1218,20 @@ void AsmMatcherInfo::BuildInfo() { for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target); + // If the tblgen -match-prefix option is specified (for tblgen hackers), + // filter the set of instruction aliases we consider, based on the target + // instruction. + if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith( + MatchPrefix)) + continue; + OwningPtr II(new MatchableInfo(Alias)); - + II->Initialize(*this, SingletonRegisters); - + // Validate the alias definitions. II->Validate(CommentDelimiter, false); - + Matchables.push_back(II.take()); } @@ -1082,7 +1248,9 @@ void AsmMatcherInfo::BuildInfo() { MatchableInfo *II = *it; // Parse the tokens after the mnemonic. - for (unsigned i = 0, e = II->AsmOperands.size(); i != e; ++i) { + // Note: BuildInstructionOperandReference may insert new AsmOperands, so + // don't precompute the loop bound. + for (unsigned i = 0; i != II->AsmOperands.size(); ++i) { MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; StringRef Token = Op.Token; @@ -1100,26 +1268,31 @@ void AsmMatcherInfo::BuildInfo() { continue; } + if (Token.size() > 1 && isdigit(Token[1])) { + Op.Class = getTokenClass(Token); + continue; + } + // Otherwise this is an operand reference. StringRef OperandName; if (Token[1] == '{') OperandName = Token.substr(2, Token.size() - 3); else OperandName = Token.substr(1); - + if (II->DefRec.is()) - BuildInstructionOperandReference(II, OperandName, Op); + BuildInstructionOperandReference(II, OperandName, i); else BuildAliasOperandReference(II, OperandName, Op); } - + if (II->DefRec.is()) II->BuildInstructionResultOperands(); else II->BuildAliasResultOperands(); } - // Reorder classes so that classes preceed super classes. + // Reorder classes so that classes precede super classes. std::sort(Classes.begin(), Classes.end(), less_ptr()); } @@ -1128,18 +1301,40 @@ void AsmMatcherInfo::BuildInfo() { void AsmMatcherInfo:: BuildInstructionOperandReference(MatchableInfo *II, StringRef OperandName, - MatchableInfo::AsmOperand &Op) { + unsigned AsmOpIdx) { const CodeGenInstruction &CGI = *II->DefRec.get(); const CGIOperandList &Operands = CGI.Operands; - + MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; + // Map this token to an operand. unsigned Idx; if (!Operands.hasOperandNamed(OperandName, Idx)) throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + OperandName.str() + "'"); + // If the instruction operand has multiple suboperands, but the parser + // match class for the asm operand is still the default "ImmAsmOperand", + // then handle each suboperand separately. + if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) { + Record *Rec = Operands[Idx].Rec; + assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); + Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); + if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") { + // Insert remaining suboperands after AsmOpIdx in II->AsmOperands. + StringRef Token = Op->Token; // save this in case Op gets moved + for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) { + MatchableInfo::AsmOperand NewAsmOp(Token); + NewAsmOp.SubOpIdx = SI; + II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp); + } + // Replace Op with first suboperand. + Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved + Op->SubOpIdx = 0; + } + } + // Set up the operand class. - Op.Class = getOperandClass(Operands[Idx]); + Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx); // If the named operand is tied, canonicalize it to the untied operand. // For example, something like: @@ -1153,15 +1348,12 @@ BuildInstructionOperandReference(MatchableInfo *II, if (OITied != -1) { // The tied operand index is an MIOperand index, find the operand that // contains it. - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (Operands[i].MIOperandNo == unsigned(OITied)) { - OperandName = Operands[i].Name; - break; - } - } + std::pair Idx = Operands.getSubOperandNumber(OITied); + OperandName = Operands[Idx.first].Name; + Op->SubOpIdx = Idx.second; } - - Op.SrcOpName = OperandName; + + Op->SrcOpName = OperandName; } /// BuildAliasOperandReference - When parsing an operand reference out of the @@ -1171,14 +1363,17 @@ void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, StringRef OperandName, MatchableInfo::AsmOperand &Op) { const CodeGenInstAlias &CGA = *II->DefRec.get(); - + // Set up the operand class. for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) - if (CGA.ResultOperands[i].Name == OperandName) { + if (CGA.ResultOperands[i].isRecord() && + CGA.ResultOperands[i].getName() == OperandName) { // It's safe to go with the first one we find, because CodeGenInstAlias // validates that all operands with the same name have the same record. - unsigned ResultIdx =CGA.getResultInstOperandIndexForResultOperandIndex(i); - Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx]); + unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first; + Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second; + Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx], + Op.SubOpIdx); Op.SrcOpName = OperandName; return; } @@ -1189,7 +1384,7 @@ void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, void MatchableInfo::BuildInstructionResultOperands() { const CodeGenInstruction *ResultInst = getResultInst(); - + // Loop over all operands of the result instruction, determining how to // populate them. for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { @@ -1198,57 +1393,90 @@ void MatchableInfo::BuildInstructionResultOperands() { // If this is a tied operand, just copy from the previously handled operand. int TiedOp = OpInfo.getTiedRegister(); if (TiedOp != -1) { - ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); continue; } - - // Find out what operand from the asmparser that this MCInst operand comes - // from. - int SrcOperand = FindAsmOperandNamed(OpInfo.Name); - if (!OpInfo.Name.empty() && SrcOperand != -1) { - ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); + // Find out what operand from the asmparser this MCInst operand comes from. + int SrcOperand = FindAsmOperandNamed(OpInfo.Name); + if (OpInfo.Name.empty() || SrcOperand == -1) + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); + + // Check if the one AsmOperand populates the entire operand. + unsigned NumOperands = OpInfo.MINumOperands; + if (AsmOperands[SrcOperand].SubOpIdx == -1) { + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands)); continue; } - - throw TGError(TheDef->getLoc(), "Instruction '" + - TheDef->getName() + "' has operand '" + OpInfo.Name + - "' that doesn't appear in asm string!"); + + // Add a separate ResOperand for each suboperand. + for (unsigned AI = 0; AI < NumOperands; ++AI) { + assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI && + AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name && + "unexpected AsmOperands for suboperands"); + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1)); + } } } void MatchableInfo::BuildAliasResultOperands() { const CodeGenInstAlias &CGA = *DefRec.get(); const CodeGenInstruction *ResultInst = getResultInst(); - + // Loop over all operands of the result instruction, determining how to // populate them. unsigned AliasOpNo = 0; + unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; - + const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; + // If this is a tied operand, just copy from the previously handled operand. - int TiedOp = OpInfo.getTiedRegister(); + int TiedOp = OpInfo->getTiedRegister(); if (TiedOp != -1) { - ResOperands.push_back(ResOperand::getTiedOp(TiedOp, &OpInfo)); + ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); continue; } - - // Find out what operand from the asmparser that this MCInst operand comes - // from. - int SrcOperand = FindAsmOperandNamed(CGA.ResultOperands[AliasOpNo++].Name); - if (SrcOperand != -1) { - ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, &OpInfo)); - continue; + + // Handle all the suboperands for this operand. + const std::string &OpName = OpInfo->Name; + for ( ; AliasOpNo < LastOpNo && + CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) { + int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; + + // Find out what operand from the asmparser that this MCInst operand + // comes from. + switch (CGA.ResultOperands[AliasOpNo].Kind) { + default: assert(0 && "unexpected InstAlias operand kind"); + case CodeGenInstAlias::ResultOperand::K_Record: { + StringRef Name = CGA.ResultOperands[AliasOpNo].getName(); + int SrcOperand = FindAsmOperand(Name, SubIdx); + if (SrcOperand == -1) + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpName + + "' that doesn't appear in asm string!"); + unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1); + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, + NumOperands)); + break; + } + case CodeGenInstAlias::ResultOperand::K_Imm: { + int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm(); + ResOperands.push_back(ResOperand::getImmOp(ImmVal)); + break; + } + case CodeGenInstAlias::ResultOperand::K_Reg: { + Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister(); + ResOperands.push_back(ResOperand::getRegOp(Reg)); + break; + } + } } - - throw TGError(TheDef->getLoc(), "Instruction '" + - TheDef->getName() + "' has operand '" + OpInfo.Name + - "' that doesn't appear in asm string!"); } } -static void EmitConvertToMCInst(CodeGenTarget &Target, +static void EmitConvertToMCInst(CodeGenTarget &Target, StringRef ClassName, std::vector &Infos, raw_ostream &OS) { // Write the convert function to a separate stream, so we can drop it after @@ -1260,7 +1488,8 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, std::set GeneratedFns; // Start the unified conversion function. - CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, " + CvtOS << "bool " << Target.getName() << ClassName << "::\n"; + CvtOS << "ConvertToMCInst(unsigned Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const SmallVectorImpl &Operands) {\n"; @@ -1280,22 +1509,41 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, ie = Infos.end(); it != ie; ++it) { MatchableInfo &II = **it; + // Check if we have a custom match function. + std::string AsmMatchConverter = + II.getResultInst()->TheDef->getValueAsString("AsmMatchConverter"); + if (!AsmMatchConverter.empty()) { + std::string Signature = "ConvertCustom_" + AsmMatchConverter; + II.ConversionFnKind = Signature; + + // Check if we have already generated this signature. + if (!GeneratedFns.insert(Signature).second) + continue; + + // If not, emit it now. Add to the enum list. + OS << " " << Signature << ",\n"; + + CvtOS << " case " << Signature << ":\n"; + CvtOS << " return " << AsmMatchConverter + << "(Inst, Opcode, Operands);\n"; + continue; + } + // Build the conversion function signature. std::string Signature = "Convert"; std::string CaseBody; raw_string_ostream CaseOS(CaseBody); - + // Compute the convert enum and the case body. for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; // Generate code to populate each result operand. switch (OpInfo.Kind) { - default: assert(0 && "Unknown result operand kind"); case MatchableInfo::ResOperand::RenderAsmOperand: { // This comes from something we parsed. MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; - + // Registers are always converted the same, don't duplicate the // conversion function based on them. Signature += "__"; @@ -1303,28 +1551,44 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, Signature += "Reg"; else Signature += Op.Class->ClassName; - Signature += utostr(OpInfo.OpInfo->MINumOperands); + Signature += utostr(OpInfo.MINumOperands); Signature += "_" + itostr(OpInfo.AsmOperandNum); - + CaseOS << " ((" << TargetOperandClass << "*)Operands[" << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod - << "(Inst, " << OpInfo.OpInfo->MINumOperands << ");\n"; + << "(Inst, " << OpInfo.MINumOperands << ");\n"; break; } - + case MatchableInfo::ResOperand::TiedOperand: { // If this operand is tied to a previous one, just copy the MCInst // operand from the earlier one.We can only tie single MCOperand values. - //assert(OpInfo.OpInfo->MINumOperands == 1 && "Not a singular MCOperand"); + //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); unsigned TiedOp = OpInfo.TiedOperandNum; - assert(i > TiedOp && "Tied operand preceeds its target!"); + assert(i > TiedOp && "Tied operand precedes its target!"); CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; Signature += "__Tie" + utostr(TiedOp); break; } + case MatchableInfo::ResOperand::ImmOperand: { + int64_t Val = OpInfo.ImmVal; + CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"; + Signature += "__imm" + itostr(Val); + break; + } + case MatchableInfo::ResOperand::RegOperand: { + if (OpInfo.Register == 0) { + CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; + Signature += "__reg0"; + } else { + std::string N = getQualifiedName(OpInfo.Register); + CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n"; + Signature += "__reg" + OpInfo.Register->getName(); + } + } } } - + II.ConversionFnKind = Signature; // Check if we have already generated this signature. @@ -1336,12 +1600,13 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, CvtOS << " case " << Signature << ":\n"; CvtOS << CaseOS.str(); - CvtOS << " return;\n"; + CvtOS << " return true;\n"; } // Finish the convert function. CvtOS << " }\n"; + CvtOS << " return false;\n"; CvtOS << "}\n\n"; // Finish the enum, and drop the convert function after it. @@ -1383,32 +1648,35 @@ static void EmitMatchClassEnumeration(CodeGenTarget &Target, OS << "}\n\n"; } -/// EmitClassifyOperand - Emit the function to classify an operand. -static void EmitClassifyOperand(AsmMatcherInfo &Info, - raw_ostream &OS) { - OS << "static MatchClassKind ClassifyOperand(MCParsedAsmOperand *GOp) {\n" - << " " << Info.Target.getName() << "Operand &Operand = *(" +/// EmitValidateOperandClass - Emit the function to validate an operand class. +static void EmitValidateOperandClass(AsmMatcherInfo &Info, + raw_ostream &OS) { + OS << "static bool ValidateOperandClass(MCParsedAsmOperand *GOp, " + << "MatchClassKind Kind) {\n"; + OS << " " << Info.Target.getName() << "Operand &Operand = *(" << Info.Target.getName() << "Operand*)GOp;\n"; - // Classify tokens. + // Check for Token operands first. OS << " if (Operand.isToken())\n"; - OS << " return MatchTokenString(Operand.getToken());\n\n"; + OS << " return MatchTokenString(Operand.getToken()) == Kind;\n\n"; - // Classify registers. - // - // FIXME: Don't hardcode isReg, getReg. + // Check for register operands, including sub-classes. OS << " if (Operand.isReg()) {\n"; + OS << " MatchClassKind OpKind;\n"; OS << " switch (Operand.getReg()) {\n"; - OS << " default: return InvalidMatchClass;\n"; + OS << " default: OpKind = InvalidMatchClass; break;\n"; for (std::map::iterator it = Info.RegisterClasses.begin(), ie = Info.RegisterClasses.end(); it != ie; ++it) OS << " case " << Info.Target.getName() << "::" - << it->first->getName() << ": return " << it->second->Name << ";\n"; + << it->first->getName() << ": OpKind = " << it->second->Name + << "; break;\n"; OS << " }\n"; + OS << " return IsSubclass(OpKind, Kind);\n"; OS << " }\n\n"; - // Classify user defined operands. + // Check the user classes. We don't care what order since we're only + // actually matching against one of them. for (std::vector::iterator it = Info.Classes.begin(), ie = Info.Classes.end(); it != ie; ++it) { ClassInfo &CI = **it; @@ -1416,30 +1684,14 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, if (!CI.isUserClass()) continue; - OS << " // '" << CI.ClassName << "' class"; - if (!CI.SuperClasses.empty()) { - OS << ", subclass of "; - for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) { - if (i) OS << ", "; - OS << "'" << CI.SuperClasses[i]->ClassName << "'"; - assert(CI < *CI.SuperClasses[i] && "Invalid class relation!"); - } - } - OS << "\n"; - - OS << " if (Operand." << CI.PredicateMethod << "()) {\n"; - - // Validate subclass relationships. - if (!CI.SuperClasses.empty()) { - for (unsigned i = 0, e = CI.SuperClasses.size(); i != e; ++i) - OS << " assert(Operand." << CI.SuperClasses[i]->PredicateMethod - << "() && \"Invalid class relationship!\");\n"; - } - - OS << " return " << CI.Name << ";\n"; + OS << " // '" << CI.ClassName << "' class\n"; + OS << " if (Kind == " << CI.Name + << " && Operand." << CI.PredicateMethod << "()) {\n"; + OS << " return true;\n"; OS << " }\n\n"; } - OS << " return InvalidMatchClass;\n"; + + OS << " return false;\n"; OS << "}\n\n"; } @@ -1490,8 +1742,6 @@ static void EmitIsSubclass(CodeGenTarget &Target, OS << "}\n\n"; } - - /// EmitMatchTokenString - Emit the function to match a token string to the /// appropriate match class value. static void EmitMatchTokenString(CodeGenTarget &Target, @@ -1522,14 +1772,16 @@ static void EmitMatchRegisterName(CodeGenTarget &Target, Record *AsmParser, raw_ostream &OS) { // Construct the match list. std::vector Matches; - for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { - const CodeGenRegister &Reg = Target.getRegisters()[i]; - if (Reg.TheDef->getValueAsString("AsmName").empty()) + const std::vector &Regs = + Target.getRegBank().getRegisters(); + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + const CodeGenRegister *Reg = Regs[i]; + if (Reg->TheDef->getValueAsString("AsmName").empty()) continue; Matches.push_back(StringMatcher::StringPair( - Reg.TheDef->getValueAsString("AsmName"), - "return " + utostr(i + 1) + ";")); + Reg->TheDef->getValueAsString("AsmName"), + "return " + utostr(Reg->EnumValue) + ";")); } OS << "static unsigned MatchRegisterName(StringRef Name) {\n"; @@ -1587,18 +1839,18 @@ static std::string GetAliasRequiredFeatures(Record *R, unsigned NumFeatures = 0; for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); - + if (F == 0) throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + "' is not marked as an AssemblerPredicate!"); - + if (NumFeatures) Result += '|'; - + Result += F->getEnumName(); ++NumFeatures; } - + if (NumFeatures > 1) Result = '(' + Result + ')'; return Result; @@ -1607,17 +1859,21 @@ static std::string GetAliasRequiredFeatures(Record *R, /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions, /// emit a function for them and return true, otherwise return false. static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { + // Ignore aliases when match-prefix is set. + if (!MatchPrefix.empty()) + return false; + std::vector Aliases = - Records.getAllDerivedDefinitions("MnemonicAlias"); + Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); if (Aliases.empty()) return false; OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " "unsigned Features) {\n"; - + // Keep track of all the aliases from a mnemonic. Use an std::map so that the // iteration order of the map is stable. std::map > AliasesFromMnemonic; - + for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { Record *R = Aliases[i]; AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); @@ -1636,11 +1892,11 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { // emit it last. std::string MatchCode; int AliasWithNoPredicate = -1; - + for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { Record *R = ToVec[i]; std::string FeatureMask = GetAliasRequiredFeatures(R, Info); - + // If this unconditionally matches, remember it for later and diagnose // duplicates. if (FeatureMask.empty()) { @@ -1650,43 +1906,190 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { "two MnemonicAliases with the same 'from' mnemonic!"); throw TGError(R->getLoc(), "this is the other MnemonicAlias."); } - + AliasWithNoPredicate = i; continue; } - + if (R->getValueAsString("ToMnemonic") == I->first) + throw TGError(R->getLoc(), "MnemonicAlias to the same string"); + if (!MatchCode.empty()) MatchCode += "else "; MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; } - + if (AliasWithNoPredicate != -1) { Record *R = ToVec[AliasWithNoPredicate]; if (!MatchCode.empty()) MatchCode += "else\n "; MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; } - + MatchCode += "return;"; Cases.push_back(std::make_pair(I->first, MatchCode)); } - - + StringMatcher("Mnemonic", Cases, OS).Emit(); - OS << "}\n"; - + OS << "}\n\n"; + return true; } +static void EmitCustomOperandParsing(raw_ostream &OS, CodeGenTarget &Target, + const AsmMatcherInfo &Info, StringRef ClassName) { + // Emit the static custom operand parsing table; + OS << "namespace {\n"; + OS << " struct OperandMatchEntry {\n"; + OS << " const char *Mnemonic;\n"; + OS << " unsigned OperandMask;\n"; + OS << " MatchClassKind Class;\n"; + OS << " unsigned RequiredFeatures;\n"; + OS << " };\n\n"; + + OS << " // Predicate for searching for an opcode.\n"; + OS << " struct LessOpcodeOperand {\n"; + OS << " bool operator()(const OperandMatchEntry &LHS, StringRef RHS) {\n"; + OS << " return StringRef(LHS.Mnemonic) < RHS;\n"; + OS << " }\n"; + OS << " bool operator()(StringRef LHS, const OperandMatchEntry &RHS) {\n"; + OS << " return LHS < StringRef(RHS.Mnemonic);\n"; + OS << " }\n"; + OS << " bool operator()(const OperandMatchEntry &LHS,"; + OS << " const OperandMatchEntry &RHS) {\n"; + OS << " return StringRef(LHS.Mnemonic) < StringRef(RHS.Mnemonic);\n"; + OS << " }\n"; + OS << " };\n"; + + OS << "} // end anonymous namespace.\n\n"; + + OS << "static const OperandMatchEntry OperandMatchTable[" + << Info.OperandMatchInfo.size() << "] = {\n"; + + OS << " /* Mnemonic, Operand List Mask, Operand Class, Features */\n"; + for (std::vector::const_iterator it = + Info.OperandMatchInfo.begin(), ie = Info.OperandMatchInfo.end(); + it != ie; ++it) { + const OperandMatchEntry &OMI = *it; + const MatchableInfo &II = *OMI.MI; + + OS << " { \"" << II.Mnemonic << "\"" + << ", " << OMI.OperandMask; + + OS << " /* "; + bool printComma = false; + for (int i = 0, e = 31; i !=e; ++i) + if (OMI.OperandMask & (1 << i)) { + if (printComma) + OS << ", "; + OS << i; + printComma = true; + } + OS << " */"; + + OS << ", " << OMI.CI->Name + << ", "; + + // Write the required features mask. + if (!II.RequiredFeatures.empty()) { + for (unsigned i = 0, e = II.RequiredFeatures.size(); i != e; ++i) { + if (i) OS << "|"; + OS << II.RequiredFeatures[i]->getEnumName(); + } + } else + OS << "0"; + OS << " },\n"; + } + OS << "};\n\n"; + + // Emit the operand class switch to call the correct custom parser for + // the found operand class. + OS << Target.getName() << ClassName << "::OperandMatchResultTy " + << Target.getName() << ClassName << "::\n" + << "TryCustomParseOperand(SmallVectorImpl" + << " &Operands,\n unsigned MCK) {\n\n" + << " switch(MCK) {\n"; + + for (std::vector::const_iterator it = Info.Classes.begin(), + ie = Info.Classes.end(); it != ie; ++it) { + ClassInfo *CI = *it; + if (CI->ParserMethod.empty()) + continue; + OS << " case " << CI->Name << ":\n" + << " return " << CI->ParserMethod << "(Operands);\n"; + } + + OS << " default:\n"; + OS << " return MatchOperand_NoMatch;\n"; + OS << " }\n"; + OS << " return MatchOperand_NoMatch;\n"; + OS << "}\n\n"; + + // Emit the static custom operand parser. This code is very similar with + // the other matcher. Also use MatchResultTy here just in case we go for + // a better error handling. + OS << Target.getName() << ClassName << "::OperandMatchResultTy " + << Target.getName() << ClassName << "::\n" + << "MatchOperandParserImpl(SmallVectorImpl" + << " &Operands,\n StringRef Mnemonic) {\n"; + + // Emit code to get the available features. + OS << " // Get the current feature set.\n"; + OS << " unsigned AvailableFeatures = getAvailableFeatures();\n\n"; + + OS << " // Get the next operand index.\n"; + OS << " unsigned NextOpNum = Operands.size()-1;\n"; + + // Emit code to search the table. + OS << " // Search the table.\n"; + OS << " std::pair"; + OS << " MnemonicRange =\n"; + OS << " std::equal_range(OperandMatchTable, OperandMatchTable+" + << Info.OperandMatchInfo.size() << ", Mnemonic,\n" + << " LessOpcodeOperand());\n\n"; + + OS << " if (MnemonicRange.first == MnemonicRange.second)\n"; + OS << " return MatchOperand_NoMatch;\n\n"; + + OS << " for (const OperandMatchEntry *it = MnemonicRange.first,\n" + << " *ie = MnemonicRange.second; it != ie; ++it) {\n"; + + OS << " // equal_range guarantees that instruction mnemonic matches.\n"; + OS << " assert(Mnemonic == it->Mnemonic);\n\n"; + + // Emit check that the required features are available. + OS << " // check if the available features match\n"; + OS << " if ((AvailableFeatures & it->RequiredFeatures) " + << "!= it->RequiredFeatures) {\n"; + OS << " continue;\n"; + OS << " }\n\n"; + + // Emit check to ensure the operand number matches. + OS << " // check if the operand in question has a custom parser.\n"; + OS << " if (!(it->OperandMask & (1 << NextOpNum)))\n"; + OS << " continue;\n\n"; + + // Emit call to the custom parser method + OS << " // call custom parse method to handle the operand\n"; + OS << " OperandMatchResultTy Result = "; + OS << "TryCustomParseOperand(Operands, it->Class);\n"; + OS << " if (Result != MatchOperand_NoMatch)\n"; + OS << " return Result;\n"; + OS << " }\n\n"; + + OS << " // Okay, we had no match.\n"; + OS << " return MatchOperand_NoMatch;\n"; + OS << "}\n\n"; +} + void AsmMatcherEmitter::run(raw_ostream &OS) { - CodeGenTarget Target; + CodeGenTarget Target(Records); Record *AsmParser = Target.getAsmParser(); std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); // Compute the information on the instructions to match. - AsmMatcherInfo Info(AsmParser, Target); + AsmMatcherInfo Info(AsmParser, Target, Records); Info.BuildInfo(); // Sort the instruction table using the partial order on classes. We use @@ -1710,7 +2113,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { MatchableInfo &A = *Info.Matchables[i]; MatchableInfo &B = *Info.Matchables[j]; - if (A.CouldMatchAmiguouslyWith(B)) { + if (A.CouldMatchAmbiguouslyWith(B)) { errs() << "warning: ambiguous matchables:\n"; A.dump(); errs() << "\nis incomparable with:\n"; @@ -1725,6 +2128,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { << " ambiguous matchables!\n"; }); + // Compute the information on the custom operand parsing. + Info.BuildOperandMatchInfo(); + // Write the output. EmitSourceFileHeader("Assembly Matcher Source Fragment", OS); @@ -1732,21 +2138,42 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Information for the class declaration. OS << "\n#ifdef GET_ASSEMBLER_HEADER\n"; OS << "#undef GET_ASSEMBLER_HEADER\n"; - OS << " // This should be included into the middle of the declaration of \n"; + OS << " // This should be included into the middle of the declaration of\n"; OS << " // your subclasses implementation of TargetAsmParser.\n"; OS << " unsigned ComputeAvailableFeatures(const " << Target.getName() << "Subtarget *Subtarget) const;\n"; OS << " enum MatchResultTy {\n"; - OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; - OS << " Match_MissingFeature\n"; + OS << " Match_ConversionFail,\n"; + OS << " Match_InvalidOperand,\n"; + OS << " Match_MissingFeature,\n"; + OS << " Match_MnemonicFail,\n"; + OS << " Match_Success\n"; OS << " };\n"; - OS << " MatchResultTy MatchInstructionImpl(const " - << "SmallVectorImpl" - << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; - OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; - - + OS << " bool ConvertToMCInst(unsigned Kind, MCInst &Inst, " + << "unsigned Opcode,\n" + << " const SmallVectorImpl " + << "&Operands);\n"; + OS << " bool MnemonicIsValid(StringRef Mnemonic);\n"; + OS << " MatchResultTy MatchInstructionImpl(\n"; + OS << " const SmallVectorImpl &Operands,\n"; + OS << " MCInst &Inst, unsigned &ErrorInfo);\n"; + + if (Info.OperandMatchInfo.size()) { + OS << "\n enum OperandMatchResultTy {\n"; + OS << " MatchOperand_Success, // operand matched successfully\n"; + OS << " MatchOperand_NoMatch, // operand did not match\n"; + OS << " MatchOperand_ParseFail // operand matched but had errors\n"; + OS << " };\n"; + OS << " OperandMatchResultTy MatchOperandParserImpl(\n"; + OS << " SmallVectorImpl &Operands,\n"; + OS << " StringRef Mnemonic);\n"; + + OS << " OperandMatchResultTy TryCustomParseOperand(\n"; + OS << " SmallVectorImpl &Operands,\n"; + OS << " unsigned MCK);\n\n"; + } + OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; OS << "\n#ifdef GET_REGISTER_MATCHER\n"; OS << "#undef GET_REGISTER_MATCHER\n\n"; @@ -1765,9 +2192,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Generate the function that remaps for mnemonic aliases. bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); - + // Generate the unified function to convert operands into an MCInst. - EmitConvertToMCInst(Target, Info.Matchables, OS); + EmitConvertToMCInst(Target, ClassName, Info.Matchables, OS); // Emit the enumeration for classes which participate in matching. EmitMatchClassEnumeration(Target, Info.Classes, OS); @@ -1775,12 +2202,12 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Emit the routine to match token strings to their match class. EmitMatchTokenString(Target, Info.Classes, OS); - // Emit the routine to classify an operand. - EmitClassifyOperand(Info, OS); - // Emit the subclass predicate routine. EmitIsSubclass(Target, Info.Classes, OS); + // Emit the routine to validate an operand against a match class. + EmitValidateOperandClass(Info, OS); + // Emit the available features compute function. EmitComputeAvailableFeatures(Info, OS); @@ -1791,7 +2218,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { it != ie; ++it) MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); - // Emit the static match table; unused classes get initalized to 0 which is // guaranteed to be InvalidMatchClass. // @@ -1811,7 +2237,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " unsigned RequiredFeatures;\n"; OS << " };\n\n"; - OS << "// Predicate for searching for an opcode.\n"; + OS << " // Predicate for searching for an opcode.\n"; OS << " struct LessOpcode {\n"; OS << " bool operator()(const MatchEntry &LHS, StringRef RHS) {\n"; OS << " return StringRef(LHS.Mnemonic) < RHS;\n"; @@ -1834,7 +2260,6 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { it != ie; ++it) { MatchableInfo &II = **it; - OS << " { " << Target.getName() << "::" << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\"" << ", " << II.ConversionFnKind << ", { "; @@ -1860,6 +2285,16 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "};\n\n"; + // A method to determine if a mnemonic is in the list. + OS << "bool " << Target.getName() << ClassName << "::\n" + << "MnemonicIsValid(StringRef Mnemonic) {\n"; + OS << " // Search the table.\n"; + OS << " std::pair MnemonicRange =\n"; + OS << " std::equal_range(MatchTable, MatchTable+" + << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n"; + OS << " return MnemonicRange.first != MnemonicRange.second;\n"; + OS << "}\n\n"; + // Finally, build the match function. OS << Target.getName() << ClassName << "::MatchResultTy " << Target.getName() << ClassName << "::\n" @@ -1879,7 +2314,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; } - + // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; @@ -1887,26 +2322,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " return Match_InvalidOperand;\n"; OS << " }\n\n"; - OS << " // Compute the class list for this operand vector.\n"; - OS << " MatchClassKind Classes[" << MaxNumOperands << "];\n"; - OS << " for (unsigned i = 1, e = Operands.size(); i != e; ++i) {\n"; - OS << " Classes[i-1] = ClassifyOperand(Operands[i]);\n\n"; - - OS << " // Check for invalid operands before matching.\n"; - OS << " if (Classes[i-1] == InvalidMatchClass) {\n"; - OS << " ErrorInfo = i;\n"; - OS << " return Match_InvalidOperand;\n"; - OS << " }\n"; - OS << " }\n\n"; - - OS << " // Mark unused classes.\n"; - OS << " for (unsigned i = Operands.size()-1, e = " << MaxNumOperands << "; " - << "i != e; ++i)\n"; - OS << " Classes[i] = InvalidMatchClass;\n\n"; - OS << " // Some state to try to produce better error messages.\n"; OS << " bool HadMatchOtherThanFeatures = false;\n\n"; - OS << " // Set ErrorInfo to the operand that mismatches if it is \n"; + OS << " // Set ErrorInfo to the operand that mismatches if it is\n"; OS << " // wrong for all instances of the instruction.\n"; OS << " ErrorInfo = ~0U;\n"; @@ -1930,14 +2348,16 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Emit check that the subclasses match. OS << " bool OperandsValid = true;\n"; OS << " for (unsigned i = 0; i != " << MaxNumOperands << "; ++i) {\n"; - OS << " if (IsSubclass(Classes[i], it->Classes[i]))\n"; + OS << " if (i + 1 >= Operands.size()) {\n"; + OS << " OperandsValid = (it->Classes[i] == " <<"InvalidMatchClass);\n"; + OS << " break;\n"; + OS << " }\n"; + OS << " if (ValidateOperandClass(Operands[i+1], it->Classes[i]))\n"; OS << " continue;\n"; OS << " // If this operand is broken for all of the instances of this\n"; OS << " // mnemonic, keep track of it so we can report loc info.\n"; - OS << " if (it == MnemonicRange.first || ErrorInfo == i+1)\n"; + OS << " if (it == MnemonicRange.first || ErrorInfo <= i+1)\n"; OS << " ErrorInfo = i+1;\n"; - OS << " else\n"; - OS << " ErrorInfo = ~0U;"; OS << " // Otherwise, just reject this instance of the mnemonic.\n"; OS << " OperandsValid = false;\n"; OS << " break;\n"; @@ -1951,9 +2371,13 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " HadMatchOtherThanFeatures = true;\n"; OS << " continue;\n"; OS << " }\n"; - OS << "\n"; - OS << " ConvertToMCInst(it->ConvertFn, Inst, it->Opcode, Operands);\n"; + OS << " // We have selected a definite instruction, convert the parsed\n" + << " // operands into the appropriate MCInst.\n"; + OS << " if (!ConvertToMCInst(it->ConvertFn, Inst,\n" + << " it->Opcode, Operands))\n"; + OS << " return Match_ConversionFail;\n"; + OS << "\n"; // Call the post-processing function, if used. std::string InsnCleanupFn = @@ -1969,5 +2393,8 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " return Match_InvalidOperand;\n"; OS << "}\n\n"; + if (Info.OperandMatchInfo.size()) + EmitCustomOperandParsing(OS, Target, Info, ClassName); + OS << "#endif // GET_MATCHER_IMPLEMENTATION\n\n"; }