X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FAsmMatcherEmitter.cpp;h=a04428c4c60b9864d579aa8f83093e3dcc763302;hb=75f6e89ea9f8fe9cf8c8f9fe6a3322bd6566fdf1;hp=143286dafb66b35c75148fe1ae2dfcbca7e38210;hpb=c2d67bbf806486984d4c9551abfd66c7f766c45b;p=oota-llvm.git diff --git a/utils/TableGen/AsmMatcherEmitter.cpp b/utils/TableGen/AsmMatcherEmitter.cpp index 143286dafb6..a04428c4c60 100644 --- a/utils/TableGen/AsmMatcherEmitter.cpp +++ b/utils/TableGen/AsmMatcherEmitter.cpp @@ -63,9 +63,6 @@ // In addition, the subset relation amongst classes induces a partial order // on such tuples, which we use to resolve ambiguities. // -// FIXME: What do we do if a crazy case shows up where this is the wrong -// resolution? -// // 2. The input can now be treated as a tuple of classes (static tokens are // simple singleton sets). Each such tuple should generally map to a single // instruction (we currently ignore cases where this isn't true, whee!!!), @@ -78,13 +75,13 @@ #include "Record.h" #include "StringMatcher.h" #include "llvm/ADT/OwningPtr.h" +#include "llvm/ADT/PointerUnion.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/STLExtras.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" -#include #include #include using namespace llvm; @@ -93,85 +90,8 @@ static cl::opt MatchPrefix("match-prefix", cl::init(""), cl::desc("Only match instructions with the given prefix")); -/// TokenizeAsmString - Tokenize a simplified assembly string. -static void TokenizeAsmString(StringRef AsmString, - SmallVectorImpl &Tokens) { - unsigned Prev = 0; - bool InTok = true; - for (unsigned i = 0, e = AsmString.size(); i != e; ++i) { - switch (AsmString[i]) { - case '[': - case ']': - case '*': - case '!': - case ' ': - case '\t': - case ',': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - if (!isspace(AsmString[i]) && AsmString[i] != ',') - Tokens.push_back(AsmString.substr(i, 1)); - Prev = i + 1; - break; - - case '\\': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - ++i; - assert(i != AsmString.size() && "Invalid quoted character"); - Tokens.push_back(AsmString.substr(i, 1)); - Prev = i + 1; - break; - - case '$': { - // If this isn't "${", treat like a normal token. - if (i + 1 == AsmString.size() || AsmString[i + 1] != '{') { - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - Prev = i; - break; - } - - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - InTok = false; - } - - StringRef::iterator End = - std::find(AsmString.begin() + i, AsmString.end(), '}'); - assert(End != AsmString.end() && "Missing brace in operand reference!"); - size_t EndPos = End - AsmString.begin(); - Tokens.push_back(AsmString.slice(i, EndPos+1)); - Prev = EndPos + 1; - i = EndPos; - break; - } - - case '.': - if (InTok) { - Tokens.push_back(AsmString.slice(Prev, i)); - } - Prev = i; - InTok = true; - break; - - default: - InTok = true; - } - } - if (InTok && Prev != AsmString.size()) - Tokens.push_back(AsmString.substr(Prev)); -} - - namespace { - class AsmMatcherInfo; +class AsmMatcherInfo; struct SubtargetFeatureInfo; /// ClassInfo - Helper class for storing the information about a particular @@ -320,32 +240,131 @@ public: } }; -/// InstructionInfo - Helper class for storing the necessary information for an -/// instruction which is capable of being matched. -struct InstructionInfo { - struct Operand { +/// MatchableInfo - Helper class for storing the necessary information for an +/// instruction or alias which is capable of being matched. +struct MatchableInfo { + struct AsmOperand { + /// Token - This is the token that the operand came from. + StringRef Token; + /// The unique class instance this operand should match. ClassInfo *Class; - /// The original operand this corresponds to, if any. - const CGIOperandList::OperandInfo *OperandInfo; + /// The operand name this is, if anything. + StringRef SrcOpName; + + /// The suboperand index within SrcOpName, or -1 for the entire operand. + int SubOpIdx; + + explicit AsmOperand(StringRef T) : Token(T), Class(0), SubOpIdx(-1) {} }; - /// InstrName - The target name for this instruction. - std::string InstrName; + /// ResOperand - This represents a single operand in the result instruction + /// generated by the match. In cases (like addressing modes) where a single + /// assembler operand expands to multiple MCOperands, this represents the + /// single assembler operand, not the MCOperand. + struct ResOperand { + enum { + /// RenderAsmOperand - This represents an operand result that is + /// generated by calling the render method on the assembly operand. The + /// corresponding AsmOperand is specified by AsmOperandNum. + RenderAsmOperand, + + /// TiedOperand - This represents a result operand that is a duplicate of + /// a previous result operand. + TiedOperand, + + /// ImmOperand - This represents an immediate value that is dumped into + /// the operand. + ImmOperand, + + /// RegOperand - This represents a fixed register that is dumped in. + RegOperand + } Kind; + + union { + /// This is the operand # in the AsmOperands list that this should be + /// copied from. + unsigned AsmOperandNum; + + /// TiedOperandNum - This is the (earlier) result operand that should be + /// copied from. + unsigned TiedOperandNum; + + /// ImmVal - This is the immediate value added to the instruction. + int64_t ImmVal; + + /// Register - This is the register record. + Record *Register; + }; + + /// MINumOperands - The number of MCInst operands populated by this + /// operand. + unsigned MINumOperands; + + static ResOperand getRenderedOp(unsigned AsmOpNum, unsigned NumOperands) { + ResOperand X; + X.Kind = RenderAsmOperand; + X.AsmOperandNum = AsmOpNum; + X.MINumOperands = NumOperands; + return X; + } + static ResOperand getTiedOp(unsigned TiedOperandNum) { + ResOperand X; + X.Kind = TiedOperand; + X.TiedOperandNum = TiedOperandNum; + X.MINumOperands = 1; + return X; + } + + static ResOperand getImmOp(int64_t Val) { + ResOperand X; + X.Kind = ImmOperand; + X.ImmVal = Val; + X.MINumOperands = 1; + return X; + } + + static ResOperand getRegOp(Record *Reg) { + ResOperand X; + X.Kind = RegOperand; + X.Register = Reg; + X.MINumOperands = 1; + return X; + } + }; + + /// TheDef - This is the definition of the instruction or InstAlias that this + /// matchable came from. Record *const TheDef; - const CGIOperandList &OperandList; + + /// DefRec - This is the definition that it came from. + PointerUnion DefRec; + + const CodeGenInstruction *getResultInst() const { + if (DefRec.is()) + return DefRec.get(); + return DefRec.get()->ResultInst; + } + + /// ResOperands - This is the operand list that should be built for the result + /// MCInst. + std::vector ResOperands; /// AsmString - The assembly string for this instruction (with variants - /// removed). + /// removed), e.g. "movsx $src, $dst". std::string AsmString; - /// Tokens - The tokenized assembly pattern that this instruction matches. - SmallVector Tokens; + /// Mnemonic - This is the first token of the matched instruction, its + /// mnemonic. + StringRef Mnemonic; - /// Operands - The operands that this instruction matches. - SmallVector Operands; + /// AsmOperands - The textual operands that this instruction matches, + /// annotated with a class and where in the OperandList they were defined. + /// This directly corresponds to the tokenized AsmString after the mnemonic is + /// removed. + SmallVector AsmOperands; /// Predicates - The required subtarget features to match this instruction. SmallVector RequiredFeatures; @@ -354,56 +373,80 @@ struct InstructionInfo { /// ConvertToMCInst to convert parsed operands into an MCInst for this /// function. std::string ConversionFnKind; - - InstructionInfo(const CodeGenInstruction &CGI) - : TheDef(CGI.TheDef), OperandList(CGI.Operands), AsmString(CGI.AsmString) { + + MatchableInfo(const CodeGenInstruction &CGI) + : TheDef(CGI.TheDef), DefRec(&CGI), AsmString(CGI.AsmString) { } - InstructionInfo(const CodeGenInstAlias *Alias) - : TheDef(Alias->TheDef), OperandList(Alias->Operands), - AsmString(Alias->AsmString) { - + MatchableInfo(const CodeGenInstAlias *Alias) + : TheDef(Alias->TheDef), DefRec(Alias), AsmString(Alias->AsmString) { } - + void Initialize(const AsmMatcherInfo &Info, SmallPtrSet &SingletonRegisters); - - /// isAssemblerInstruction - Return true if this matchable is a valid thing to - /// match against. - bool isAssemblerInstruction(StringRef CommentDelimiter) const; - - /// getSingletonRegisterForToken - If the specified token is a singleton + + /// Validate - Return true if this matchable is a valid thing to match against + /// and perform a bunch of validity checking. + bool Validate(StringRef CommentDelimiter, bool Hack) const; + + /// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the Record for it, otherwise return null. - Record *getSingletonRegisterForToken(unsigned i, - const AsmMatcherInfo &Info) const; + Record *getSingletonRegisterForAsmOperand(unsigned i, + const AsmMatcherInfo &Info) const; + + /// FindAsmOperand - Find the AsmOperand with the specified name and + /// suboperand index. + int FindAsmOperand(StringRef N, int SubOpIdx) const { + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (N == AsmOperands[i].SrcOpName && + SubOpIdx == AsmOperands[i].SubOpIdx) + return i; + return -1; + } - /// operator< - Compare two instructions. - bool operator<(const InstructionInfo &RHS) const { + /// FindAsmOperandNamed - Find the first AsmOperand with the specified name. + /// This does not check the suboperand index. + int FindAsmOperandNamed(StringRef N) const { + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (N == AsmOperands[i].SrcOpName) + return i; + return -1; + } + + void BuildInstructionResultOperands(); + void BuildAliasResultOperands(); + + /// operator< - Compare two matchables. + bool operator<(const MatchableInfo &RHS) const { // The primary comparator is the instruction mnemonic. - if (Tokens[0] != RHS.Tokens[0]) - return Tokens[0] < RHS.Tokens[0]; + if (Mnemonic != RHS.Mnemonic) + return Mnemonic < RHS.Mnemonic; - if (Operands.size() != RHS.Operands.size()) - return Operands.size() < RHS.Operands.size(); + if (AsmOperands.size() != RHS.AsmOperands.size()) + return AsmOperands.size() < RHS.AsmOperands.size(); // Compare lexicographically by operand. The matcher validates that other - // orderings wouldn't be ambiguous using \see CouldMatchAmiguouslyWith(). - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (*Operands[i].Class < *RHS.Operands[i].Class) + // orderings wouldn't be ambiguous using \see CouldMatchAmbiguouslyWith(). + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) return true; - if (*RHS.Operands[i].Class < *Operands[i].Class) + if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) return false; } return false; } - /// CouldMatchAmiguouslyWith - Check whether this instruction could + /// CouldMatchAmbiguouslyWith - Check whether this matchable could /// ambiguously match the same set of operands as \arg RHS (without being a /// strictly superior match). - bool CouldMatchAmiguouslyWith(const InstructionInfo &RHS) { + bool CouldMatchAmbiguouslyWith(const MatchableInfo &RHS) { + // The primary comparator is the instruction mnemonic. + if (Mnemonic != RHS.Mnemonic) + return false; + // The number of operands is unambiguous. - if (Operands.size() != RHS.Operands.size()) + if (AsmOperands.size() != RHS.AsmOperands.size()) return false; // Otherwise, make sure the ordering of the two instructions is unambiguous @@ -412,21 +455,21 @@ struct InstructionInfo { // Tokens and operand kinds are unambiguous (assuming a correct target // specific parser). - for (unsigned i = 0, e = Operands.size(); i != e; ++i) - if (Operands[i].Class->Kind != RHS.Operands[i].Class->Kind || - Operands[i].Class->Kind == ClassInfo::Token) - if (*Operands[i].Class < *RHS.Operands[i].Class || - *RHS.Operands[i].Class < *Operands[i].Class) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) + if (AsmOperands[i].Class->Kind != RHS.AsmOperands[i].Class->Kind || + AsmOperands[i].Class->Kind == ClassInfo::Token) + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class || + *RHS.AsmOperands[i].Class < *AsmOperands[i].Class) return false; // Otherwise, this operand could commute if all operands are equivalent, or // there is a pair of operands that compare less than and a pair that // compare greater than. bool HasLT = false, HasGT = false; - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (*Operands[i].Class < *RHS.Operands[i].Class) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (*AsmOperands[i].Class < *RHS.AsmOperands[i].Class) HasLT = true; - if (*RHS.Operands[i].Class < *Operands[i].Class) + if (*RHS.AsmOperands[i].Class < *AsmOperands[i].Class) HasGT = true; } @@ -434,6 +477,9 @@ struct InstructionInfo { } void dump(); + +private: + void TokenizeAsmString(const AsmMatcherInfo &Info); }; /// SubtargetFeatureInfo - Helper class for storing information on a subtarget @@ -446,7 +492,7 @@ struct SubtargetFeatureInfo { unsigned Index; SubtargetFeatureInfo(Record *D, unsigned Idx) : TheDef(D), Index(Idx) {} - + /// \brief The name of the enumerated constant identifying this feature. std::string getEnumName() const { return "Feature_" + TheDef->getName(); @@ -455,6 +501,9 @@ struct SubtargetFeatureInfo { class AsmMatcherInfo { public: + /// Tracked Records + RecordKeeper &Records; + /// The tablegen AsmParser record. Record *AsmParser; @@ -467,15 +516,15 @@ public: /// The classes which are needed for matching. std::vector Classes; - /// The information on the instruction to match. - std::vector Instructions; + /// The information on the matchables to match. + std::vector Matchables; /// Map of Register records to their class information. std::map RegisterClasses; /// Map of Predicate records to their subtarget information. std::map SubtargetFeatures; - + private: /// Map of token to class information which has already been constructed. std::map TokenClasses; @@ -491,8 +540,8 @@ private: ClassInfo *getTokenClass(StringRef Token); /// getOperandClass - Lookup or create the class for the given operand. - ClassInfo *getOperandClass(StringRef Token, - const CGIOperandList::OperandInfo &OI); + ClassInfo *getOperandClass(const CGIOperandList::OperandInfo &OI, + int SubOpIdx = -1); /// BuildRegisterClasses - Build the ClassInfo* instances for register /// classes. @@ -502,12 +551,19 @@ private: /// operand classes. void BuildOperandClasses(); + void BuildInstructionOperandReference(MatchableInfo *II, StringRef OpName, + unsigned AsmOpIdx); + void BuildAliasOperandReference(MatchableInfo *II, StringRef OpName, + MatchableInfo::AsmOperand &Op); + public: - AsmMatcherInfo(Record *AsmParser, CodeGenTarget &Target); + AsmMatcherInfo(Record *AsmParser, + CodeGenTarget &Target, + RecordKeeper &Records); /// BuildInfo - Construct the various tables used during matching. void BuildInfo(); - + /// getSubtargetFeature - Lookup or create the subtarget feature info for the /// given operand. SubtargetFeatureInfo *getSubtargetFeature(Record *Def) const { @@ -516,86 +572,138 @@ public: SubtargetFeatures.find(Def); return I == SubtargetFeatures.end() ? 0 : I->second; } + + RecordKeeper &getRecords() const { + return Records; + } }; } -void InstructionInfo::dump() { - errs() << InstrName << " -- " << "flattened:\"" << AsmString << '\"' - << ", tokens:["; - for (unsigned i = 0, e = Tokens.size(); i != e; ++i) { - errs() << Tokens[i]; - if (i + 1 != e) - errs() << ", "; - } - errs() << "]\n"; +void MatchableInfo::dump() { + errs() << TheDef->getName() << " -- " << "flattened:\"" << AsmString <<"\"\n"; - for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - Operand &Op = Operands[i]; + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + AsmOperand &Op = AsmOperands[i]; errs() << " op[" << i << "] = " << Op.Class->ClassName << " - "; - if (Op.Class->Kind == ClassInfo::Token) { - errs() << '\"' << Tokens[i] << "\"\n"; - continue; - } - - if (!Op.OperandInfo) { - errs() << "(singleton register)\n"; - continue; - } - - const CGIOperandList::OperandInfo &OI = *Op.OperandInfo; - errs() << OI.Name << " " << OI.Rec->getName() - << " (" << OI.MIOperandNo << ", " << OI.MINumOperands << ")\n"; + errs() << '\"' << Op.Token << "\"\n"; } } -void InstructionInfo::Initialize(const AsmMatcherInfo &Info, - SmallPtrSet &SingletonRegisters) { - InstrName = TheDef->getName(); - +void MatchableInfo::Initialize(const AsmMatcherInfo &Info, + SmallPtrSet &SingletonRegisters) { // TODO: Eventually support asmparser for Variant != 0. AsmString = CodeGenInstruction::FlattenAsmStringVariants(AsmString, 0); - - TokenizeAsmString(AsmString, Tokens); - + + TokenizeAsmString(Info); + // Compute the require features. std::vector Predicates =TheDef->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) if (SubtargetFeatureInfo *Feature = Info.getSubtargetFeature(Predicates[i])) RequiredFeatures.push_back(Feature); - + // Collect singleton registers, if used. - for (unsigned i = 0, e = Tokens.size(); i != e; ++i) { - if (Record *Reg = getSingletonRegisterForToken(i, Info)) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + if (Record *Reg = getSingletonRegisterForAsmOperand(i, Info)) SingletonRegisters.insert(Reg); } } +/// TokenizeAsmString - Tokenize a simplified assembly string. +void MatchableInfo::TokenizeAsmString(const AsmMatcherInfo &Info) { + StringRef String = AsmString; + unsigned Prev = 0; + bool InTok = true; + for (unsigned i = 0, e = String.size(); i != e; ++i) { + switch (String[i]) { + case '[': + case ']': + case '*': + case '!': + case ' ': + case '\t': + case ',': + if (InTok) { + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + InTok = false; + } + if (!isspace(String[i]) && String[i] != ',') + AsmOperands.push_back(AsmOperand(String.substr(i, 1))); + Prev = i + 1; + break; -/// getRegisterRecord - Get the register record for \arg name, or 0. -static Record *getRegisterRecord(CodeGenTarget &Target, StringRef Name) { - for (unsigned i = 0, e = Target.getRegisters().size(); i != e; ++i) { - const CodeGenRegister &Reg = Target.getRegisters()[i]; - if (Name == Reg.TheDef->getValueAsString("AsmName")) - return Reg.TheDef; + case '\\': + if (InTok) { + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + InTok = false; + } + ++i; + assert(i != String.size() && "Invalid quoted character"); + AsmOperands.push_back(AsmOperand(String.substr(i, 1))); + Prev = i + 1; + break; + + case '$': { + if (InTok) { + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + InTok = false; + } + + // If this isn't "${", treat like a normal token. + if (i + 1 == String.size() || String[i + 1] != '{') { + Prev = i; + break; + } + + StringRef::iterator End = std::find(String.begin() + i, String.end(),'}'); + assert(End != String.end() && "Missing brace in operand reference!"); + size_t EndPos = End - String.begin(); + AsmOperands.push_back(AsmOperand(String.slice(i, EndPos+1))); + Prev = EndPos + 1; + i = EndPos; + break; + } + + case '.': + if (InTok) + AsmOperands.push_back(AsmOperand(String.slice(Prev, i))); + Prev = i; + InTok = true; + break; + + default: + InTok = true; + } } - - return 0; + if (InTok && Prev != String.size()) + AsmOperands.push_back(AsmOperand(String.substr(Prev))); + + // The first token of the instruction is the mnemonic, which must be a + // simple string, not a $foo variable or a singleton register. + assert(!AsmOperands.empty() && "Instruction has no tokens?"); + Mnemonic = AsmOperands[0].Token; + if (Mnemonic[0] == '$' || getSingletonRegisterForAsmOperand(0, Info)) + throw TGError(TheDef->getLoc(), + "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); + + // Remove the first operand, it is tracked in the mnemonic field. + AsmOperands.erase(AsmOperands.begin()); } -bool InstructionInfo::isAssemblerInstruction(StringRef CommentDelimiter) const { - // Reject instructions with no .s string. +bool MatchableInfo::Validate(StringRef CommentDelimiter, bool Hack) const { + // Reject matchables with no .s string. if (AsmString.empty()) throw TGError(TheDef->getLoc(), "instruction with empty asm string"); - - // Reject any instructions with a newline in them, they should be marked + + // Reject any matchables with a newline in them, they should be marked // isCodeGenOnly if they are pseudo instructions. if (AsmString.find('\n') != std::string::npos) throw TGError(TheDef->getLoc(), "multiline instruction is not valid for the asmparser, " "mark it isCodeGenOnly"); - + // Remove comments from the asm string. We know that the asmstring only // has one line. if (!CommentDelimiter.empty() && @@ -603,58 +711,66 @@ bool InstructionInfo::isAssemblerInstruction(StringRef CommentDelimiter) const { throw TGError(TheDef->getLoc(), "asmstring for instruction has comment character in it, " "mark it isCodeGenOnly"); - - // Reject instructions with attributes, these aren't something we can handle, - // the target should be refactored to use operands instead of modifiers. + + // Reject matchables with operand modifiers, these aren't something we can + // handle, the target should be refactored to use operands instead of + // modifiers. // // Also, check for instructions which reference the operand multiple times; // this implies a constraint we would not honor. std::set OperandNames; - for (unsigned i = 1, e = Tokens.size(); i < e; ++i) { - if (Tokens[i][0] == '$' && Tokens[i].find(':') != StringRef::npos) + for (unsigned i = 0, e = AsmOperands.size(); i != e; ++i) { + StringRef Tok = AsmOperands[i].Token; + if (Tok[0] == '$' && Tok.find(':') != StringRef::npos) throw TGError(TheDef->getLoc(), - "instruction with operand modifier '" + Tokens[i].str() + + "matchable with operand modifier '" + Tok.str() + "' not supported by asm matcher. Mark isCodeGenOnly!"); - - // FIXME: Should reject these. The ARM backend hits this with $lane in a - // bunch of instructions. It is unclear what the right answer is for this. - if (Tokens[i][0] == '$' && !OperandNames.insert(Tokens[i]).second) { + + // Verify that any operand is only mentioned once. + // We reject aliases and ignore instructions for now. + if (Tok[0] == '$' && !OperandNames.insert(Tok).second) { + if (!Hack) + throw TGError(TheDef->getLoc(), + "ERROR: matchable with tied operand '" + Tok.str() + + "' can never be matched!"); + // FIXME: Should reject these. The ARM backend hits this with $lane in a + // bunch of instructions. It is unclear what the right answer is. DEBUG({ - errs() << "warning: '" << InstrName << "': " - << "ignoring instruction with tied operand '" - << Tokens[i].str() << "'\n"; + errs() << "warning: '" << TheDef->getName() << "': " + << "ignoring instruction with tied operand '" + << Tok.str() << "'\n"; }); return false; } } - + return true; } - -/// getSingletonRegisterForToken - If the specified token is a singleton +/// getSingletonRegisterForAsmOperand - If the specified token is a singleton /// register, return the register name, otherwise return a null StringRef. -Record *InstructionInfo:: -getSingletonRegisterForToken(unsigned i, const AsmMatcherInfo &Info) const { - StringRef Tok = Tokens[i]; +Record *MatchableInfo:: +getSingletonRegisterForAsmOperand(unsigned i, const AsmMatcherInfo &Info) const{ + StringRef Tok = AsmOperands[i].Token; if (!Tok.startswith(Info.RegisterPrefix)) return 0; - + StringRef RegName = Tok.substr(Info.RegisterPrefix.size()); - if (Record *Rec = getRegisterRecord(Info.Target, RegName)) - return Rec; - + if (const CodeGenRegister *Reg = Info.Target.getRegisterByName(RegName)) + return Reg->TheDef; + // If there is no register prefix (i.e. "%" in "%eax"), then this may // be some random non-register token, just ignore it. if (Info.RegisterPrefix.empty()) return 0; - + + // Otherwise, we have something invalid prefixed with the register prefix, + // such as %foo. std::string Err = "unable to find register for '" + RegName.str() + "' (which matches register prefix)"; throw TGError(TheDef->getLoc(), Err); } - static std::string getEnumNameForToken(StringRef Str) { std::string Res; @@ -663,6 +779,8 @@ static std::string getEnumNameForToken(StringRef Str) { case '*': Res += "_STAR_"; break; case '%': Res += "_PCT_"; break; case ':': Res += "_COLON_"; break; + case '!': Res += "_EXCLAIM_"; break; + case '.': Res += "_DOT_"; break; default: if (isalnum(*it)) Res += *it; @@ -692,41 +810,38 @@ ClassInfo *AsmMatcherInfo::getTokenClass(StringRef Token) { } ClassInfo * -AsmMatcherInfo::getOperandClass(StringRef Token, - const CGIOperandList::OperandInfo &OI) { - if (OI.Rec->isSubClassOf("RegisterClass")) { - ClassInfo *CI = RegisterClassClasses[OI.Rec]; - - if (!CI) - throw TGError(OI.Rec->getLoc(), "register class has no class info!"); - - return CI; +AsmMatcherInfo::getOperandClass(const CGIOperandList::OperandInfo &OI, + int SubOpIdx) { + Record *Rec = OI.Rec; + if (SubOpIdx != -1) + Rec = dynamic_cast(OI.MIOperandInfo->getArg(SubOpIdx))->getDef(); + + if (Rec->isSubClassOf("RegisterClass")) { + if (ClassInfo *CI = RegisterClassClasses[Rec]) + return CI; + throw TGError(Rec->getLoc(), "register class has no class info!"); } - assert(OI.Rec->isSubClassOf("Operand") && "Unexpected operand!"); - Record *MatchClass = OI.Rec->getValueAsDef("ParserMatchClass"); - ClassInfo *CI = AsmOperandClasses[MatchClass]; - - if (!CI) - throw TGError(OI.Rec->getLoc(), "operand has no match class!"); + assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); + Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); + if (ClassInfo *CI = AsmOperandClasses[MatchClass]) + return CI; - return CI; + throw TGError(Rec->getLoc(), "operand has no match class!"); } void AsmMatcherInfo:: BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { - std::vector RegisterClasses; - std::vector Registers; - - RegisterClasses = Target.getRegisterClasses(); - Registers = Target.getRegisters(); + const std::vector &Registers = Target.getRegisters(); + const std::vector &RegClassList = + Target.getRegisterClasses(); // The register sets used for matching. std::set< std::set > RegisterSets; // Gather the defined sets. - for (std::vector::iterator it = RegisterClasses.begin(), - ie = RegisterClasses.end(); it != ie; ++it) + for (std::vector::const_iterator it = + RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) RegisterSets.insert(std::set(it->Elements.begin(), it->Elements.end())); @@ -741,9 +856,9 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { // a unique register set class), and build the mapping of registers to the set // they should classify to. std::map > RegisterMap; - for (std::vector::iterator it = Registers.begin(), + for (std::vector::const_iterator it = Registers.begin(), ie = Registers.end(); it != ie; ++it) { - CodeGenRegister &CGR = *it; + const CodeGenRegister &CGR = *it; // Compute the intersection of all sets containing this register. std::set ContainingSet; @@ -754,14 +869,14 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { if (ContainingSet.empty()) { ContainingSet = *it; - } else { - std::set Tmp; - std::swap(Tmp, ContainingSet); - std::insert_iterator< std::set > II(ContainingSet, - ContainingSet.begin()); - std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), - II); + continue; } + + std::set Tmp; + std::swap(Tmp, ContainingSet); + std::insert_iterator< std::set > II(ContainingSet, + ContainingSet.begin()); + std::set_intersection(Tmp.begin(), Tmp.end(), it->begin(), it->end(), II); } if (!ContainingSet.empty()) { @@ -800,8 +915,8 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { } // Name the register classes which correspond to a user defined RegisterClass. - for (std::vector::iterator it = RegisterClasses.begin(), - ie = RegisterClasses.end(); it != ie; ++it) { + for (std::vector::const_iterator + it = RegClassList.begin(), ie = RegClassList.end(); it != ie; ++it) { ClassInfo *CI = RegisterSetClasses[std::set(it->Elements.begin(), it->Elements.end())]; if (CI->ValueName.empty()) { @@ -817,13 +932,13 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { // Populate the map for individual registers. for (std::map >::iterator it = RegisterMap.begin(), ie = RegisterMap.end(); it != ie; ++it) - this->RegisterClasses[it->first] = RegisterSetClasses[it->second]; + RegisterClasses[it->first] = RegisterSetClasses[it->second]; // Name the register classes which correspond to singleton registers. for (SmallPtrSet::iterator it = SingletonRegisters.begin(), ie = SingletonRegisters.end(); it != ie; ++it) { Record *Rec = *it; - ClassInfo *CI = this->RegisterClasses[Rec]; + ClassInfo *CI = RegisterClasses[Rec]; assert(CI && "Missing singleton register class info!"); if (CI->ValueName.empty()) { @@ -836,8 +951,8 @@ BuildRegisterClasses(SmallPtrSet &SingletonRegisters) { } void AsmMatcherInfo::BuildOperandClasses() { - std::vector AsmOperands; - AsmOperands = Records.getAllDerivedDefinitions("AsmOperandClass"); + std::vector AsmOperands = + Records.getAllDerivedDefinitions("AsmOperandClass"); // Pre-populate AsmOperandClasses map. for (std::vector::iterator it = AsmOperands.begin(), @@ -893,12 +1008,13 @@ void AsmMatcherInfo::BuildOperandClasses() { } } -AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, CodeGenTarget &target) - : AsmParser(asmParser), Target(target), +AsmMatcherInfo::AsmMatcherInfo(Record *asmParser, + CodeGenTarget &target, + RecordKeeper &records) + : Records(records), AsmParser(asmParser), Target(target), RegisterPrefix(AsmParser->getValueAsString("RegisterPrefix")) { } - void AsmMatcherInfo::BuildInfo() { // Build information about all of the AssemblerPredicates. std::vector AllPredicates = @@ -908,17 +1024,17 @@ void AsmMatcherInfo::BuildInfo() { // Ignore predicates that are not intended for the assembler. if (!Pred->getValueAsBit("AssemblerMatcherPredicate")) continue; - + if (Pred->getName().empty()) throw TGError(Pred->getLoc(), "Predicate has no name!"); - + unsigned FeatureNo = SubtargetFeatures.size(); SubtargetFeatures[Pred] = new SubtargetFeatureInfo(Pred, FeatureNo); assert(FeatureNo < 32 && "Too many subtarget features!"); } StringRef CommentDelimiter = AsmParser->getValueAsString("CommentDelimiter"); - + // Parse the instructions; we need to do this first so that we can gather the // singleton register classes. SmallPtrSet SingletonRegisters; @@ -934,38 +1050,69 @@ void AsmMatcherInfo::BuildInfo() { // Ignore "codegen only" instructions. if (CGI.TheDef->getValueAsBit("isCodeGenOnly")) continue; - - OwningPtr II(new InstructionInfo(CGI)); + + // Validate the operand list to ensure we can handle this instruction. + for (unsigned i = 0, e = CGI.Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OI = CGI.Operands[i]; + + // Validate tied operands. + if (OI.getTiedRegister() != -1) { + // If we have a tied operand that consists of multiple MCOperands, + // reject it. We reject aliases and ignore instructions for now. + if (OI.MINumOperands != 1) { + // FIXME: Should reject these. The ARM backend hits this with $lane + // in a bunch of instructions. It is unclear what the right answer is. + DEBUG({ + errs() << "warning: '" << CGI.TheDef->getName() << "': " + << "ignoring instruction with multi-operand tied operand '" + << OI.Name << "'\n"; + }); + continue; + } + } + } + + OwningPtr II(new MatchableInfo(CGI)); II->Initialize(*this, SingletonRegisters); - + // Ignore instructions which shouldn't be matched and diagnose invalid // instruction definitions with an error. - if (!II->isAssemblerInstruction(CommentDelimiter)) + if (!II->Validate(CommentDelimiter, true)) continue; - + // Ignore "Int_*" and "*_Int" instructions, which are internal aliases. // // FIXME: This is a total hack. - if (StringRef(II->InstrName).startswith("Int_") || - StringRef(II->InstrName).endswith("_Int")) + if (StringRef(II->TheDef->getName()).startswith("Int_") || + StringRef(II->TheDef->getName()).endswith("_Int")) continue; - - Instructions.push_back(II.take()); + + Matchables.push_back(II.take()); } - + // Parse all of the InstAlias definitions and stick them in the list of // matchables. std::vector AllInstAliases = Records.getAllDerivedDefinitions("InstAlias"); for (unsigned i = 0, e = AllInstAliases.size(); i != e; ++i) { - CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i]); + CodeGenInstAlias *Alias = new CodeGenInstAlias(AllInstAliases[i], Target); + + // If the tblgen -match-prefix option is specified (for tblgen hackers), + // filter the set of instruction aliases we consider, based on the target + // instruction. + if (!StringRef(Alias->ResultInst->TheDef->getName()).startswith( + MatchPrefix)) + continue; + + OwningPtr II(new MatchableInfo(Alias)); - OwningPtr II(new InstructionInfo(Alias)); - II->Initialize(*this, SingletonRegisters); - - //Instructions.push_back(II.take()); + + // Validate the alias definitions. + II->Validate(CommentDelimiter, false); + + Matchables.push_back(II.take()); } // Build info for the register classes. @@ -974,40 +1121,35 @@ void AsmMatcherInfo::BuildInfo() { // Build info for the user defined assembly operand classes. BuildOperandClasses(); - // Build the instruction information. - for (std::vector::iterator it = Instructions.begin(), - ie = Instructions.end(); it != ie; ++it) { - InstructionInfo *II = *it; - - // The first token of the instruction is the mnemonic, which must be a - // simple string, not a $foo variable or a singleton register. - assert(!II->Tokens.empty() && "Instruction has no tokens?"); - StringRef Mnemonic = II->Tokens[0]; - if (Mnemonic[0] == '$' || II->getSingletonRegisterForToken(0, *this)) - throw TGError(II->TheDef->getLoc(), - "Invalid instruction mnemonic '" + Mnemonic.str() + "'!"); + // Build the information about matchables, now that we have fully formed + // classes. + for (std::vector::iterator it = Matchables.begin(), + ie = Matchables.end(); it != ie; ++it) { + MatchableInfo *II = *it; // Parse the tokens after the mnemonic. - for (unsigned i = 1, e = II->Tokens.size(); i != e; ++i) { - StringRef Token = II->Tokens[i]; + // Note: BuildInstructionOperandReference may insert new AsmOperands, so + // don't precompute the loop bound. + for (unsigned i = 0; i != II->AsmOperands.size(); ++i) { + MatchableInfo::AsmOperand &Op = II->AsmOperands[i]; + StringRef Token = Op.Token; // Check for singleton registers. - if (Record *RegRecord = II->getSingletonRegisterForToken(i, *this)) { - InstructionInfo::Operand Op; + if (Record *RegRecord = II->getSingletonRegisterForAsmOperand(i, *this)) { Op.Class = RegisterClasses[RegRecord]; - Op.OperandInfo = 0; assert(Op.Class && Op.Class->Registers.size() == 1 && "Unexpected class for singleton register"); - II->Operands.push_back(Op); continue; } // Check for simple tokens. if (Token[0] != '$') { - InstructionInfo::Operand Op; Op.Class = getTokenClass(Token); - Op.OperandInfo = 0; - II->Operands.push_back(Op); + continue; + } + + if (Token.size() > 1 && isdigit(Token[1])) { + Op.Class = getTokenClass(Token); continue; } @@ -1018,55 +1160,204 @@ void AsmMatcherInfo::BuildInfo() { else OperandName = Token.substr(1); - // Map this token to an operand. FIXME: Move elsewhere. - unsigned Idx; - if (!II->OperandList.hasOperandNamed(OperandName, Idx)) - throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + - OperandName.str() + "'"); - - // FIXME: This is annoying, the named operand may be tied (e.g., - // XCHG8rm). What we want is the untied operand, which we now have to - // grovel for. Only worry about this for single entry operands, we have to - // clean this up anyway. - const CGIOperandList::OperandInfo *OI = &II->OperandList[Idx]; - if (OI->Constraints[0].isTied()) { - unsigned TiedOp = OI->Constraints[0].getTiedOperand(); - - // The tied operand index is an MIOperand index, find the operand that - // contains it. - for (unsigned i = 0, e = II->OperandList.size(); i != e; ++i) { - if (II->OperandList[i].MIOperandNo == TiedOp) { - OI = &II->OperandList[i]; - break; - } - } - - assert(OI && "Unable to find tied operand target!"); - } - - InstructionInfo::Operand Op; - Op.Class = getOperandClass(Token, *OI); - Op.OperandInfo = OI; - II->Operands.push_back(Op); + if (II->DefRec.is()) + BuildInstructionOperandReference(II, OperandName, i); + else + BuildAliasOperandReference(II, OperandName, Op); } + + if (II->DefRec.is()) + II->BuildInstructionResultOperands(); + else + II->BuildAliasResultOperands(); } // Reorder classes so that classes preceed super classes. std::sort(Classes.begin(), Classes.end(), less_ptr()); } -static std::pair * -GetTiedOperandAtIndex(SmallVectorImpl > &List, - unsigned Index) { - for (unsigned i = 0, e = List.size(); i != e; ++i) - if (Index == List[i].first) - return &List[i]; +/// BuildInstructionOperandReference - The specified operand is a reference to a +/// named operand such as $src. Resolve the Class and OperandInfo pointers. +void AsmMatcherInfo:: +BuildInstructionOperandReference(MatchableInfo *II, + StringRef OperandName, + unsigned AsmOpIdx) { + const CodeGenInstruction &CGI = *II->DefRec.get(); + const CGIOperandList &Operands = CGI.Operands; + MatchableInfo::AsmOperand *Op = &II->AsmOperands[AsmOpIdx]; + + // Map this token to an operand. + unsigned Idx; + if (!Operands.hasOperandNamed(OperandName, Idx)) + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); + + // If the instruction operand has multiple suboperands, but the parser + // match class for the asm operand is still the default "ImmAsmOperand", + // then handle each suboperand separately. + if (Op->SubOpIdx == -1 && Operands[Idx].MINumOperands > 1) { + Record *Rec = Operands[Idx].Rec; + assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); + Record *MatchClass = Rec->getValueAsDef("ParserMatchClass"); + if (MatchClass && MatchClass->getValueAsString("Name") == "Imm") { + // Insert remaining suboperands after AsmOpIdx in II->AsmOperands. + StringRef Token = Op->Token; // save this in case Op gets moved + for (unsigned SI = 1, SE = Operands[Idx].MINumOperands; SI != SE; ++SI) { + MatchableInfo::AsmOperand NewAsmOp(Token); + NewAsmOp.SubOpIdx = SI; + II->AsmOperands.insert(II->AsmOperands.begin()+AsmOpIdx+SI, NewAsmOp); + } + // Replace Op with first suboperand. + Op = &II->AsmOperands[AsmOpIdx]; // update the pointer in case it moved + Op->SubOpIdx = 0; + } + } + + // Set up the operand class. + Op->Class = getOperandClass(Operands[Idx], Op->SubOpIdx); + + // If the named operand is tied, canonicalize it to the untied operand. + // For example, something like: + // (outs GPR:$dst), (ins GPR:$src) + // with an asmstring of + // "inc $src" + // we want to canonicalize to: + // "inc $dst" + // so that we know how to provide the $dst operand when filling in the result. + int OITied = Operands[Idx].getTiedRegister(); + if (OITied != -1) { + // The tied operand index is an MIOperand index, find the operand that + // contains it. + std::pair Idx = Operands.getSubOperandNumber(OITied); + OperandName = Operands[Idx.first].Name; + Op->SubOpIdx = Idx.second; + } + + Op->SrcOpName = OperandName; +} + +/// BuildAliasOperandReference - When parsing an operand reference out of the +/// matching string (e.g. "movsx $src, $dst"), determine what the class of the +/// operand reference is by looking it up in the result pattern definition. +void AsmMatcherInfo::BuildAliasOperandReference(MatchableInfo *II, + StringRef OperandName, + MatchableInfo::AsmOperand &Op) { + const CodeGenInstAlias &CGA = *II->DefRec.get(); + + // Set up the operand class. + for (unsigned i = 0, e = CGA.ResultOperands.size(); i != e; ++i) + if (CGA.ResultOperands[i].isRecord() && + CGA.ResultOperands[i].getName() == OperandName) { + // It's safe to go with the first one we find, because CodeGenInstAlias + // validates that all operands with the same name have the same record. + unsigned ResultIdx = CGA.ResultInstOperandIndex[i].first; + Op.SubOpIdx = CGA.ResultInstOperandIndex[i].second; + Op.Class = getOperandClass(CGA.ResultInst->Operands[ResultIdx], + Op.SubOpIdx); + Op.SrcOpName = OperandName; + return; + } - return 0; + throw TGError(II->TheDef->getLoc(), "error: unable to find operand: '" + + OperandName.str() + "'"); +} + +void MatchableInfo::BuildInstructionResultOperands() { + const CodeGenInstruction *ResultInst = getResultInst(); + + // Loop over all operands of the result instruction, determining how to + // populate them. + for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo &OpInfo = ResultInst->Operands[i]; + + // If this is a tied operand, just copy from the previously handled operand. + int TiedOp = OpInfo.getTiedRegister(); + if (TiedOp != -1) { + ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); + continue; + } + + // Find out what operand from the asmparser this MCInst operand comes from. + int SrcOperand = FindAsmOperandNamed(OpInfo.Name); + if (OpInfo.Name.empty() || SrcOperand == -1) + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpInfo.Name + + "' that doesn't appear in asm string!"); + + // Check if the one AsmOperand populates the entire operand. + unsigned NumOperands = OpInfo.MINumOperands; + if (AsmOperands[SrcOperand].SubOpIdx == -1) { + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, NumOperands)); + continue; + } + + // Add a separate ResOperand for each suboperand. + for (unsigned AI = 0; AI < NumOperands; ++AI) { + assert(AsmOperands[SrcOperand+AI].SubOpIdx == (int)AI && + AsmOperands[SrcOperand+AI].SrcOpName == OpInfo.Name && + "unexpected AsmOperands for suboperands"); + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand + AI, 1)); + } + } +} + +void MatchableInfo::BuildAliasResultOperands() { + const CodeGenInstAlias &CGA = *DefRec.get(); + const CodeGenInstruction *ResultInst = getResultInst(); + + // Loop over all operands of the result instruction, determining how to + // populate them. + unsigned AliasOpNo = 0; + unsigned LastOpNo = CGA.ResultInstOperandIndex.size(); + for (unsigned i = 0, e = ResultInst->Operands.size(); i != e; ++i) { + const CGIOperandList::OperandInfo *OpInfo = &ResultInst->Operands[i]; + + // If this is a tied operand, just copy from the previously handled operand. + int TiedOp = OpInfo->getTiedRegister(); + if (TiedOp != -1) { + ResOperands.push_back(ResOperand::getTiedOp(TiedOp)); + continue; + } + + // Handle all the suboperands for this operand. + const std::string &OpName = OpInfo->Name; + for ( ; AliasOpNo < LastOpNo && + CGA.ResultInstOperandIndex[AliasOpNo].first == i; ++AliasOpNo) { + int SubIdx = CGA.ResultInstOperandIndex[AliasOpNo].second; + + // Find out what operand from the asmparser that this MCInst operand + // comes from. + switch (CGA.ResultOperands[AliasOpNo].Kind) { + default: assert(0 && "unexpected InstAlias operand kind"); + case CodeGenInstAlias::ResultOperand::K_Record: { + StringRef Name = CGA.ResultOperands[AliasOpNo].getName(); + int SrcOperand = FindAsmOperand(Name, SubIdx); + if (SrcOperand == -1) + throw TGError(TheDef->getLoc(), "Instruction '" + + TheDef->getName() + "' has operand '" + OpName + + "' that doesn't appear in asm string!"); + unsigned NumOperands = (SubIdx == -1 ? OpInfo->MINumOperands : 1); + ResOperands.push_back(ResOperand::getRenderedOp(SrcOperand, + NumOperands)); + break; + } + case CodeGenInstAlias::ResultOperand::K_Imm: { + int64_t ImmVal = CGA.ResultOperands[AliasOpNo].getImm(); + ResOperands.push_back(ResOperand::getImmOp(ImmVal)); + break; + } + case CodeGenInstAlias::ResultOperand::K_Reg: { + Record *Reg = CGA.ResultOperands[AliasOpNo].getRegister(); + ResOperands.push_back(ResOperand::getRegOp(Reg)); + break; + } + } + } + } } static void EmitConvertToMCInst(CodeGenTarget &Target, - std::vector &Infos, + std::vector &Infos, raw_ostream &OS) { // Write the convert function to a separate stream, so we can drop it after // the enum. @@ -1077,7 +1368,6 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, std::set GeneratedFns; // Start the unified conversion function. - CvtOS << "static void ConvertToMCInst(ConversionKind Kind, MCInst &Inst, " << "unsigned Opcode,\n" << " const SmallVectorImpl::const_iterator it = Infos.begin(), + for (std::vector::const_iterator it = Infos.begin(), ie = Infos.end(); it != ie; ++it) { - InstructionInfo &II = **it; - - // Order the (class) operands by the order to convert them into an MCInst. - SmallVector, 4> MIOperandList; - for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[i]; - if (Op.OperandInfo) - MIOperandList.push_back(std::make_pair(Op.OperandInfo->MIOperandNo, i)); - } - - // Find any tied operands. - SmallVector, 4> TiedOperands; - for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OpInfo = II.OperandList[i]; - for (unsigned j = 0, e = OpInfo.Constraints.size(); j != e; ++j) { - const CGIOperandList::ConstraintInfo &CI = OpInfo.Constraints[j]; - if (CI.isTied()) - TiedOperands.push_back(std::make_pair(OpInfo.MIOperandNo + j, - CI.getTiedOperand())); - } - } - - std::sort(MIOperandList.begin(), MIOperandList.end()); - - // Compute the total number of operands. - unsigned NumMIOperands = 0; - for (unsigned i = 0, e = II.OperandList.size(); i != e; ++i) { - const CGIOperandList::OperandInfo &OI = II.OperandList[i]; - NumMIOperands = std::max(NumMIOperands, - OI.MIOperandNo + OI.MINumOperands); - } + MatchableInfo &II = **it; // Build the conversion function signature. std::string Signature = "Convert"; - unsigned CurIndex = 0; - for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second]; - assert(CurIndex <= Op.OperandInfo->MIOperandNo && - "Duplicate match for instruction operand!"); - - // Skip operands which weren't matched by anything, this occurs when the - // .td file encodes "implicit" operands as explicit ones. - // - // FIXME: This should be removed from the MCInst structure. - for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - if (!Tie) - Signature += "__Imp"; + std::string CaseBody; + raw_string_ostream CaseOS(CaseBody); + + // Compute the convert enum and the case body. + for (unsigned i = 0, e = II.ResOperands.size(); i != e; ++i) { + const MatchableInfo::ResOperand &OpInfo = II.ResOperands[i]; + + // Generate code to populate each result operand. + switch (OpInfo.Kind) { + case MatchableInfo::ResOperand::RenderAsmOperand: { + // This comes from something we parsed. + MatchableInfo::AsmOperand &Op = II.AsmOperands[OpInfo.AsmOperandNum]; + + // Registers are always converted the same, don't duplicate the + // conversion function based on them. + Signature += "__"; + if (Op.Class->isRegisterClass()) + Signature += "Reg"; else - Signature += "__Tie" + utostr(Tie->second); - } - - Signature += "__"; - - // Registers are always converted the same, don't duplicate the conversion - // function based on them. - // - // FIXME: We could generalize this based on the render method, if it - // mattered. - if (Op.Class->isRegisterClass()) - Signature += "Reg"; - else - Signature += Op.Class->ClassName; - Signature += utostr(Op.OperandInfo->MINumOperands); - Signature += "_" + utostr(MIOperandList[i].second); + Signature += Op.Class->ClassName; + Signature += utostr(OpInfo.MINumOperands); + Signature += "_" + itostr(OpInfo.AsmOperandNum); - CurIndex += Op.OperandInfo->MINumOperands; - } + CaseOS << " ((" << TargetOperandClass << "*)Operands[" + << (OpInfo.AsmOperandNum+1) << "])->" << Op.Class->RenderMethod + << "(Inst, " << OpInfo.MINumOperands << ");\n"; + break; + } - // Add any trailing implicit operands. - for (; CurIndex != NumMIOperands; ++CurIndex) { - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - if (!Tie) - Signature += "__Imp"; - else - Signature += "__Tie" + utostr(Tie->second); + case MatchableInfo::ResOperand::TiedOperand: { + // If this operand is tied to a previous one, just copy the MCInst + // operand from the earlier one.We can only tie single MCOperand values. + //assert(OpInfo.MINumOperands == 1 && "Not a singular MCOperand"); + unsigned TiedOp = OpInfo.TiedOperandNum; + assert(i > TiedOp && "Tied operand preceeds its target!"); + CaseOS << " Inst.addOperand(Inst.getOperand(" << TiedOp << "));\n"; + Signature += "__Tie" + utostr(TiedOp); + break; + } + case MatchableInfo::ResOperand::ImmOperand: { + int64_t Val = OpInfo.ImmVal; + CaseOS << " Inst.addOperand(MCOperand::CreateImm(" << Val << "));\n"; + Signature += "__imm" + itostr(Val); + break; + } + case MatchableInfo::ResOperand::RegOperand: { + if (OpInfo.Register == 0) { + CaseOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; + Signature += "__reg0"; + } else { + std::string N = getQualifiedName(OpInfo.Register); + CaseOS << " Inst.addOperand(MCOperand::CreateReg(" << N << "));\n"; + Signature += "__reg" + OpInfo.Register->getName(); + } + } + } } II.ConversionFnKind = Signature; @@ -1182,59 +1454,11 @@ static void EmitConvertToMCInst(CodeGenTarget &Target, if (!GeneratedFns.insert(Signature).second) continue; - // If not, emit it now. - - // Add to the enum list. + // If not, emit it now. Add to the enum list. OS << " " << Signature << ",\n"; - // And to the convert function. CvtOS << " case " << Signature << ":\n"; - CurIndex = 0; - for (unsigned i = 0, e = MIOperandList.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[MIOperandList[i].second]; - - // Add the implicit operands. - for (; CurIndex != Op.OperandInfo->MIOperandNo; ++CurIndex) { - // See if this is a tied operand. - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - } else { - // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CvtOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - } - } - - CvtOS << " ((" << TargetOperandClass << "*)Operands[" - << MIOperandList[i].second - << "+1])->" << Op.Class->RenderMethod - << "(Inst, " << Op.OperandInfo->MINumOperands << ");\n"; - CurIndex += Op.OperandInfo->MINumOperands; - } - - // And add trailing implicit operands. - for (; CurIndex != NumMIOperands; ++CurIndex) { - std::pair *Tie = GetTiedOperandAtIndex(TiedOperands, - CurIndex); - - if (!Tie) { - // If not, this is some implicit operand. Just assume it is a register - // for now. - CvtOS << " Inst.addOperand(MCOperand::CreateReg(0));\n"; - } else { - // Copy the tied operand. - assert(Tie->first>Tie->second && "Tied operand preceeds its target!"); - CvtOS << " Inst.addOperand(Inst.getOperand(" - << Tie->second << "));\n"; - } - } - + CvtOS << CaseOS.str(); CvtOS << " return;\n"; } @@ -1307,11 +1531,39 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, OS << " }\n"; OS << " }\n\n"; - // Classify user defined operands. + // Classify user defined operands. To do so, we need to perform a topological + // sort of the superclass relationship graph so that we always match the + // narrowest type first. + + // Collect the incoming edge counts for each class. + std::map IncomingEdges; for (std::vector::iterator it = Info.Classes.begin(), ie = Info.Classes.end(); it != ie; ++it) { ClassInfo &CI = **it; + if (!CI.isUserClass()) + continue; + + for (std::vector::iterator SI = CI.SuperClasses.begin(), + SE = CI.SuperClasses.end(); SI != SE; ++SI) + ++IncomingEdges[*SI]; + } + + // Initialize a worklist of classes with no incoming edges. + std::vector LeafClasses; + for (std::vector::iterator it = Info.Classes.begin(), + ie = Info.Classes.end(); it != ie; ++it) { + if (!IncomingEdges[*it]) + LeafClasses.push_back(*it); + } + + // Iteratively pop the list, process that class, and update the incoming + // edge counts for its super classes. When a superclass reaches zero + // incoming edges, push it onto the worklist for processing. + while (!LeafClasses.empty()) { + ClassInfo &CI = *LeafClasses.back(); + LeafClasses.pop_back(); + if (!CI.isUserClass()) continue; @@ -1322,6 +1574,10 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, if (i) OS << ", "; OS << "'" << CI.SuperClasses[i]->ClassName << "'"; assert(CI < *CI.SuperClasses[i] && "Invalid class relation!"); + + --IncomingEdges[CI.SuperClasses[i]]; + if (!IncomingEdges[CI.SuperClasses[i]]) + LeafClasses.push_back(CI.SuperClasses[i]); } } OS << "\n"; @@ -1338,6 +1594,7 @@ static void EmitClassifyOperand(AsmMatcherInfo &Info, OS << " return " << CI.Name << ";\n"; OS << " }\n\n"; } + OS << " return InvalidMatchClass;\n"; OS << "}\n\n"; } @@ -1389,8 +1646,6 @@ static void EmitIsSubclass(CodeGenTarget &Target, OS << "}\n\n"; } - - /// EmitMatchTokenString - Emit the function to match a token string to the /// appropriate match class value. static void EmitMatchTokenString(CodeGenTarget &Target, @@ -1486,18 +1741,18 @@ static std::string GetAliasRequiredFeatures(Record *R, unsigned NumFeatures = 0; for (unsigned i = 0, e = ReqFeatures.size(); i != e; ++i) { SubtargetFeatureInfo *F = Info.getSubtargetFeature(ReqFeatures[i]); - + if (F == 0) throw TGError(R->getLoc(), "Predicate '" + ReqFeatures[i]->getName() + "' is not marked as an AssemblerPredicate!"); - + if (NumFeatures) Result += '|'; - + Result += F->getEnumName(); ++NumFeatures; } - + if (NumFeatures > 1) Result = '(' + Result + ')'; return Result; @@ -1506,17 +1761,21 @@ static std::string GetAliasRequiredFeatures(Record *R, /// EmitMnemonicAliases - If the target has any MnemonicAlias<> definitions, /// emit a function for them and return true, otherwise return false. static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { + // Ignore aliases when match-prefix is set. + if (!MatchPrefix.empty()) + return false; + std::vector Aliases = - Records.getAllDerivedDefinitions("MnemonicAlias"); + Info.getRecords().getAllDerivedDefinitions("MnemonicAlias"); if (Aliases.empty()) return false; OS << "static void ApplyMnemonicAliases(StringRef &Mnemonic, " "unsigned Features) {\n"; - + // Keep track of all the aliases from a mnemonic. Use an std::map so that the // iteration order of the map is stable. std::map > AliasesFromMnemonic; - + for (unsigned i = 0, e = Aliases.size(); i != e; ++i) { Record *R = Aliases[i]; AliasesFromMnemonic[R->getValueAsString("FromMnemonic")].push_back(R); @@ -1535,11 +1794,11 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { // emit it last. std::string MatchCode; int AliasWithNoPredicate = -1; - + for (unsigned i = 0, e = ToVec.size(); i != e; ++i) { Record *R = ToVec[i]; std::string FeatureMask = GetAliasRequiredFeatures(R, Info); - + // If this unconditionally matches, remember it for later and diagnose // duplicates. if (FeatureMask.empty()) { @@ -1549,68 +1808,67 @@ static bool EmitMnemonicAliases(raw_ostream &OS, const AsmMatcherInfo &Info) { "two MnemonicAliases with the same 'from' mnemonic!"); throw TGError(R->getLoc(), "this is the other MnemonicAlias."); } - + AliasWithNoPredicate = i; continue; } - + if (!MatchCode.empty()) MatchCode += "else "; MatchCode += "if ((Features & " + FeatureMask + ") == "+FeatureMask+")\n"; MatchCode += " Mnemonic = \"" +R->getValueAsString("ToMnemonic")+"\";\n"; } - + if (AliasWithNoPredicate != -1) { Record *R = ToVec[AliasWithNoPredicate]; if (!MatchCode.empty()) MatchCode += "else\n "; MatchCode += "Mnemonic = \"" + R->getValueAsString("ToMnemonic")+"\";\n"; } - + MatchCode += "return;"; Cases.push_back(std::make_pair(I->first, MatchCode)); } - - + StringMatcher("Mnemonic", Cases, OS).Emit(); - OS << "}\n"; - + OS << "}\n\n"; + return true; } void AsmMatcherEmitter::run(raw_ostream &OS) { - CodeGenTarget Target; + CodeGenTarget Target(Records); Record *AsmParser = Target.getAsmParser(); std::string ClassName = AsmParser->getValueAsString("AsmParserClassName"); // Compute the information on the instructions to match. - AsmMatcherInfo Info(AsmParser, Target); + AsmMatcherInfo Info(AsmParser, Target, Records); Info.BuildInfo(); // Sort the instruction table using the partial order on classes. We use // stable_sort to ensure that ambiguous instructions are still // deterministically ordered. - std::stable_sort(Info.Instructions.begin(), Info.Instructions.end(), - less_ptr()); + std::stable_sort(Info.Matchables.begin(), Info.Matchables.end(), + less_ptr()); DEBUG_WITH_TYPE("instruction_info", { - for (std::vector::iterator - it = Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::iterator + it = Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) (*it)->dump(); }); - // Check for ambiguous instructions. + // Check for ambiguous matchables. DEBUG_WITH_TYPE("ambiguous_instrs", { unsigned NumAmbiguous = 0; - for (unsigned i = 0, e = Info.Instructions.size(); i != e; ++i) { + for (unsigned i = 0, e = Info.Matchables.size(); i != e; ++i) { for (unsigned j = i + 1; j != e; ++j) { - InstructionInfo &A = *Info.Instructions[i]; - InstructionInfo &B = *Info.Instructions[j]; + MatchableInfo &A = *Info.Matchables[i]; + MatchableInfo &B = *Info.Matchables[j]; - if (A.CouldMatchAmiguouslyWith(B)) { - errs() << "warning: ambiguous instruction match:\n"; + if (A.CouldMatchAmbiguouslyWith(B)) { + errs() << "warning: ambiguous matchables:\n"; A.dump(); errs() << "\nis incomparable with:\n"; B.dump(); @@ -1621,7 +1879,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { } if (NumAmbiguous) errs() << "warning: " << NumAmbiguous - << " ambiguous instructions!\n"; + << " ambiguous matchables!\n"; }); // Write the output. @@ -1639,14 +1897,12 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " Match_Success, Match_MnemonicFail, Match_InvalidOperand,\n"; OS << " Match_MissingFeature\n"; OS << " };\n"; - OS << " MatchResultTy MatchInstructionImpl(const " - << "SmallVectorImpl" - << " &Operands, MCInst &Inst, unsigned &ErrorInfo);\n\n"; + OS << " bool MnemonicIsValid(StringRef Mnemonic);\n"; + OS << " MatchResultTy MatchInstructionImpl(\n"; + OS << " const SmallVectorImpl &Operands,\n"; + OS << " MCInst &Inst, unsigned &ErrorInfo);\n\n"; OS << "#endif // GET_ASSEMBLER_HEADER_INFO\n\n"; - - - OS << "\n#ifdef GET_REGISTER_MATCHER\n"; OS << "#undef GET_REGISTER_MATCHER\n\n"; @@ -1664,9 +1920,9 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { // Generate the function that remaps for mnemonic aliases. bool HasMnemonicAliases = EmitMnemonicAliases(OS, Info); - + // Generate the unified function to convert operands into an MCInst. - EmitConvertToMCInst(Target, Info.Instructions, OS); + EmitConvertToMCInst(Target, Info.Matchables, OS); // Emit the enumeration for classes which participate in matching. EmitMatchClassEnumeration(Target, Info.Classes, OS); @@ -1685,11 +1941,10 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { size_t MaxNumOperands = 0; - for (std::vector::const_iterator it = - Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::const_iterator it = + Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) - MaxNumOperands = std::max(MaxNumOperands, (*it)->Operands.size()); - + MaxNumOperands = std::max(MaxNumOperands, (*it)->AsmOperands.size()); // Emit the static match table; unused classes get initalized to 0 which is // guaranteed to be InvalidMatchClass. @@ -1726,18 +1981,19 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "} // end anonymous namespace.\n\n"; OS << "static const MatchEntry MatchTable[" - << Info.Instructions.size() << "] = {\n"; + << Info.Matchables.size() << "] = {\n"; - for (std::vector::const_iterator it = - Info.Instructions.begin(), ie = Info.Instructions.end(); + for (std::vector::const_iterator it = + Info.Matchables.begin(), ie = Info.Matchables.end(); it != ie; ++it) { - InstructionInfo &II = **it; + MatchableInfo &II = **it; + - OS << " { " << Target.getName() << "::" << II.InstrName - << ", \"" << II.Tokens[0] << "\"" - << ", " << II.ConversionFnKind << ", { "; - for (unsigned i = 0, e = II.Operands.size(); i != e; ++i) { - InstructionInfo::Operand &Op = II.Operands[i]; + OS << " { " << Target.getName() << "::" + << II.getResultInst()->TheDef->getName() << ", \"" << II.Mnemonic << "\"" + << ", " << II.ConversionFnKind << ", { "; + for (unsigned i = 0, e = II.AsmOperands.size(); i != e; ++i) { + MatchableInfo::AsmOperand &Op = II.AsmOperands[i]; if (i) OS << ", "; OS << Op.Class->Name; @@ -1758,6 +2014,16 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << "};\n\n"; + // A method to determine if a mnemonic is in the list. + OS << "bool " << Target.getName() << ClassName << "::\n" + << "MnemonicIsValid(StringRef Mnemonic) {\n"; + OS << " // Search the table.\n"; + OS << " std::pair MnemonicRange =\n"; + OS << " std::equal_range(MatchTable, MatchTable+" + << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n"; + OS << " return MnemonicRange.first != MnemonicRange.second;\n"; + OS << "}\n\n"; + // Finally, build the match function. OS << Target.getName() << ClassName << "::MatchResultTy " << Target.getName() << ClassName << "::\n" @@ -1777,7 +2043,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " // Process all MnemonicAliases to remap the mnemonic.\n"; OS << " ApplyMnemonicAliases(Mnemonic, AvailableFeatures);\n\n"; } - + // Emit code to compute the class list for this operand vector. OS << " // Eliminate obvious mismatches.\n"; OS << " if (Operands.size() > " << (MaxNumOperands+1) << ") {\n"; @@ -1812,7 +2078,7 @@ void AsmMatcherEmitter::run(raw_ostream &OS) { OS << " // Search the table.\n"; OS << " std::pair MnemonicRange =\n"; OS << " std::equal_range(MatchTable, MatchTable+" - << Info.Instructions.size() << ", Mnemonic, LessOpcode());\n\n"; + << Info.Matchables.size() << ", Mnemonic, LessOpcode());\n\n"; OS << " // Return a more specific error code if no mnemonics match.\n"; OS << " if (MnemonicRange.first == MnemonicRange.second)\n";