X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=a6d1daf91a485f39d70025fd941df9eff00a2c0c;hb=be5c1fd43fd1cef8a18f41978d147190b50f5510;hp=7f9d4061f9b5b9b30cadfcf3d1bd0e563629e711;hpb=785a41d1388077aabb8f2a5e8e9352bf2a4fb692;p=oota-llvm.git diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 7f9d4061f9b..a6d1daf91a4 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -18,6 +18,7 @@ #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" #include "llvm/TableGen/Error.h" #include "llvm/TableGen/Record.h" @@ -315,7 +316,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { /// chunk of the output as well as indices used for operand printing. /// To reduce the number of unhandled cases, we expand the size from 32-bit /// to 32+16 = 48-bit. - std::vector > OpcodeInfo; + std::vector OpcodeInfo; // Add all strings to the string table upfront so it can generate an optimized // representation. @@ -356,7 +357,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Bias offset by one since we want 0 as a sentinel. - OpcodeInfo.push_back(std::make_pair(Idx+1, 0)); + OpcodeInfo.push_back(Idx+1); } // Figure out how many bits we used for the string index. @@ -364,7 +365,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // To reduce code size, we compactify common instructions into a few bits // in the opcode-indexed table. - unsigned BitsLeft = 32+16-AsmStrBits; + unsigned BitsLeft = 64-AsmStrBits; std::vector > TableDrivenOperandPrinters; @@ -382,13 +383,6 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // ceil(log2(numentries)). unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); - // Check whether these Bits will fit in the first 32 bits. - if (BitsLeft > 16 && NumBits > BitsLeft - 16) - // We don't have enough bits in the first 32 bits, and we skip the - // left-over bits. - BitsLeft = 16; - bool UseSecond = (BitsLeft <= 16); - // If we don't have enough bits for this operand, don't include it. if (NumBits > BitsLeft) { DEBUG(errs() << "Not enough bits to densely encode " << NumBits @@ -397,15 +391,11 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } // Otherwise, we can include this in the initial lookup table. Add it in. - BitsLeft -= NumBits; for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) - // Update the first 32 bits or the second 16 bits. if (InstIdxs[i] != ~0U) { - if (UseSecond) - OpcodeInfo[i].second |= InstIdxs[i] << BitsLeft; - else - OpcodeInfo[i].first |= InstIdxs[i] << (BitsLeft-16+AsmStrBits); + OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); } + BitsLeft -= NumBits; // Remove the info about this operand. for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { @@ -424,21 +414,25 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } - - O<<" static const unsigned OpInfo[] = {\n"; + // We always emit at least one 32-bit table. A second table is emitted if + // more bits are needed. + O<<" static const uint32_t OpInfo[] = {\n"; for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - O << " " << OpcodeInfo[i].first << "U,\t// " + O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " << NumberedInstructions[i]->TheDef->getName() << "\n"; } // Add a dummy entry so the array init doesn't end with a comma. O << " 0U\n"; O << " };\n\n"; - if (BitsLeft < 16) { + if (BitsLeft < 32) { // Add a second OpInfo table only when it is necessary. - O<<" static const uint16_t OpInfo2[] = {\n"; + // Adjust the type of the second table based on the number of bits needed. + O << " static const uint" + << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") + << "_t OpInfo2[] = {\n"; for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - O << " " << OpcodeInfo[i].second << "U,\t// " + O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " << NumberedInstructions[i]->TheDef->getName() << "\n"; } // Add a dummy entry so the array init doesn't end with a comma. @@ -453,15 +447,22 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { O << " O << \"\\t\";\n\n"; - O << " // Emit the opcode for the instruction.\n" - << " unsigned Bits = OpInfo[MI->getOpcode()];\n"; - if (BitsLeft < 16) - O << " unsigned short Bits2 = OpInfo2[MI->getOpcode()];\n"; + O << " // Emit the opcode for the instruction.\n"; + if (BitsLeft < 32) { + // If we have two tables then we need to perform two lookups and combine + // the results into a single 64-bit value. + O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n" + << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n" + << " uint64_t Bits = (Bits2 << 32) | Bits1;\n"; + } else { + // If only one table is used we just need to perform a single lookup. + O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n"; + } O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; // Output the table driven operand information. - BitsLeft = 32+16-AsmStrBits; + BitsLeft = 64-AsmStrBits; for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { std::vector &Commands = TableDrivenOperandPrinters[i]; @@ -470,21 +471,14 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { unsigned NumBits = Log2_32_Ceil(Commands.size()); assert(NumBits <= BitsLeft && "consistency error"); - // Check whether these Bits will fit in the first 32 bits. - if (BitsLeft > 16 && NumBits > BitsLeft - 16) - BitsLeft = 16; - bool UseSecond = (BitsLeft <= 16); - // Emit code to extract this field from Bits. - BitsLeft -= NumBits; - O << "\n // Fragment " << i << " encoded into " << NumBits << " bits for " << Commands.size() << " unique commands.\n"; if (Commands.size() == 2) { // Emit two possibilitys with if/else. - O << (UseSecond ? " if ((Bits2 >> " : " if ((Bits >> ") - << (UseSecond ? BitsLeft : (BitsLeft-16+AsmStrBits)) << ") & " + O << " if ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" << Commands[1] << " } else {\n" @@ -494,8 +488,8 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // Emit a single possibility. O << Commands[0] << "\n\n"; } else { - O << (UseSecond ? " switch ((Bits2 >> " : " switch ((Bits >> ") - << (UseSecond ? BitsLeft : (BitsLeft-16+AsmStrBits)) << ") & " + O << " switch ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" << " default: // unreachable.\n"; @@ -507,6 +501,7 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } O << " }\n\n"; } + BitsLeft -= NumBits; } // Okay, delete instructions with no operand info left. @@ -572,9 +567,9 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, std::vector AltNames = Reg.TheDef->getValueAsListOfStrings("AltNames"); if (AltNames.size() <= Idx) - throw TGError(Reg.TheDef->getLoc(), - (Twine("Register definition missing alt name for '") + - AltName + "'.").str()); + PrintFatalError(Reg.TheDef->getLoc(), + (Twine("Register definition missing alt name for '") + + AltName + "'.").str()); AsmName = AltNames[Idx]; } } @@ -586,7 +581,7 @@ emitRegisterNameString(raw_ostream &O, StringRef AltName, StringTable.emit(O, printChar); O << " };\n\n"; - O << " static const unsigned RegAsmOffset" << AltName << "[] = {"; + O << " static const uint32_t RegAsmOffset" << AltName << "[] = {"; for (unsigned i = 0, e = Registers.size(); i != e; ++i) { if ((i % 14) == 0) O << "\n "; @@ -625,7 +620,7 @@ void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { emitRegisterNameString(O, "", Registers); if (hasAltNames) { - O << " const unsigned *RegAsmOffset;\n" + O << " const uint32_t *RegAsmOffset;\n" << " const char *AsmStrs;\n" << " switch(AltIdx) {\n" << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; @@ -663,7 +658,10 @@ public: void addCond(const std::string &C) { Conds.push_back(C); } - void addOperand(StringRef Op, unsigned Idx) { OpMap[Op] = Idx; } + void addOperand(StringRef Op, unsigned Idx) { + assert(Idx < 0xFF && "Index too large!"); + OpMap[Op] = Idx; + } unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } @@ -687,12 +685,35 @@ public: O << ") {\n"; O.indent(6) << "// " << Result << "\n"; - O.indent(6) << "AsmString = \"" << AsmString << "\";\n"; - for (std::map::iterator - I = OpMap.begin(), E = OpMap.end(); I != E; ++I) - O.indent(6) << "OpMap.push_back(std::make_pair(\"" << I->first << "\", " - << I->second << "));\n"; + // Directly mangle mapped operands into the string. Each operand is + // identified by a '$' sign followed by a byte identifying the number of the + // operand. We add one to the index to avoid zero bytes. + std::pair ASM = StringRef(AsmString).split(' '); + SmallString<128> OutString = ASM.first; + if (!ASM.second.empty()) { + raw_svector_ostream OS(OutString); + OS << ' '; + for (StringRef::iterator I = ASM.second.begin(), E = ASM.second.end(); + I != E;) { + OS << *I; + if (*I == '$') { + StringRef::iterator Start = ++I; + while (I != E && + ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || + (*I >= '0' && *I <= '9') || *I == '_')) + ++I; + StringRef Name(Start, I - Start); + assert(isOpMapped(Name) && "Unmapped operand!"); + OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1); + } else { + ++I; + } + } + } + + // Emit the string. + O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n"; O.indent(6) << "break;\n"; O.indent(4) << '}'; @@ -727,19 +748,6 @@ public: } // end anonymous namespace -static void EmitGetMapOperandNumber(raw_ostream &O) { - O << "static unsigned getMapOperandNumber(" - << "const SmallVectorImpl > &OpMap,\n"; - O << " StringRef Name) {\n"; - O << " for (SmallVectorImpl >::" - << "const_iterator\n"; - O << " I = OpMap.begin(), E = OpMap.end(); I != E; ++I)\n"; - O << " if (I->first == Name)\n"; - O << " return I->second;\n"; - O << " llvm_unreachable(\"Operand not in map!\");\n"; - O << "}\n\n"; -} - static unsigned CountNumOperands(StringRef AsmString) { unsigned NumOps = 0; std::pair ASM = AsmString.split(' '); @@ -798,7 +806,7 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { if (!R->getValueAsBit("EmitAlias")) continue; // We were told not to emit the alias, but to emit the aliasee. const DagInit *DI = R->getValueAsDag("ResultInst"); - const DefInit *Op = dynamic_cast(DI->getOperator()); + const DefInit *Op = cast(DI->getOperator()); AliasMap[getQualifiedName(Op->getDef())].push_back(Alias); } @@ -828,7 +836,6 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); IAP->addCond(Cond); - std::map OpMap; bool CantHandle = false; for (unsigned i = 0, e = LastOpNo; i != e; ++i) { @@ -848,8 +855,11 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { if (!IAP->isOpMapped(ROName)) { IAP->addOperand(ROName, i); + Record *R = CGA->ResultOperands[i].getRecord(); + if (R->isSubClassOf("RegisterOperand")) + R = R->getValueAsDef("RegClass"); Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + - CGA->ResultOperands[i].getRecord()->getName() + "RegClassID)" + R->getName() + "RegClassID)" ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())"; IAP->addCond(Cond); } else { @@ -869,12 +879,18 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { break; } - case CodeGenInstAlias::ResultOperand::K_Imm: - Cond = std::string("MI->getOperand(") + - llvm::utostr(i) + ").getImm() == " + - llvm::utostr(CGA->ResultOperands[i].getImm()); + case CodeGenInstAlias::ResultOperand::K_Imm: { + std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")"; + + // Just because the alias has an immediate result, doesn't mean the + // MCInst will. An MCExpr could be present, for example. + IAP->addCond(Op + ".isImm()"); + + Cond = Op + ".getImm() == " + + llvm::utostr(CGA->ResultOperands[i].getImm()); IAP->addCond(Cond); break; + } case CodeGenInstAlias::ResultOperand::K_Reg: // If this is zero_reg, something's playing tricks we're not // equipped to handle. @@ -952,11 +968,8 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { return; } - EmitGetMapOperandNumber(O); - O << HeaderO.str(); - O.indent(2) << "StringRef AsmString;\n"; - O.indent(2) << "SmallVector, 4> OpMap;\n"; + O.indent(2) << "const char *AsmString;\n"; O.indent(2) << "switch (MI->getOpcode()) {\n"; O.indent(2) << "default: return false;\n"; O << CasesO.str(); @@ -964,27 +977,21 @@ void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { // Code that prints the alias, replacing the operands with the ones from the // MCInst. - O << " std::pair ASM = AsmString.split(' ');\n"; - O << " OS << '\\t' << ASM.first;\n"; + O << " unsigned I = 0;\n"; + O << " while (AsmString[I] != ' ' && AsmString[I] != '\\0')\n"; + O << " ++I;\n"; + O << " OS << '\\t' << StringRef(AsmString, I);\n"; - O << " if (!ASM.second.empty()) {\n"; + O << " if (AsmString[I] != '\\0') {\n"; O << " OS << '\\t';\n"; - O << " for (StringRef::iterator\n"; - O << " I = ASM.second.begin(), E = ASM.second.end(); I != E; ) {\n"; - O << " if (*I == '$') {\n"; - O << " StringRef::iterator Start = ++I;\n"; - O << " while (I != E &&\n"; - O << " ((*I >= 'a' && *I <= 'z') ||\n"; - O << " (*I >= 'A' && *I <= 'Z') ||\n"; - O << " (*I >= '0' && *I <= '9') ||\n"; - O << " *I == '_'))\n"; - O << " ++I;\n"; - O << " StringRef Name(Start, I - Start);\n"; - O << " printOperand(MI, getMapOperandNumber(OpMap, Name), OS);\n"; + O << " do {\n"; + O << " if (AsmString[I] == '$') {\n"; + O << " ++I;\n"; + O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n"; O << " } else {\n"; - O << " OS << *I++;\n"; + O << " OS << AsmString[I++];\n"; O << " }\n"; - O << " }\n"; + O << " } while (AsmString[I] != '\\0');\n"; O << " }\n\n"; O << " return true;\n";