X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FAsmWriterEmitter.cpp;h=a6d1daf91a485f39d70025fd941df9eff00a2c0c;hb=be5c1fd43fd1cef8a18f41978d147190b50f5510;hp=9378343cec78843c5ab575faea7012f43ca92f26;hpb=f65027842e82027dd6e8020586a299aaa548e355;p=oota-llvm.git diff --git a/utils/TableGen/AsmWriterEmitter.cpp b/utils/TableGen/AsmWriterEmitter.cpp index 9378343cec7..a6d1daf91a4 100644 --- a/utils/TableGen/AsmWriterEmitter.cpp +++ b/utils/TableGen/AsmWriterEmitter.cpp @@ -12,16 +12,51 @@ // //===----------------------------------------------------------------------===// -#include "AsmWriterEmitter.h" #include "AsmWriterInst.h" #include "CodeGenTarget.h" -#include "Record.h" -#include "StringToOffsetTable.h" +#include "SequenceToOffsetTable.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/ADT/Twine.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/Format.h" #include "llvm/Support/MathExtras.h" +#include "llvm/TableGen/Error.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" #include +#include +#include +#include using namespace llvm; +namespace { +class AsmWriterEmitter { + RecordKeeper &Records; + std::map CGIAWIMap; + std::vector NumberedInstructions; +public: + AsmWriterEmitter(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &o); + +private: + void EmitPrintInstruction(raw_ostream &o); + void EmitGetRegisterName(raw_ostream &o); + void EmitPrintAliasInstruction(raw_ostream &O); + + AsmWriterInst *getAsmWriterInstByID(unsigned ID) const { + assert(ID < NumberedInstructions.size()); + std::map::const_iterator I = + CGIAWIMap.find(NumberedInstructions[ID]); + assert(I != CGIAWIMap.end() && "Didn't find inst!"); + return I->second; + } + void FindUniqueOperandCommands(std::vector &UOC, + std::vector &InstIdxs, + std::vector &InstOpsUsed) const; +}; +} // end anonymous namespace + static void PrintCases(std::vector > &OpsToPrint, raw_ostream &O) { O << " case " << OpsToPrint.back().first << ": "; @@ -101,22 +136,22 @@ static void EmitInstructions(std::vector &Insts, } void AsmWriterEmitter:: -FindUniqueOperandCommands(std::vector &UniqueOperandCommands, +FindUniqueOperandCommands(std::vector &UniqueOperandCommands, std::vector &InstIdxs, std::vector &InstOpsUsed) const { InstIdxs.assign(NumberedInstructions.size(), ~0U); - + // This vector parallels UniqueOperandCommands, keeping track of which // instructions each case are used for. It is a comma separated string of // enums. std::vector InstrsForCase; InstrsForCase.resize(UniqueOperandCommands.size()); InstOpsUsed.assign(UniqueOperandCommands.size(), 0); - + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { const AsmWriterInst *Inst = getAsmWriterInstByID(i); - if (Inst == 0) continue; // PHI, INLINEASM, DBG_LABEL, etc. - + if (Inst == 0) continue; // PHI, INLINEASM, PROLOG_LABEL, etc. + std::string Command; if (Inst->Operands.empty()) continue; // Instruction already done. @@ -143,13 +178,13 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, InstOpsUsed.push_back(1); } } - + // For each entry of UniqueOperandCommands, there is a set of instructions // that uses it. If the next command of all instructions in the set are // identical, fold it into the command. for (unsigned CommandIdx = 0, e = UniqueOperandCommands.size(); CommandIdx != e; ++CommandIdx) { - + for (unsigned Op = 1; ; ++Op) { // Scan for the first instruction in the set. std::vector::iterator NIT = @@ -158,7 +193,7 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, // If this instruction has no more operands, we isn't anything to merge // into this command. - const AsmWriterInst *FirstInst = + const AsmWriterInst *FirstInst = getAsmWriterInstByID(NIT-InstIdxs.begin()); if (!FirstInst || FirstInst->Operands.size() == Op) break; @@ -175,7 +210,7 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, NIT = std::find(NIT+1, InstIdxs.end(), CommandIdx)) { // Okay, found another instruction in this command set. If the operand // matches, we're ok, otherwise bail out. - const AsmWriterInst *OtherInst = + const AsmWriterInst *OtherInst = getAsmWriterInstByID(NIT-InstIdxs.begin()); if (OtherInst && @@ -189,16 +224,16 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, } } if (!AllSame) break; - + // Okay, everything in this command set has the same next operand. Add it // to UniqueOperandCommands and remember that it was consumed. std::string Command = " " + FirstInst->Operands[Op].getCode() + "\n"; - + UniqueOperandCommands[CommandIdx] += Command; InstOpsUsed[CommandIdx]++; } } - + // Prepend some of the instructions each case is used for onto the case val. for (unsigned i = 0, e = InstrsForCase.size(); i != e; ++i) { std::string Instrs = InstrsForCase[i]; @@ -206,9 +241,9 @@ FindUniqueOperandCommands(std::vector &UniqueOperandCommands, Instrs.erase(Instrs.begin()+70, Instrs.end()); Instrs += "..."; } - + if (!Instrs.empty()) - UniqueOperandCommands[i] = " // " + Instrs + "\n" + + UniqueOperandCommands[i] = " // " + Instrs + "\n" + UniqueOperandCommands[i]; } } @@ -240,31 +275,34 @@ static void UnescapeString(std::string &Str) { /// EmitPrintInstruction - Generate the code for the "printInstruction" method /// implementation. void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { - CodeGenTarget Target; + CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - + bool isMC = AsmWriter->getValueAsBit("isMCAsmWriter"); + const char *MachineInstrClassName = isMC ? "MCInst" : "MachineInstr"; + O << "/// printInstruction - This method is automatically generated by tablegen\n" "/// from the instruction set description.\n" "void " << Target.getName() << ClassName - << "::printInstruction(const MachineInstr *MI) {\n"; + << "::printInstruction(const " << MachineInstrClassName + << " *MI, raw_ostream &O) {\n"; std::vector Instructions; for (CodeGenTarget::inst_iterator I = Target.inst_begin(), E = Target.inst_end(); I != E; ++I) - if (!I->second.AsmString.empty() && - I->second.TheDef->getName() != "PHI") + if (!(*I)->AsmString.empty() && + (*I)->TheDef->getName() != "PHI") Instructions.push_back( - AsmWriterInst(I->second, + AsmWriterInst(**I, AsmWriter->getValueAsInt("Variant"), AsmWriter->getValueAsInt("FirstOperandColumn"), AsmWriter->getValueAsInt("OperandSpacing"))); // Get the instruction numbering. NumberedInstructions = Target.getInstructionsByEnumValue(); - + // Compute the CodeGenInstruction -> AsmWriterInst mapping. Note that not // all machine instructions are necessarily being printed, so there may be // target instructions not in this map. @@ -272,12 +310,30 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { CGIAWIMap.insert(std::make_pair(Instructions[i].CGI, &Instructions[i])); // Build an aggregate string, and build a table of offsets into it. - StringToOffsetTable StringTable; - + SequenceToOffsetTable StringTable; + /// OpcodeInfo - This encodes the index of the string to use for the first /// chunk of the output as well as indices used for operand printing. - std::vector OpcodeInfo; - + /// To reduce the number of unhandled cases, we expand the size from 32-bit + /// to 32+16 = 48-bit. + std::vector OpcodeInfo; + + // Add all strings to the string table upfront so it can generate an optimized + // representation. + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; + if (AWI != 0 && + AWI->Operands[0].OperandType == + AsmWriterOperand::isLiteralTextOperand && + !AWI->Operands[0].Str.empty()) { + std::string Str = AWI->Operands[0].Str; + UnescapeString(Str); + StringTable.add(Str); + } + } + + StringTable.layout(); + unsigned MaxStringIdx = 0; for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { AsmWriterInst *AWI = CGIAWIMap[NumberedInstructions[i]]; @@ -285,61 +341,62 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { if (AWI == 0) { // Something not handled by the asmwriter printer. Idx = ~0U; - } else if (AWI->Operands[0].OperandType != + } else if (AWI->Operands[0].OperandType != AsmWriterOperand::isLiteralTextOperand || AWI->Operands[0].Str.empty()) { // Something handled by the asmwriter printer, but with no leading string. - Idx = StringTable.GetOrAddStringOffset(""); + Idx = StringTable.get(""); } else { std::string Str = AWI->Operands[0].Str; UnescapeString(Str); - Idx = StringTable.GetOrAddStringOffset(Str); + Idx = StringTable.get(Str); MaxStringIdx = std::max(MaxStringIdx, Idx); - + // Nuke the string from the operand list. It is now handled! AWI->Operands.erase(AWI->Operands.begin()); } - + // Bias offset by one since we want 0 as a sentinel. OpcodeInfo.push_back(Idx+1); } - + // Figure out how many bits we used for the string index. unsigned AsmStrBits = Log2_32_Ceil(MaxStringIdx+2); - + // To reduce code size, we compactify common instructions into a few bits // in the opcode-indexed table. - unsigned BitsLeft = 32-AsmStrBits; + unsigned BitsLeft = 64-AsmStrBits; std::vector > TableDrivenOperandPrinters; - + while (1) { std::vector UniqueOperandCommands; std::vector InstIdxs; std::vector NumInstOpsHandled; FindUniqueOperandCommands(UniqueOperandCommands, InstIdxs, NumInstOpsHandled); - + // If we ran out of operands to print, we're done. if (UniqueOperandCommands.empty()) break; - + // Compute the number of bits we need to represent these cases, this is // ceil(log2(numentries)). unsigned NumBits = Log2_32_Ceil(UniqueOperandCommands.size()); - + // If we don't have enough bits for this operand, don't include it. if (NumBits > BitsLeft) { DEBUG(errs() << "Not enough bits to densely encode " << NumBits << " more bits\n"); break; } - + // Otherwise, we can include this in the initial lookup table. Add it in. - BitsLeft -= NumBits; for (unsigned i = 0, e = InstIdxs.size(); i != e; ++i) - if (InstIdxs[i] != ~0U) - OpcodeInfo[i] |= InstIdxs[i] << (BitsLeft+AsmStrBits); - + if (InstIdxs[i] != ~0U) { + OpcodeInfo[i] |= (uint64_t)InstIdxs[i] << (64-BitsLeft); + } + BitsLeft -= NumBits; + // Remove the info about this operand. for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { if (AsmWriterInst *Inst = getAsmWriterInstByID(i)) @@ -351,36 +408,61 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { Inst->Operands.begin()+NumOps); } } - + // Remember the handlers for this set of operands. TableDrivenOperandPrinters.push_back(UniqueOperandCommands); } - - - - O<<" static const unsigned OpInfo[] = {\n"; + + + // We always emit at least one 32-bit table. A second table is emitted if + // more bits are needed. + O<<" static const uint32_t OpInfo[] = {\n"; for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - O << " " << OpcodeInfo[i] << "U,\t// " + O << " " << (OpcodeInfo[i] & 0xffffffff) << "U,\t// " << NumberedInstructions[i]->TheDef->getName() << "\n"; } // Add a dummy entry so the array init doesn't end with a comma. O << " 0U\n"; O << " };\n\n"; - + + if (BitsLeft < 32) { + // Add a second OpInfo table only when it is necessary. + // Adjust the type of the second table based on the number of bits needed. + O << " static const uint" + << ((BitsLeft < 16) ? "32" : (BitsLeft < 24) ? "16" : "8") + << "_t OpInfo2[] = {\n"; + for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { + O << " " << (OpcodeInfo[i] >> 32) << "U,\t// " + << NumberedInstructions[i]->TheDef->getName() << "\n"; + } + // Add a dummy entry so the array init doesn't end with a comma. + O << " 0U\n"; + O << " };\n\n"; + } + // Emit the string itself. - O << " const char *AsmStrs = \n"; - StringTable.EmitString(O); - O << ";\n\n"; + O << " const char AsmStrs[] = {\n"; + StringTable.emit(O, printChar); + O << " };\n\n"; O << " O << \"\\t\";\n\n"; - O << " // Emit the opcode for the instruction.\n" - << " unsigned Bits = OpInfo[MI->getOpcode()];\n" - << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" + O << " // Emit the opcode for the instruction.\n"; + if (BitsLeft < 32) { + // If we have two tables then we need to perform two lookups and combine + // the results into a single 64-bit value. + O << " uint64_t Bits1 = OpInfo[MI->getOpcode()];\n" + << " uint64_t Bits2 = OpInfo2[MI->getOpcode()];\n" + << " uint64_t Bits = (Bits2 << 32) | Bits1;\n"; + } else { + // If only one table is used we just need to perform a single lookup. + O << " uint32_t Bits = OpInfo[MI->getOpcode()];\n"; + } + O << " assert(Bits != 0 && \"Cannot print this instruction.\");\n" << " O << AsmStrs+(Bits & " << (1 << AsmStrBits)-1 << ")-1;\n\n"; // Output the table driven operand information. - BitsLeft = 32-AsmStrBits; + BitsLeft = 64-AsmStrBits; for (unsigned i = 0, e = TableDrivenOperandPrinters.size(); i != e; ++i) { std::vector &Commands = TableDrivenOperandPrinters[i]; @@ -388,26 +470,29 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { // ceil(log2(numentries)). unsigned NumBits = Log2_32_Ceil(Commands.size()); assert(NumBits <= BitsLeft && "consistency error"); - + // Emit code to extract this field from Bits. - BitsLeft -= NumBits; - O << "\n // Fragment " << i << " encoded into " << NumBits << " bits for " << Commands.size() << " unique commands.\n"; - + if (Commands.size() == 2) { // Emit two possibilitys with if/else. - O << " if ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " + O << " if ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" << Commands[1] << " } else {\n" << Commands[0] << " }\n\n"; + } else if (Commands.size() == 1) { + // Emit a single possibility. + O << Commands[0] << "\n\n"; } else { - O << " switch ((Bits >> " << (BitsLeft+AsmStrBits) << ") & " + O << " switch ((Bits >> " + << (64-BitsLeft) << ") & " << ((1 << NumBits)-1) << ") {\n" << " default: // unreachable.\n"; - + // Print out all the cases. for (unsigned i = 0, e = Commands.size(); i != e; ++i) { O << " case " << i << ":\n"; @@ -416,8 +501,9 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } O << " }\n\n"; } + BitsLeft -= NumBits; } - + // Okay, delete instructions with no operand info left. for (unsigned i = 0, e = Instructions.size(); i != e; ++i) { // Entire instruction has been emitted? @@ -428,12 +514,12 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { } } - + // Because this is a vector, we want to emit from the end. Reverse all of the // elements in the vector. std::reverse(Instructions.begin(), Instructions.end()); - - + + // Now that we've emitted all of the operand info that fit into 32 bits, emit // information for those instructions that are left. This is a less dense // encoding, but we expect the main 32-bit table to handle the majority of @@ -451,98 +537,481 @@ void AsmWriterEmitter::EmitPrintInstruction(raw_ostream &O) { O << "}\n"; } +static void +emitRegisterNameString(raw_ostream &O, StringRef AltName, + const std::vector &Registers) { + SequenceToOffsetTable StringTable; + SmallVector AsmNames(Registers.size()); + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + const CodeGenRegister &Reg = *Registers[i]; + std::string &AsmName = AsmNames[i]; + + // "NoRegAltName" is special. We don't need to do a lookup for that, + // as it's just a reference to the default register name. + if (AltName == "" || AltName == "NoRegAltName") { + AsmName = Reg.TheDef->getValueAsString("AsmName"); + if (AsmName.empty()) + AsmName = Reg.getName(); + } else { + // Make sure the register has an alternate name for this index. + std::vector AltNameList = + Reg.TheDef->getValueAsListOfDefs("RegAltNameIndices"); + unsigned Idx = 0, e; + for (e = AltNameList.size(); + Idx < e && (AltNameList[Idx]->getName() != AltName); + ++Idx) + ; + // If the register has an alternate name for this index, use it. + // Otherwise, leave it empty as an error flag. + if (Idx < e) { + std::vector AltNames = + Reg.TheDef->getValueAsListOfStrings("AltNames"); + if (AltNames.size() <= Idx) + PrintFatalError(Reg.TheDef->getLoc(), + (Twine("Register definition missing alt name for '") + + AltName + "'.").str()); + AsmName = AltNames[Idx]; + } + } + StringTable.add(AsmName); + } + + StringTable.layout(); + O << " static const char AsmStrs" << AltName << "[] = {\n"; + StringTable.emit(O, printChar); + O << " };\n\n"; + + O << " static const uint32_t RegAsmOffset" << AltName << "[] = {"; + for (unsigned i = 0, e = Registers.size(); i != e; ++i) { + if ((i % 14) == 0) + O << "\n "; + O << StringTable.get(AsmNames[i]) << ", "; + } + O << "\n };\n" + << "\n"; +} void AsmWriterEmitter::EmitGetRegisterName(raw_ostream &O) { - CodeGenTarget Target; + CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - const std::vector &Registers = Target.getRegisters(); - - StringToOffsetTable StringTable; + const std::vector &Registers = + Target.getRegBank().getRegisters(); + std::vector AltNameIndices = Target.getRegAltNameIndices(); + bool hasAltNames = AltNameIndices.size() > 1; + O << "\n\n/// getRegisterName - This method is automatically generated by tblgen\n" "/// from the register set description. This returns the assembler name\n" "/// for the specified register.\n" - "const char *" << Target.getName() << ClassName - << "::getRegisterName(unsigned RegNo) {\n" - << " assert(RegNo && RegNo < " << (Registers.size()+1) - << " && \"Invalid register number!\");\n" - << "\n" - << " static const unsigned RegAsmOffset[] = {"; - for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - const CodeGenRegister &Reg = Registers[i]; + "const char *" << Target.getName() << ClassName << "::"; + if (hasAltNames) + O << "\ngetRegisterName(unsigned RegNo, unsigned AltIdx) {\n"; + else + O << "getRegisterName(unsigned RegNo) {\n"; + O << " assert(RegNo && RegNo < " << (Registers.size()+1) + << " && \"Invalid register number!\");\n" + << "\n"; - std::string AsmName = Reg.TheDef->getValueAsString("AsmName"); - if (AsmName.empty()) - AsmName = Reg.getName(); - - - if ((i % 14) == 0) - O << "\n "; - - O << StringTable.GetOrAddStringOffset(AsmName) << ", "; + if (hasAltNames) { + for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) + emitRegisterNameString(O, AltNameIndices[i]->getName(), Registers); + } else + emitRegisterNameString(O, "", Registers); + + if (hasAltNames) { + O << " const uint32_t *RegAsmOffset;\n" + << " const char *AsmStrs;\n" + << " switch(AltIdx) {\n" + << " default: llvm_unreachable(\"Invalid register alt name index!\");\n"; + for (unsigned i = 0, e = AltNameIndices.size(); i < e; ++i) { + StringRef Namespace = AltNameIndices[1]->getValueAsString("Namespace"); + StringRef AltName(AltNameIndices[i]->getName()); + O << " case " << Namespace << "::" << AltName + << ":\n" + << " AsmStrs = AsmStrs" << AltName << ";\n" + << " RegAsmOffset = RegAsmOffset" << AltName << ";\n" + << " break;\n"; + } + O << "}\n"; } - O << "0\n" - << " };\n" - << "\n"; - - O << " const char *AsmStrs =\n"; - StringTable.EmitString(O); - O << ";\n"; - - O << " return AsmStrs+RegAsmOffset[RegNo-1];\n" + + O << " assert (*(AsmStrs+RegAsmOffset[RegNo-1]) &&\n" + << " \"Invalid alt name index for register!\");\n" + << " return AsmStrs+RegAsmOffset[RegNo-1];\n" << "}\n"; } -void AsmWriterEmitter::EmitGetInstructionName(raw_ostream &O) { - CodeGenTarget Target; +namespace { +// IAPrinter - Holds information about an InstAlias. Two InstAliases match if +// they both have the same conditionals. In which case, we cannot print out the +// alias for that pattern. +class IAPrinter { + std::vector Conds; + std::map OpMap; + std::string Result; + std::string AsmString; + SmallVector ReqFeatures; +public: + IAPrinter(std::string R, std::string AS) + : Result(R), AsmString(AS) {} + + void addCond(const std::string &C) { Conds.push_back(C); } + + void addOperand(StringRef Op, unsigned Idx) { + assert(Idx < 0xFF && "Index too large!"); + OpMap[Op] = Idx; + } + unsigned getOpIndex(StringRef Op) { return OpMap[Op]; } + bool isOpMapped(StringRef Op) { return OpMap.find(Op) != OpMap.end(); } + + void print(raw_ostream &O) { + if (Conds.empty() && ReqFeatures.empty()) { + O.indent(6) << "return true;\n"; + return; + } + + O << "if ("; + + for (std::vector::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) { + if (I != Conds.begin()) { + O << " &&\n"; + O.indent(8); + } + + O << *I; + } + + O << ") {\n"; + O.indent(6) << "// " << Result << "\n"; + + // Directly mangle mapped operands into the string. Each operand is + // identified by a '$' sign followed by a byte identifying the number of the + // operand. We add one to the index to avoid zero bytes. + std::pair ASM = StringRef(AsmString).split(' '); + SmallString<128> OutString = ASM.first; + if (!ASM.second.empty()) { + raw_svector_ostream OS(OutString); + OS << ' '; + for (StringRef::iterator I = ASM.second.begin(), E = ASM.second.end(); + I != E;) { + OS << *I; + if (*I == '$') { + StringRef::iterator Start = ++I; + while (I != E && + ((*I >= 'a' && *I <= 'z') || (*I >= 'A' && *I <= 'Z') || + (*I >= '0' && *I <= '9') || *I == '_')) + ++I; + StringRef Name(Start, I - Start); + assert(isOpMapped(Name) && "Unmapped operand!"); + OS << format("\\x%02X", (unsigned char)getOpIndex(Name) + 1); + } else { + ++I; + } + } + } + + // Emit the string. + O.indent(6) << "AsmString = \"" << OutString.str() << "\";\n"; + + O.indent(6) << "break;\n"; + O.indent(4) << '}'; + } + + bool operator==(const IAPrinter &RHS) { + if (Conds.size() != RHS.Conds.size()) + return false; + + unsigned Idx = 0; + for (std::vector::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) + if (*I != RHS.Conds[Idx++]) + return false; + + return true; + } + + bool operator()(const IAPrinter &RHS) { + if (Conds.size() < RHS.Conds.size()) + return true; + + unsigned Idx = 0; + for (std::vector::iterator + I = Conds.begin(), E = Conds.end(); I != E; ++I) + if (*I != RHS.Conds[Idx++]) + return *I < RHS.Conds[Idx++]; + + return false; + } +}; + +} // end anonymous namespace + +static unsigned CountNumOperands(StringRef AsmString) { + unsigned NumOps = 0; + std::pair ASM = AsmString.split(' '); + + while (!ASM.second.empty()) { + ++NumOps; + ASM = ASM.second.split(' '); + } + + return NumOps; +} + +static unsigned CountResultNumOperands(StringRef AsmString) { + unsigned NumOps = 0; + std::pair ASM = AsmString.split('\t'); + + if (!ASM.second.empty()) { + size_t I = ASM.second.find('{'); + StringRef Str = ASM.second; + if (I != StringRef::npos) + Str = ASM.second.substr(I, ASM.second.find('|', I)); + + ASM = Str.split(' '); + + do { + ++NumOps; + ASM = ASM.second.split(' '); + } while (!ASM.second.empty()); + } + + return NumOps; +} + +void AsmWriterEmitter::EmitPrintAliasInstruction(raw_ostream &O) { + CodeGenTarget Target(Records); Record *AsmWriter = Target.getAsmWriter(); + + if (!AsmWriter->getValueAsBit("isMCAsmWriter")) + return; + + O << "\n#ifdef PRINT_ALIAS_INSTR\n"; + O << "#undef PRINT_ALIAS_INSTR\n\n"; + + // Emit the method that prints the alias instruction. std::string ClassName = AsmWriter->getValueAsString("AsmWriterClassName"); - const std::vector &NumberedInstructions = - Target.getInstructionsByEnumValue(); - - StringToOffsetTable StringTable; - O << -"\n\n#ifdef GET_INSTRUCTION_NAME\n" -"#undef GET_INSTRUCTION_NAME\n\n" -"/// getInstructionName: This method is automatically generated by tblgen\n" -"/// from the instruction set description. This returns the enum name of the\n" -"/// specified instruction.\n" - "const char *" << Target.getName() << ClassName - << "::getInstructionName(unsigned Opcode) {\n" - << " assert(Opcode < " << NumberedInstructions.size() - << " && \"Invalid instruction number!\");\n" - << "\n" - << " static const unsigned InstAsmOffset[] = {"; - for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) { - const CodeGenInstruction &Inst = *NumberedInstructions[i]; - - std::string AsmName = Inst.TheDef->getName(); - if ((i % 14) == 0) - O << "\n "; - - O << StringTable.GetOrAddStringOffset(AsmName) << ", "; + std::vector AllInstAliases = + Records.getAllDerivedDefinitions("InstAlias"); + + // Create a map from the qualified name to a list of potential matches. + std::map > AliasMap; + for (std::vector::iterator + I = AllInstAliases.begin(), E = AllInstAliases.end(); I != E; ++I) { + CodeGenInstAlias *Alias = new CodeGenInstAlias(*I, Target); + const Record *R = *I; + if (!R->getValueAsBit("EmitAlias")) + continue; // We were told not to emit the alias, but to emit the aliasee. + const DagInit *DI = R->getValueAsDag("ResultInst"); + const DefInit *Op = cast(DI->getOperator()); + AliasMap[getQualifiedName(Op->getDef())].push_back(Alias); } - O << "0\n" - << " };\n" - << "\n"; - - O << " const char *Strs =\n"; - StringTable.EmitString(O); - O << ";\n"; - - O << " return Strs+InstAsmOffset[Opcode];\n" - << "}\n\n#endif\n"; -} + // A map of which conditions need to be met for each instruction operand + // before it can be matched to the mnemonic. + std::map > IAPrinterMap; + + for (std::map >::iterator + I = AliasMap.begin(), E = AliasMap.end(); I != E; ++I) { + std::vector &Aliases = I->second; + + for (std::vector::iterator + II = Aliases.begin(), IE = Aliases.end(); II != IE; ++II) { + const CodeGenInstAlias *CGA = *II; + unsigned LastOpNo = CGA->ResultInstOperandIndex.size(); + unsigned NumResultOps = + CountResultNumOperands(CGA->ResultInst->AsmString); + + // Don't emit the alias if it has more operands than what it's aliasing. + if (NumResultOps < CountNumOperands(CGA->AsmString)) + continue; + + IAPrinter *IAP = new IAPrinter(CGA->Result->getAsString(), + CGA->AsmString); + + std::string Cond; + Cond = std::string("MI->getNumOperands() == ") + llvm::utostr(LastOpNo); + IAP->addCond(Cond); + + bool CantHandle = false; + + for (unsigned i = 0, e = LastOpNo; i != e; ++i) { + const CodeGenInstAlias::ResultOperand &RO = CGA->ResultOperands[i]; + + switch (RO.Kind) { + case CodeGenInstAlias::ResultOperand::K_Record: { + const Record *Rec = RO.getRecord(); + StringRef ROName = RO.getName(); + + + if (Rec->isSubClassOf("RegisterOperand")) + Rec = Rec->getValueAsDef("RegClass"); + if (Rec->isSubClassOf("RegisterClass")) { + Cond = std::string("MI->getOperand(")+llvm::utostr(i)+").isReg()"; + IAP->addCond(Cond); + + if (!IAP->isOpMapped(ROName)) { + IAP->addOperand(ROName, i); + Record *R = CGA->ResultOperands[i].getRecord(); + if (R->isSubClassOf("RegisterOperand")) + R = R->getValueAsDef("RegClass"); + Cond = std::string("MRI.getRegClass(") + Target.getName() + "::" + + R->getName() + "RegClassID)" + ".contains(MI->getOperand(" + llvm::utostr(i) + ").getReg())"; + IAP->addCond(Cond); + } else { + Cond = std::string("MI->getOperand(") + + llvm::utostr(i) + ").getReg() == MI->getOperand(" + + llvm::utostr(IAP->getOpIndex(ROName)) + ").getReg()"; + IAP->addCond(Cond); + } + } else { + assert(Rec->isSubClassOf("Operand") && "Unexpected operand!"); + // FIXME: We may need to handle these situations. + delete IAP; + IAP = 0; + CantHandle = true; + break; + } + + break; + } + case CodeGenInstAlias::ResultOperand::K_Imm: { + std::string Op = "MI->getOperand(" + llvm::utostr(i) + ")"; + + // Just because the alias has an immediate result, doesn't mean the + // MCInst will. An MCExpr could be present, for example. + IAP->addCond(Op + ".isImm()"); + + Cond = Op + ".getImm() == " + + llvm::utostr(CGA->ResultOperands[i].getImm()); + IAP->addCond(Cond); + break; + } + case CodeGenInstAlias::ResultOperand::K_Reg: + // If this is zero_reg, something's playing tricks we're not + // equipped to handle. + if (!CGA->ResultOperands[i].getRegister()) { + CantHandle = true; + break; + } + + Cond = std::string("MI->getOperand(") + + llvm::utostr(i) + ").getReg() == " + Target.getName() + + "::" + CGA->ResultOperands[i].getRegister()->getName(); + IAP->addCond(Cond); + break; + } + + if (!IAP) break; + } + + if (CantHandle) continue; + IAPrinterMap[I->first].push_back(IAP); + } + } + + std::string Header; + raw_string_ostream HeaderO(Header); + + HeaderO << "bool " << Target.getName() << ClassName + << "::printAliasInstr(const MCInst" + << " *MI, raw_ostream &OS) {\n"; + + std::string Cases; + raw_string_ostream CasesO(Cases); + + for (std::map >::iterator + I = IAPrinterMap.begin(), E = IAPrinterMap.end(); I != E; ++I) { + std::vector &IAPs = I->second; + std::vector UniqueIAPs; + + for (std::vector::iterator + II = IAPs.begin(), IE = IAPs.end(); II != IE; ++II) { + IAPrinter *LHS = *II; + bool IsDup = false; + for (std::vector::iterator + III = IAPs.begin(), IIE = IAPs.end(); III != IIE; ++III) { + IAPrinter *RHS = *III; + if (LHS != RHS && *LHS == *RHS) { + IsDup = true; + break; + } + } + + if (!IsDup) UniqueIAPs.push_back(LHS); + } + + if (UniqueIAPs.empty()) continue; + CasesO.indent(2) << "case " << I->first << ":\n"; + + for (std::vector::iterator + II = UniqueIAPs.begin(), IE = UniqueIAPs.end(); II != IE; ++II) { + IAPrinter *IAP = *II; + CasesO.indent(4); + IAP->print(CasesO); + CasesO << '\n'; + } + + CasesO.indent(4) << "return false;\n"; + } + + if (CasesO.str().empty()) { + O << HeaderO.str(); + O << " return false;\n"; + O << "}\n\n"; + O << "#endif // PRINT_ALIAS_INSTR\n"; + return; + } + + O << HeaderO.str(); + O.indent(2) << "const char *AsmString;\n"; + O.indent(2) << "switch (MI->getOpcode()) {\n"; + O.indent(2) << "default: return false;\n"; + O << CasesO.str(); + O.indent(2) << "}\n\n"; + + // Code that prints the alias, replacing the operands with the ones from the + // MCInst. + O << " unsigned I = 0;\n"; + O << " while (AsmString[I] != ' ' && AsmString[I] != '\\0')\n"; + O << " ++I;\n"; + O << " OS << '\\t' << StringRef(AsmString, I);\n"; + + O << " if (AsmString[I] != '\\0') {\n"; + O << " OS << '\\t';\n"; + O << " do {\n"; + O << " if (AsmString[I] == '$') {\n"; + O << " ++I;\n"; + O << " printOperand(MI, unsigned(AsmString[I++]) - 1, OS);\n"; + O << " } else {\n"; + O << " OS << AsmString[I++];\n"; + O << " }\n"; + O << " } while (AsmString[I] != '\\0');\n"; + O << " }\n\n"; + + O << " return true;\n"; + O << "}\n\n"; + + O << "#endif // PRINT_ALIAS_INSTR\n"; +} void AsmWriterEmitter::run(raw_ostream &O) { - EmitSourceFileHeader("Assembly Writer Source Fragment", O); - EmitPrintInstruction(O); EmitGetRegisterName(O); - EmitGetInstructionName(O); + EmitPrintAliasInstruction(O); +} + + +namespace llvm { + +void EmitAsmWriter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Assembly Writer Source Fragment", OS); + AsmWriterEmitter(RK).run(OS); } +} // End llvm namespace