X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=46fcdf5e96ffdcc48a4d17a94094ac94cbd64fdf;hb=47f0e3f434e2e43f951c3a826c40906cb15b7285;hp=f27e14ea4191c16e52bdc2cd9b5cfd2f0ee329ae;hpb=ecc7fd3c56f482ecb4ea42d2cf83e54f73dfb69a;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index f27e14ea419..46fcdf5e96f 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -1,123 +1,326 @@ -#include "Record.h" -#include "CodeEmitterGen.h" -#include - -void CodeEmitterGen::createEmitter(std::ostream &o) { - std::vector Insts; - - const std::map &Defs = Records.getDefs(); - Record *Inst = Records.getClass("Instruction"); - assert(Inst && "Couldn't find Instruction class!"); - - for (std::map::const_iterator I = Defs.begin(), - E = Defs.end(); I != E; ++I) - if (I->second->isSubClassOf(Inst)) - Insts.push_back(I->second); - - std::string Namespace = "V9::"; - std::string ClassName = "SparcV9CodeEmitter::"; - - //const std::string &Namespace = Inst->getValue("Namespace")->getName(); - o << "unsigned " << ClassName - << "getBinaryCodeForInstr(MachineInstr &MI) {\n" - << " unsigned Value = 0;\n" - << " std::cerr << MI;\n" - << " switch (MI.getOpcode()) {\n"; - for (std::vector::iterator I = Insts.begin(), E = Insts.end(); - I != E; ++I) - { - Record *R = *I; - o << " case " << Namespace << R->getName() << ": {\n" - << " std::cerr << \"Emitting " << R->getName() << "\\n\";\n"; - - const RecordVal *InstVal = R->getValue("Inst"); - Init *InitVal = InstVal->getValue(); - - assert(dynamic_cast(InitVal) && - "Can only handle undefined bits<> types!"); - BitsInit *BI = (BitsInit*)InitVal; - - unsigned Value = 0; - const std::vector &Vals = R->getValues(); - - o << " // prefilling: "; - // Start by filling in fixed values... - for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) { - Value |= B->getValue() << (e-i-1); - o << B->getValue(); - } else { - o << "0"; +//===- CodeEmitterGen.cpp - Code Emitter Generator ------------------------===// +// +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// CodeEmitterGen uses the descriptions of instructions and their fields to +// construct an automated code emitter: a function that, given a MachineInstr, +// returns the (currently, 32-bit unsigned) value of the instruction. +// +//===----------------------------------------------------------------------===// + +#include "CodeGenTarget.h" +#include "llvm/ADT/StringExtras.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" +#include +#include +#include +using namespace llvm; + +namespace { + +class CodeEmitterGen { + RecordKeeper &Records; +public: + CodeEmitterGen(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &o); +private: + int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); + std::string getInstructionCase(Record *R, CodeGenTarget &Target); + void AddCodeToMergeInOperand(Record *R, BitsInit *BI, + const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target); + +}; + +// If the VarBitInit at position 'bit' matches the specified variable then +// return the variable bit position. Otherwise return -1. +int CodeEmitterGen::getVariableBit(const std::string &VarName, + BitsInit *BI, int bit) { + if (VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + if (VarInit *VI = dyn_cast(VBI->getBitVar())) + if (VI->getName() == VarName) + return VBI->getBitNum(); + } else if (VarInit *VI = dyn_cast(BI->getBit(bit))) { + if (VI->getName() == VarName) + return 0; + } + + return -1; +} + +void CodeEmitterGen:: +AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, + unsigned &NumberedOp, + std::set &NamedOpIndices, + std::string &Case, CodeGenTarget &Target) { + CodeGenInstruction &CGI = Target.getInstruction(R); + + // Determine if VarName actually contributes to the Inst encoding. + int bit = BI->getNumBits()-1; + + // Scan for a bit that this contributed to. + for (; bit >= 0; ) { + if (getVariableBit(VarName, BI, bit) != -1) + break; + + --bit; + } + + // If we found no bits, ignore this value, otherwise emit the call to get the + // operand encoding. + if (bit < 0) return; + + // If the operand matches by name, reference according to that + // operand number. Non-matching operands are assumed to be in + // order. + unsigned OpIdx; + if (CGI.Operands.hasOperandNamed(VarName, OpIdx)) { + // Get the machine operand number for the indicated operand. + OpIdx = CGI.Operands[OpIdx].MIOperandNo; + assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && + "Explicitly used operand also marked as not emitted!"); + } else { + unsigned NumberOps = CGI.Operands.size(); + /// If this operand is not supposed to be emitted by the + /// generated emitter, skip it. + while (NumberedOp < NumberOps && + (CGI.Operands.isFlatOperandNotEmitted(NumberedOp) || + (!NamedOpIndices.empty() && NamedOpIndices.count( + CGI.Operands.getSubOperandNumber(NumberedOp).first)))) { + ++NumberedOp; + + if (NumberedOp >= CGI.Operands.back().MIOperandNo + + CGI.Operands.back().MINumOperands) { + errs() << "Too few operands in record " << R->getName() << + " (no match for variable " << VarName << "):\n"; + errs() << *R; + errs() << '\n'; + + return; } } - o << "\n"; - o << " // " << *InstVal << "\n"; - o << " Value = " << Value << "U;\n\n"; + OpIdx = NumberedOp++; + } + + std::pair SO = CGI.Operands.getSubOperandNumber(OpIdx); + std::string &EncoderMethodName = CGI.Operands[SO.first].EncoderMethodName; + + // If the source operand has a custom encoder, use it. This will + // get the encoding for all of the suboperands. + if (!EncoderMethodName.empty()) { + // A custom encoder has all of the information for the + // sub-operands, if there are more than one, so only + // query the encoder once per source operand. + if (SO.second == 0) { + Case += " // op: " + VarName + "\n" + + " op = " + EncoderMethodName + "(MI, " + utostr(OpIdx); + Case += ", Fixups, STI"; + Case += ");\n"; + } + } else { + Case += " // op: " + VarName + "\n" + + " op = getMachineOpValue(MI, MI.getOperand(" + utostr(OpIdx) + ")"; + Case += ", Fixups, STI"; + Case += ");\n"; + } + + for (; bit >= 0; ) { + int varBit = getVariableBit(VarName, BI, bit); + + // If this bit isn't from a variable, skip it. + if (varBit == -1) { + --bit; + continue; + } + + // Figure out the consecutive range of bits covered by this operand, in + // order to generate better encoding code. + int beginInstBit = bit; + int beginVarBit = varBit; + int N = 1; + for (--bit; bit >= 0;) { + varBit = getVariableBit(VarName, BI, bit); + if (varBit == -1 || varBit != (beginVarBit - N)) break; + ++N; + --bit; + } + + uint64_t opMask = ~(uint64_t)0 >> (64-N); + int opShift = beginVarBit - N + 1; + opMask <<= opShift; + opShift = beginInstBit - beginVarBit; - // Loop over all of the fields in the instruction adding in any - // contributions to this value (due to bit references). - // - unsigned op = 0; - std::map OpOrder; + if (opShift > 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " + + itostr(opShift) + ";\n"; + } else if (opShift < 0) { + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " + + itostr(-opShift) + ";\n"; + } else { + Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n"; + } + } +} + + +std::string CodeEmitterGen::getInstructionCase(Record *R, + CodeGenTarget &Target) { + std::string Case; + + BitsInit *BI = R->getValueAsBitsInit("Inst"); + const std::vector &Vals = R->getValues(); + unsigned NumberedOp = 0; + + std::set NamedOpIndices; + // Collect the set of operand indices that might correspond to named + // operand, and skip these when assigning operands based on position. + if (Target.getInstructionSet()-> + getValueAsBit("noNamedPositionallyEncodedOperands")) { + CodeGenInstruction &CGI = Target.getInstruction(R); for (unsigned i = 0, e = Vals.size(); i != e; ++i) { - if (Vals[i].getName() != "Inst" && - !Vals[i].getValue()->isComplete() && - Vals[i].getName() != "annul" && - Vals[i].getName() != "cc" && - Vals[i].getName() != "predict") - { - o << " // op" << op << ": " << Vals[i].getName() << "\n" - << " int64_t op" << op - <<" = getMachineOpValue(MI.getOperand("<= 0; --f) { - if (Vals[f].getPrefix()) { - BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue(); - - // Scan through the field looking for bit initializers of the current - // variable... - for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) { - if (BitInit *BI=dynamic_cast(FieldInitializer->getBit(i))){ - --Offset; - } else if (UnsetInit *UI = - dynamic_cast(FieldInitializer->getBit(i))) { - --Offset; - } else if (VarBitInit *VBI = - dynamic_cast(FieldInitializer->getBit(i))) { - TypedInit *TI = VBI->getVariable(); - if (VarInit *VI = dynamic_cast(TI)) { - o << " Value |= getValueBit(op" << OpOrder[VI->getName()] - << ", " << VBI->getBitNum() - << ")" << " << " << Offset << ";\n"; - --Offset; - } else if (FieldInit *FI = dynamic_cast(TI)) { - // FIXME: implement this! - o << "FIELD INIT not implemented yet!\n"; - } else { - o << "Error: UNIMPLEMENTED\n"; - } - } - } - } else { - if (Vals[f].getName() == "annul" || Vals[f].getName() == "cc" || - Vals[f].getName() == "predict") - --Offset; - } + // Loop over all of the fields in the instruction, determining which are the + // operands to the instruction. + for (unsigned i = 0, e = Vals.size(); i != e; ++i) { + // Ignore fixed fields in the record, we're looking for values like: + // bits<5> RST = { ?, ?, ?, ?, ? }; + if (Vals[i].getPrefix() || Vals[i].getValue()->isComplete()) + continue; + + AddCodeToMergeInOperand(R, BI, Vals[i].getName(), NumberedOp, + NamedOpIndices, Case, Target); + } + + std::string PostEmitter = R->getValueAsString("PostEncoderMethod"); + if (!PostEmitter.empty()) { + Case += " Value = " + PostEmitter + "(MI, Value"; + Case += ", STI"; + Case += ");\n"; + } + + return Case; +} + +void CodeEmitterGen::run(raw_ostream &o) { + CodeGenTarget Target(Records); + std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); + + // For little-endian instruction bit encodings, reverse the bit order + Target.reverseBitsForLittleEndianEncoding(); + + const std::vector &NumberedInstructions = + Target.getInstructionsByEnumValue(); + + // Emit function declaration + o << "uint64_t " << Target.getName(); + o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" + << " SmallVectorImpl &Fixups,\n" + << " const MCSubtargetInfo &STI) const {\n"; + + // Emit instruction base values + o << " static const uint64_t InstBits[] = {\n"; + for (std::vector::const_iterator + IN = NumberedInstructions.begin(), + EN = NumberedInstructions.end(); + IN != EN; ++IN) { + const CodeGenInstruction *CGI = *IN; + Record *R = CGI->TheDef; + + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { + o << " UINT64_C(0),\n"; + continue; } + BitsInit *BI = R->getValueAsBitsInit("Inst"); + + // Start by filling in fixed values. + uint64_t Value = 0; + for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { + if (BitInit *B = dyn_cast(BI->getBit(e-i-1))) + Value |= (uint64_t)B->getValue() << (e-i-1); + } + o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n"; + } + o << " UINT64_C(0)\n };\n"; + + // Map to accumulate all the cases. + std::map > CaseMap; + + // Construct all cases statement for each opcode + for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); + IC != EC; ++IC) { + Record *R = *IC; + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) + continue; + const std::string &InstName = R->getValueAsString("Namespace") + "::" + + R->getName(); + std::string Case = getInstructionCase(R, Target); + + CaseMap[Case].push_back(InstName); + } + + // Emit initial function code + o << " const unsigned opcode = MI.getOpcode();\n" + << " uint64_t Value = InstBits[opcode];\n" + << " uint64_t op = 0;\n" + << " (void)op; // suppress warning\n" + << " switch (opcode) {\n"; + + // Emit each case statement + std::map >::iterator IE, EE; + for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { + const std::string &Case = IE->first; + std::vector &InstList = IE->second; + + for (int i = 0, N = InstList.size(); i < N; i++) { + if (i) o << "\n"; + o << " case " << InstList[i] << ":"; + } + o << " {\n"; + o << Case; o << " break;\n" << " }\n"; } + + // Default case: unhandled opcode o << " default:\n" - << " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n" - << " abort();\n" + << " std::string msg;\n" + << " raw_string_ostream Msg(msg);\n" + << " Msg << \"Not supported instr: \" << MI;\n" + << " report_fatal_error(Msg.str());\n" << " }\n" << " return Value;\n" - << "}\n"; + << "}\n\n"; } + +} // End anonymous namespace + +namespace llvm { + +void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Machine Code Emitter", OS); + CodeEmitterGen(RK).run(OS); +} + +} // End llvm namespace