X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=557a8f4df9abfffb2d583f0ba7c232332b4b44e6;hb=7b2e579546d1ebf49c2e187efab2c76be9e32050;hp=15b35d5d5dbc8a7d875e3b9a7c84709b6f902666;hpb=485c00f7e8153e9d281c4f542593f503d022043c;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 15b35d5d5db..557a8f4df9a 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -16,246 +16,232 @@ #include "CodeEmitterGen.h" #include "CodeGenTarget.h" #include "Record.h" +#include "llvm/ADT/StringExtras.h" #include "llvm/Support/Debug.h" using namespace llvm; -void CodeEmitterGen::emitInstrOpBits(std::ostream &o, - const std::vector &Vals, - std::map &OpOrder, - std::map &OpContinuous) -{ - for (unsigned f = 0, e = Vals.size(); f != e; ++f) { - if (Vals[f].getPrefix()) { - BitsInit *FieldInitializer = (BitsInit*)Vals[f].getValue(); - - // Scan through the field looking for bit initializers of the current - // variable... - for (int i = FieldInitializer->getNumBits()-1; i >= 0; --i) { - Init *I = FieldInitializer->getBit(i); - if (BitInit *BI = dynamic_cast(I)) { - DEBUG(o << " // bit init: f: " << f << ", i: " << i << "\n"); - } else if (UnsetInit *UI = dynamic_cast(I)) { - DEBUG(o << " // unset init: f: " << f << ", i: " << i << "\n"); - } else if (VarBitInit *VBI = dynamic_cast(I)) { - TypedInit *TI = VBI->getVariable(); - if (VarInit *VI = dynamic_cast(TI)) { - // If the bits of the field are laid out consecutively in the - // instruction, then instead of separately ORing in bits, just - // mask and shift the entire field for efficiency. - if (OpContinuous[VI->getName()]) { - // already taken care of in the loop above, thus there is no - // need to individually OR in the bits +void CodeEmitterGen::reverseBits(std::vector &Insts) { + for (std::vector::iterator I = Insts.begin(), E = Insts.end(); + I != E; ++I) { + Record *R = *I; + if (R->getName() == "PHI" || + R->getName() == "INLINEASM" || + R->getName() == "DBG_LABEL" || + R->getName() == "EH_LABEL" || + R->getName() == "GC_LABEL" || + R->getName() == "DECLARE" || + R->getName() == "EXTRACT_SUBREG" || + R->getName() == "INSERT_SUBREG" || + R->getName() == "IMPLICIT_DEF" || + R->getName() == "SUBREG_TO_REG") continue; + + BitsInit *BI = R->getValueAsBitsInit("Inst"); - // for debugging, output the regular version anyway, commented - DEBUG(o << " // Value |= getValueBit(op" - << OpOrder[VI->getName()] << ", " << VBI->getBitNum() - << ")" << " << " << i << ";\n"); - } else { - o << " Value |= getValueBit(op" << OpOrder[VI->getName()] - << ", " << VBI->getBitNum() - << ")" << " << " << i << ";\n"; - } - } else if (FieldInit *FI = dynamic_cast(TI)) { - // FIXME: implement this! - std::cerr << "Error: FieldInit not implemented!\n"; - abort(); - } else { - std::cerr << "Error: unimplemented case in " - << "CodeEmitterGen::emitInstrOpBits()\n"; - abort(); - } - } - } + unsigned numBits = BI->getNumBits(); + BitsInit *NewBI = new BitsInit(numBits); + for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { + unsigned bitSwapIdx = numBits - bit - 1; + Init *OrigBit = BI->getBit(bit); + Init *BitSwap = BI->getBit(bitSwapIdx); + NewBI->setBit(bit, BitSwap); + NewBI->setBit(bitSwapIdx, OrigBit); } + if (numBits % 2) { + unsigned middle = (numBits + 1) / 2; + NewBI->setBit(middle, BI->getBit(middle)); + } + + // Update the bits in reversed order so that emitInstrOpBits will get the + // correct endianness. + R->getValue("Inst")->setValue(NewBI); } } +// If the VarBitInit at position 'bit' matches the specified variable then +// return the variable bit position. Otherwise return -1. +int CodeEmitterGen::getVariableBit(const std::string &VarName, + BitsInit *BI, int bit) { + if (VarBitInit *VBI = dynamic_cast(BI->getBit(bit))) { + TypedInit *TI = VBI->getVariable(); + + if (VarInit *VI = dynamic_cast(TI)) { + if (VI->getName() == VarName) return VBI->getBitNum(); + } + } + + return -1; +} + + void CodeEmitterGen::run(std::ostream &o) { CodeGenTarget Target; std::vector Insts = Records.getAllDerivedDefinitions("Instruction"); + + // For little-endian instruction bit encodings, reverse the bit order + if (Target.isLittleEndianEncoding()) reverseBits(Insts); EmitSourceFileHeader("Machine Code Emitter", o); std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; + + std::vector NumberedInstructions; + Target.getInstructionsByEnumValue(NumberedInstructions); // Emit function declaration o << "unsigned " << Target.getName() << "CodeEmitter::" - << "getBinaryCodeForInstr(MachineInstr &MI) {\n" - << " unsigned Value = 0;\n" - << " DEBUG(std::cerr << MI);\n" - << " switch (MI.getOpcode()) {\n"; - - // Emit a case statement for each opcode - for (std::vector::iterator I = Insts.begin(), E = Insts.end(); - I != E; ++I) { - Record *R = *I; - if (R->getName() == "PHI" || R->getName() == "INLINEASM") continue; + << "getBinaryCodeForInstr(MachineInstr &MI) {\n"; + + // Emit instruction base values + o << " static const unsigned InstBits[] = {\n"; + for (std::vector::iterator + IN = NumberedInstructions.begin(), + EN = NumberedInstructions.end(); + IN != EN; ++IN) { + const CodeGenInstruction *CGI = *IN; + Record *R = CGI->TheDef; - o << " case " << Namespace << R->getName() << ": {\n" - << " DEBUG(std::cerr << \"Emitting " << R->getName() << "\\n\");\n"; - - BitsInit *BI = R->getValueAsBitsInit("Inst"); - - // For little-endian instruction bit encodings, reverse the bit order - if (Target.isLittleEndianEncoding()) { - unsigned numBits = BI->getNumBits(); - BitsInit *NewBI = new BitsInit(numBits); - for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { - unsigned bitSwapIdx = numBits - bit - 1; - Init *OrigBit = BI->getBit(bit); - Init *BitSwap = BI->getBit(bitSwapIdx); - NewBI->setBit(bit, BitSwap); - NewBI->setBit(bitSwapIdx, OrigBit); - } - if (numBits % 2) { - unsigned middle = (numBits + 1) / 2; - NewBI->setBit(middle, BI->getBit(middle)); - } - BI = NewBI; - - // Update the bits in reversed order so that emitInstrOpBits will get the - // correct endianness. - R->getValue("Inst")->setValue(NewBI); + if (IN != NumberedInstructions.begin()) o << ",\n"; + + if (R->getName() == "PHI" || + R->getName() == "INLINEASM" || + R->getName() == "DBG_LABEL" || + R->getName() == "EH_LABEL" || + R->getName() == "GC_LABEL" || + R->getName() == "DECLARE" || + R->getName() == "EXTRACT_SUBREG" || + R->getName() == "INSERT_SUBREG" || + R->getName() == "IMPLICIT_DEF" || + R->getName() == "SUBREG_TO_REG") { + o << " 0U"; + continue; } + + BitsInit *BI = R->getValueAsBitsInit("Inst"); - unsigned Value = 0; - const std::vector &Vals = R->getValues(); - - DEBUG(o << " // prefilling: "); // Start by filling in fixed values... + unsigned Value = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) { Value |= B->getValue() << (e-i-1); - DEBUG(o << B->getValue()); - } else { - DEBUG(o << "0"); } } - DEBUG(o << "\n"); - - DEBUG(o << " // " << *R->getValue("Inst") << "\n"); - o << " Value = " << Value << "U;\n\n"; - + o << " " << Value << "U"; + } + o << "\n };\n"; + + // Map to accumulate all the cases. + std::map > CaseMap; + + // Construct all cases statement for each opcode + for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); + IC != EC; ++IC) { + Record *R = *IC; + const std::string &InstName = R->getName(); + std::string Case(""); + + if (InstName == "PHI" || + InstName == "INLINEASM" || + InstName == "DBG_LABEL"|| + InstName == "EH_LABEL"|| + InstName == "GC_LABEL"|| + InstName == "DECLARE"|| + InstName == "EXTRACT_SUBREG" || + InstName == "INSERT_SUBREG" || + InstName == "IMPLICIT_DEF" || + InstName == "SUBREG_TO_REG") continue; + + BitsInit *BI = R->getValueAsBitsInit("Inst"); + const std::vector &Vals = R->getValues(); + CodeGenInstruction &CGI = Target.getInstruction(InstName); + // Loop over all of the fields in the instruction, determining which are the // operands to the instruction. unsigned op = 0; - std::map OpOrder; - std::map OpContinuous; for (unsigned i = 0, e = Vals.size(); i != e; ++i) { if (!Vals[i].getPrefix() && !Vals[i].getValue()->isComplete()) { // Is the operand continuous? If so, we can just mask and OR it in // instead of doing it bit-by-bit, saving a lot in runtime cost. - BitsInit *InstInit = BI; - int beginBitInVar = -1, endBitInVar = -1; - int beginBitInInst = -1, endBitInInst = -1; - bool continuous = true; - - for (int bit = InstInit->getNumBits()-1; bit >= 0; --bit) { - if (VarBitInit *VBI = - dynamic_cast(InstInit->getBit(bit))) { - TypedInit *TI = VBI->getVariable(); - if (VarInit *VI = dynamic_cast(TI)) { - // only process the current variable - if (VI->getName() != Vals[i].getName()) - continue; - - if (beginBitInVar == -1) - beginBitInVar = VBI->getBitNum(); - - if (endBitInVar == -1) - endBitInVar = VBI->getBitNum(); - else { - if (endBitInVar == (int)VBI->getBitNum() + 1) - endBitInVar = VBI->getBitNum(); - else { - continuous = false; - break; - } - } - - if (beginBitInInst == -1) - beginBitInInst = bit; - if (endBitInInst == -1) - endBitInInst = bit; - else { - if (endBitInInst == bit + 1) - endBitInInst = bit; - else { - continuous = false; - break; - } - } + const std::string &VarName = Vals[i].getName(); + bool gotOp = false; + + for (int bit = BI->getNumBits()-1; bit >= 0; ) { + int varBit = getVariableBit(VarName, BI, bit); + + if (varBit == -1) { + --bit; + } else { + int beginInstBit = bit; + int beginVarBit = varBit; + int N = 1; + + for (--bit; bit >= 0;) { + varBit = getVariableBit(VarName, BI, bit); + if (varBit == -1 || varBit != (beginVarBit - N)) break; + ++N; + --bit; + } - // maintain same distance between bits in field and bits in - // instruction. if the relative distances stay the same - // throughout, - if (beginBitInVar - (int)VBI->getBitNum() != - beginBitInInst - bit) { - continuous = false; - break; - } + if (!gotOp) { + /// If this operand is not supposed to be emitted by the generated + /// emitter, skip it. + while (CGI.isFlatOperandNotEmitted(op)) + ++op; + + Case += " // op: " + VarName + "\n" + + " op = getMachineOpValue(MI, MI.getOperand(" + + utostr(op++) + "));\n"; + gotOp = true; + } + + unsigned opMask = (1 << N) - 1; + int opShift = beginVarBit - N + 1; + opMask <<= opShift; + opShift = beginInstBit - beginVarBit; + + if (opShift > 0) { + Case += " Value |= (op & " + utostr(opMask) + "U) << " + + itostr(opShift) + ";\n"; + } else if (opShift < 0) { + Case += " Value |= (op & " + utostr(opMask) + "U) >> " + + itostr(-opShift) + ";\n"; + } else { + Case += " Value |= op & " + utostr(opMask) + "U;\n"; } } } + } + } - // If we have found no bit in "Inst" which comes from this field, then - // this is not an operand!! - if (beginBitInInst != -1) { - o << " // op" << op << ": " << Vals[i].getName() << "\n" - << " int op" << op - <<" = getMachineOpValue(MI, MI.getOperand("<= 0 && "Negative shift amount in masking!"); - if (endBitInVar != 0) { - o << " op" << OpOrder[Vals[i].getName()] - << " >>= " << endBitInVar << ";\n"; - beginBitInVar -= endBitInVar; - endBitInVar = 0; - } + std::vector &InstList = CaseMap[Case]; + InstList.push_back(InstName); + } - // High mask - o << " op" << OpOrder[Vals[i].getName()] - << " &= (1<<" << beginBitInVar+1 << ") - 1;\n"; - // Shift the value to the correct place (according to place in inst) - assert(endBitInInst >= 0 && "Negative shift amount!"); - if (endBitInInst != 0) - o << " op" << OpOrder[Vals[i].getName()] - << " <<= " << endBitInInst << ";\n"; + // Emit initial function code + o << " const unsigned opcode = MI.getOpcode();\n" + << " unsigned Value = InstBits[opcode];\n" + << " unsigned op;\n" + << " switch (opcode) {\n"; - // Just OR in the result - o << " Value |= op" << OpOrder[Vals[i].getName()] << ";\n"; - } + // Emit each case statement + std::map >::iterator IE, EE; + for (IE = CaseMap.begin(), EE = CaseMap.end(); IE != EE; ++IE) { + const std::string &Case = IE->first; + std::vector &InstList = IE->second; - // otherwise, will be taken care of in the loop below using this - // value: - OpContinuous[Vals[i].getName()] = continuous; - } - } + for (int i = 0, N = InstList.size(); i < N; i++) { + if (i) o << "\n"; + o << " case " << Namespace << InstList[i] << ":"; } - - emitInstrOpBits(o, Vals, OpOrder, OpContinuous); - + o << " {\n"; + o << Case; o << " break;\n" << " }\n"; } // Default case: unhandled opcode o << " default:\n" - << " std::cerr << \"Not supported instr: \" << MI << \"\\n\";\n" + << " cerr << \"Not supported instr: \" << MI << \"\\n\";\n" << " abort();\n" << " }\n" << " return Value;\n"