X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeEmitterGen.cpp;h=c94d384901f0c21d02081448c1df5c9f3fe30a23;hb=86779ee177c11863f74a9aecb445fdd8659557e0;hp=6ee63b8f9500593f20c5770304377825b93b8f3a;hpb=67db883487fca3472fdde51e931657e22d4d0495;p=oota-llvm.git diff --git a/utils/TableGen/CodeEmitterGen.cpp b/utils/TableGen/CodeEmitterGen.cpp index 6ee63b8f950..c94d384901f 100644 --- a/utils/TableGen/CodeEmitterGen.cpp +++ b/utils/TableGen/CodeEmitterGen.cpp @@ -13,12 +13,15 @@ // //===----------------------------------------------------------------------===// -#include "CodeEmitterGen.h" #include "CodeGenTarget.h" -#include "Record.h" #include "llvm/ADT/StringExtras.h" #include "llvm/Support/CommandLine.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" +#include +#include +#include using namespace llvm; // FIXME: Somewhat hackish to use a command line option for this. There should @@ -29,29 +32,55 @@ MCEmitter("mc-emitter", cl::desc("Generate CodeEmitter for use with the MC library."), cl::init(false)); +namespace { + +class CodeEmitterGen { + RecordKeeper &Records; +public: + CodeEmitterGen(RecordKeeper &R) : Records(R) {} + + void run(raw_ostream &o); +private: + void emitMachineOpEmitter(raw_ostream &o, const std::string &Namespace); + void emitGetValueBit(raw_ostream &o, const std::string &Namespace); + void reverseBits(std::vector &Insts); + int getVariableBit(const std::string &VarName, BitsInit *BI, int bit); + std::string getInstructionCase(Record *R, CodeGenTarget &Target); + void AddCodeToMergeInOperand(Record *R, BitsInit *BI, + const std::string &VarName, + unsigned &NumberedOp, + std::string &Case, CodeGenTarget &Target); + +}; + void CodeEmitterGen::reverseBits(std::vector &Insts) { for (std::vector::iterator I = Insts.begin(), E = Insts.end(); I != E; ++I) { Record *R = *I; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; BitsInit *BI = R->getValueAsBitsInit("Inst"); unsigned numBits = BI->getNumBits(); - BitsInit *NewBI = new BitsInit(numBits); + + SmallVector NewBits(numBits); + for (unsigned bit = 0, end = numBits / 2; bit != end; ++bit) { unsigned bitSwapIdx = numBits - bit - 1; Init *OrigBit = BI->getBit(bit); Init *BitSwap = BI->getBit(bitSwapIdx); - NewBI->setBit(bit, BitSwap); - NewBI->setBit(bitSwapIdx, OrigBit); + NewBits[bit] = BitSwap; + NewBits[bitSwapIdx] = OrigBit; } if (numBits % 2) { unsigned middle = (numBits + 1) / 2; - NewBI->setBit(middle, BI->getBit(middle)); + NewBits[middle] = BI->getBit(middle); } + BitsInit *NewBI = BitsInit::get(NewBits); + // Update the bits in reversed order so that emitInstrOpBits will get the // correct endianness. R->getValue("Inst")->setValue(NewBI); @@ -62,10 +91,14 @@ void CodeEmitterGen::reverseBits(std::vector &Insts) { // return the variable bit position. Otherwise return -1. int CodeEmitterGen::getVariableBit(const std::string &VarName, BitsInit *BI, int bit) { - if (VarBitInit *VBI = dynamic_cast(BI->getBit(bit))) - if (VarInit *VI = dynamic_cast(VBI->getVariable())) + if (VarBitInit *VBI = dyn_cast(BI->getBit(bit))) { + if (VarInit *VI = dyn_cast(VBI->getBitVar())) if (VI->getName() == VarName) return VBI->getBitNum(); + } else if (VarInit *VI = dyn_cast(BI->getBit(bit))) { + if (VI->getName() == VarName) + return 0; + } return -1; } @@ -101,10 +134,13 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, assert(!CGI.Operands.isFlatOperandNotEmitted(OpIdx) && "Explicitly used operand also marked as not emitted!"); } else { + unsigned NumberOps = CGI.Operands.size(); /// If this operand is not supposed to be emitted by the /// generated emitter, skip it. - while (CGI.Operands.isFlatOperandNotEmitted(NumberedOp)) + while (NumberedOp < NumberOps && + CGI.Operands.isFlatOperandNotEmitted(NumberedOp)) ++NumberedOp; + OpIdx = NumberedOp++; } @@ -141,7 +177,7 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, continue; } - // Figure out the consequtive range of bits covered by this operand, in + // Figure out the consecutive range of bits covered by this operand, in // order to generate better encoding code. int beginInstBit = bit; int beginVarBit = varBit; @@ -153,19 +189,19 @@ AddCodeToMergeInOperand(Record *R, BitsInit *BI, const std::string &VarName, --bit; } - unsigned opMask = ~0U >> (32-N); + uint64_t opMask = ~(uint64_t)0 >> (64-N); int opShift = beginVarBit - N + 1; opMask <<= opShift; opShift = beginInstBit - beginVarBit; if (opShift > 0) { - Case += " Value |= (op & " + utostr(opMask) + "U) << " + + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) << " + itostr(opShift) + ";\n"; } else if (opShift < 0) { - Case += " Value |= (op & " + utostr(opMask) + "U) >> " + + Case += " Value |= (op & UINT64_C(" + utostr(opMask) + ")) >> " + itostr(-opShift) + ";\n"; } else { - Case += " Value |= op & " + utostr(opMask) + "U;\n"; + Case += " Value |= op & UINT64_C(" + utostr(opMask) + ");\n"; } } } @@ -204,14 +240,12 @@ void CodeEmitterGen::run(raw_ostream &o) { // For little-endian instruction bit encodings, reverse the bit order if (Target.isLittleEndianEncoding()) reverseBits(Insts); - EmitSourceFileHeader("Machine Code Emitter", o); - std::string Namespace = Insts[0]->getValueAsString("Namespace") + "::"; const std::vector &NumberedInstructions = Target.getInstructionsByEnumValue(); // Emit function declaration - o << "unsigned " << Target.getName(); + o << "uint64_t " << Target.getName(); if (MCEmitter) o << "MCCodeEmitter::getBinaryCodeForInstr(const MCInst &MI,\n" << " SmallVectorImpl &Fixups) const {\n"; @@ -219,7 +253,7 @@ void CodeEmitterGen::run(raw_ostream &o) { o << "CodeEmitter::getBinaryCodeForInstr(const MachineInstr &MI) const {\n"; // Emit instruction base values - o << " static const unsigned InstBits[] = {\n"; + o << " static const uint64_t InstBits[] = {\n"; for (std::vector::const_iterator IN = NumberedInstructions.begin(), EN = NumberedInstructions.end(); @@ -227,22 +261,23 @@ void CodeEmitterGen::run(raw_ostream &o) { const CodeGenInstruction *CGI = *IN; Record *R = CGI->TheDef; - if (R->getValueAsString("Namespace") == "TargetOpcode") { - o << " 0U,\n"; + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) { + o << " UINT64_C(0),\n"; continue; } BitsInit *BI = R->getValueAsBitsInit("Inst"); // Start by filling in fixed values. - unsigned Value = 0; + uint64_t Value = 0; for (unsigned i = 0, e = BI->getNumBits(); i != e; ++i) { - if (BitInit *B = dynamic_cast(BI->getBit(e-i-1))) - Value |= B->getValue() << (e-i-1); + if (BitInit *B = dyn_cast(BI->getBit(e-i-1))) + Value |= (uint64_t)B->getValue() << (e-i-1); } - o << " " << Value << "U," << '\t' << "// " << R->getName() << "\n"; + o << " UINT64_C(" << Value << ")," << '\t' << "// " << R->getName() << "\n"; } - o << " 0U\n };\n"; + o << " UINT64_C(0)\n };\n"; // Map to accumulate all the cases. std::map > CaseMap; @@ -251,9 +286,11 @@ void CodeEmitterGen::run(raw_ostream &o) { for (std::vector::iterator IC = Insts.begin(), EC = Insts.end(); IC != EC; ++IC) { Record *R = *IC; - if (R->getValueAsString("Namespace") == "TargetOpcode") + if (R->getValueAsString("Namespace") == "TargetOpcode" || + R->getValueAsBit("isPseudo")) continue; - const std::string &InstName = R->getName(); + const std::string &InstName = R->getValueAsString("Namespace") + "::" + + R->getName(); std::string Case = getInstructionCase(R, Target); CaseMap[Case].push_back(InstName); @@ -261,9 +298,9 @@ void CodeEmitterGen::run(raw_ostream &o) { // Emit initial function code o << " const unsigned opcode = MI.getOpcode();\n" - << " unsigned Value = InstBits[opcode];\n" - << " unsigned op = 0;\n" - << " op = op; // suppress warning\n" + << " uint64_t Value = InstBits[opcode];\n" + << " uint64_t op = 0;\n" + << " (void)op; // suppress warning\n" << " switch (opcode) {\n"; // Emit each case statement @@ -274,7 +311,7 @@ void CodeEmitterGen::run(raw_ostream &o) { for (int i = 0, N = InstList.size(); i < N; i++) { if (i) o << "\n"; - o << " case " << Namespace << InstList[i] << ":"; + o << " case " << InstList[i] << ":"; } o << " {\n"; o << Case; @@ -292,3 +329,14 @@ void CodeEmitterGen::run(raw_ostream &o) { << " return Value;\n" << "}\n\n"; } + +} // End anonymous namespace + +namespace llvm { + +void EmitCodeEmitter(RecordKeeper &RK, raw_ostream &OS) { + emitSourceFileHeader("Machine Code Emitter", OS); + CodeEmitterGen(RK).run(OS); +} + +} // End llvm namespace