X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeGenRegisters.h;h=f9edc6553ac9d80db8cda370b74846a4b15a6bab;hb=36cd99caccbc62366b30c47fefba6c4832f0b2be;hp=491a91667a05aa51b6636dcb9740ffc085651c18;hpb=31d938a6b1173c642f975d78417459d4d8cd3677;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenRegisters.h b/utils/TableGen/CodeGenRegisters.h index 491a91667a0..f9edc6553ac 100644 --- a/utils/TableGen/CodeGenRegisters.h +++ b/utils/TableGen/CodeGenRegisters.h @@ -16,17 +16,17 @@ #define CODEGEN_REGISTERS_H #include "SetTheory.h" -#include "llvm/TableGen/Record.h" -#include "llvm/CodeGen/ValueTypes.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/ADT/BitVector.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/SetVector.h" +#include "llvm/CodeGen/ValueTypes.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/TableGen/Record.h" #include #include -#include #include +#include #include namespace llvm { @@ -35,14 +35,24 @@ namespace llvm { /// CodeGenSubRegIndex - Represents a sub-register index. class CodeGenSubRegIndex { Record *const TheDef; + std::string Name; + std::string Namespace; public: + uint16_t Size; + uint16_t Offset; const unsigned EnumValue; + unsigned LaneMask; + + // Are all super-registers containing this SubRegIndex covered by their + // sub-registers? + bool AllSuperRegsCovered; CodeGenSubRegIndex(Record *R, unsigned Enum); + CodeGenSubRegIndex(StringRef N, StringRef Nspace, unsigned Enum); - const std::string &getName() const; - std::string getNamespace() const; + const std::string &getName() const { return Name; } + const std::string &getNamespace() const { return Namespace; } std::string getQualifiedName() const; // Order CodeGenSubRegIndex pointers by EnumValue. @@ -71,18 +81,27 @@ namespace llvm { assert(A && B); std::pair Ins = Composed.insert(std::make_pair(A, B)); + // Synthetic subreg indices that aren't contiguous (for instance ARM + // register tuples) don't have a bit range, so it's OK to let + // B->Offset == -1. For the other cases, accumulate the offset and set + // the size here. Only do so if there is no offset yet though. + if ((Offset != (uint16_t)-1 && A->Offset != (uint16_t)-1) && + (B->Offset == (uint16_t)-1)) { + B->Offset = Offset + A->Offset; + B->Size = A->Size; + } return (Ins.second || Ins.first->second == B) ? 0 : Ins.first->second; } // Update the composite maps of components specified in 'ComposedOf'. void updateComponents(CodeGenRegBank&); - // Clean out redundant composite mappings. - void cleanComposites(); - // Return the map of composites. const CompMap &getComposites() const { return Composed; } + // Compute LaneMask from Composed. Return LaneMask. + unsigned computeLaneMask(); + private: CompMap Composed; }; @@ -162,10 +181,18 @@ namespace llvm { // List of register units in ascending order. typedef SmallVector RegUnitList; + // How many entries in RegUnitList are native? + unsigned NumNativeRegUnits; + // Get the list of register units. - // This is only valid after getSubRegs() completes. + // This is only valid after computeSubRegs() completes. const RegUnitList &getRegUnits() const { return RegUnits; } + // Get the native register units. This is a prefix of getRegUnits(). + ArrayRef getNativeRegUnits() const { + return makeArrayRef(RegUnits).slice(0, NumNativeRegUnits); + } + // Inherit register units from subregisters. // Return true if the RegUnits changed. bool inheritRegUnits(CodeGenRegBank &RegBank); @@ -246,7 +273,7 @@ namespace llvm { public: unsigned EnumValue; std::string Namespace; - std::vector VTs; + SmallVector VTs; unsigned SpillSize; unsigned SpillAlignment; int CopyCost; @@ -259,7 +286,7 @@ namespace llvm { const std::string &getName() const { return Name; } std::string getQualifiedName() const; - const std::vector &getValueTypes() const {return VTs;} + ArrayRef getValueTypes() const {return VTs;} unsigned getNumValueTypes() const { return VTs.size(); } MVT::SimpleValueType getValueTypeNum(unsigned VTNum) const { @@ -365,12 +392,41 @@ namespace llvm { }; // Create a non-user defined register class. - CodeGenRegisterClass(StringRef Name, Key Props); + CodeGenRegisterClass(CodeGenRegBank&, StringRef Name, Key Props); // Called by CodeGenRegBank::CodeGenRegBank(). static void computeSubClasses(CodeGenRegBank&); }; + // Register units are used to model interference and register pressure. + // Every register is assigned one or more register units such that two + // registers overlap if and only if they have a register unit in common. + // + // Normally, one register unit is created per leaf register. Non-leaf + // registers inherit the units of their sub-registers. + struct RegUnit { + // Weight assigned to this RegUnit for estimating register pressure. + // This is useful when equalizing weights in register classes with mixed + // register topologies. + unsigned Weight; + + // Each native RegUnit corresponds to one or two root registers. The full + // set of registers containing this unit can be computed as the union of + // these two registers and their super-registers. + const CodeGenRegister *Roots[2]; + + // Index into RegClassUnitSets where we can find the list of UnitSets that + // contain this unit. + unsigned RegClassUnitSetsIdx; + + RegUnit() : Weight(0), RegClassUnitSetsIdx(0) { Roots[0] = Roots[1] = 0; } + + ArrayRef getRoots() const { + assert(!(Roots[1] && !Roots[0]) && "Invalid roots array"); + return makeArrayRef(Roots, !!Roots[0] + !!Roots[1]); + } + }; + // Each RegUnitSet is a sorted vector with a name. struct RegUnitSet { typedef std::vector::const_iterator iterator; @@ -386,13 +442,13 @@ namespace llvm { // CodeGenRegBank - Represent a target's registers and the relations between // them. class CodeGenRegBank { - RecordKeeper &Records; SetTheory Sets; // SubRegIndices. std::vector SubRegIndices; DenseMap Def2SubRegIdx; - unsigned NumNamedIndices; + + CodeGenSubRegIndex *createSubRegIndex(StringRef Name, StringRef NameSpace); typedef std::map, CodeGenSubRegIndex*> ConcatIdxMap; @@ -400,15 +456,14 @@ namespace llvm { // Registers. std::vector Registers; + StringMap RegistersByName; DenseMap Def2Reg; unsigned NumNativeRegUnits; - unsigned NumRegUnits; // # native + adopted register units. std::map TopoSigs; - // Map each register unit to a weight (for register pressure). - // Includes native and adopted register units. - std::vector RegUnitWeights; + // Includes native (0..NumNativeRegUnits-1) and adopted register units. + SmallVector RegUnits; // Register classes. std::vector RegClasses; @@ -423,6 +478,10 @@ namespace llvm { // Map RegisterClass index to the index of the RegUnitSet that contains the // class's units and any inferred RegUnit supersets. + // + // NOTE: This could grow beyond the number of register classes when we map + // register units to lists of unit sets. If the list of unit sets does not + // already exist for a register class, we create a new entry in this vector. std::vector > RegClassUnitSets; // Add RC to *2RC maps. @@ -452,6 +511,9 @@ namespace llvm { // Populate the Composite map from sub-register relationships. void computeComposites(); + // Compute a lane mask for each sub-register index. + void computeSubRegIndexLaneMasks(); + public: CodeGenRegBank(RecordKeeper&); @@ -461,7 +523,6 @@ namespace llvm { // in the .td files. The rest are synthesized such that all sub-registers // have a unique name. ArrayRef getSubRegIndices() { return SubRegIndices; } - unsigned getNumNamedIndices() { return NumNamedIndices; } // Find a SubRegIndex form its Record def. CodeGenSubRegIndex *getSubRegIdx(Record*); @@ -482,6 +543,9 @@ namespace llvm { } const std::vector &getRegisters() { return Registers; } + const StringMap &getRegistersByName() { + return RegistersByName; + } // Find a register from its Record def. CodeGenRegister *getReg(Record*); @@ -504,15 +568,21 @@ namespace llvm { return TopoSigs.insert(std::make_pair(Id, TopoSigs.size())).first->second; } + // Create a native register unit that is associated with one or two root + // registers. + unsigned newRegUnit(CodeGenRegister *R0, CodeGenRegister *R1 = 0) { + RegUnits.resize(RegUnits.size() + 1); + RegUnits.back().Roots[0] = R0; + RegUnits.back().Roots[1] = R1; + return RegUnits.size() - 1; + } + // Create a new non-native register unit that can be adopted by a register // to increase its pressure. Note that NumNativeRegUnits is not increased. unsigned newRegUnit(unsigned Weight) { - if (!RegUnitWeights.empty()) { - assert(Weight && "should only add allocatable units"); - RegUnitWeights.resize(NumRegUnits+1); - RegUnitWeights[NumRegUnits] = Weight; - } - return NumRegUnits++; + RegUnits.resize(RegUnits.size() + 1); + RegUnits.back().Weight = Weight; + return RegUnits.size() - 1; } // Native units are the singular unit of a leaf register. Register aliasing @@ -522,6 +592,13 @@ namespace llvm { return RUID < NumNativeRegUnits; } + unsigned getNumNativeRegUnits() const { + return NumNativeRegUnits; + } + + RegUnit &getRegUnit(unsigned RUID) { return RegUnits[RUID]; } + const RegUnit &getRegUnit(unsigned RUID) const { return RegUnits[RUID]; } + ArrayRef getRegClasses() const { return RegClasses; } @@ -536,23 +613,18 @@ namespace llvm { /// return the superclass. Otherwise return null. const CodeGenRegisterClass* getRegClassForRegister(Record *R); - // Get a register unit's weight. Zero for unallocatable registers. - unsigned getRegUnitWeight(unsigned RUID) const { - return RegUnitWeights[RUID]; - } - // Get the sum of unit weights. unsigned getRegUnitSetWeight(const std::vector &Units) const { unsigned Weight = 0; for (std::vector::const_iterator I = Units.begin(), E = Units.end(); I != E; ++I) - Weight += getRegUnitWeight(*I); + Weight += getRegUnit(*I).Weight; return Weight; } // Increase a RegUnitWeight. void increaseRegUnitWeight(unsigned RUID, unsigned Inc) { - RegUnitWeights[RUID] += Inc; + getRegUnit(RUID).Weight += Inc; } // Get the number of register pressure dimensions. @@ -563,6 +635,13 @@ namespace llvm { return RegUnitSets[Idx]; } + // The number of pressure set lists may be larget than the number of + // register classes if some register units appeared in a list of sets that + // did not correspond to an existing register class. + unsigned getNumRegClassPressureSetLists() const { + return RegClassUnitSets.size(); + } + // Get a list of pressure set IDs for a register class. Liveness of a // register in this class impacts each pressure set in this list by the // weight of the register. An exact solution requires all registers in a @@ -574,15 +653,6 @@ namespace llvm { // Computed derived records such as missing sub-register indices. void computeDerivedInfo(); - // Compute full overlap sets for every register. These sets include the - // rarely used aliases that are neither sub nor super-registers. - // - // Map[R1].count(R2) is reflexive and symmetric, but not transitive. - // - // If R1 is a sub-register of R2, Map[R1] is a subset of Map[R2]. - void computeOverlaps(std::map &Map); - // Compute the set of registers completely covered by the registers in Regs. // The returned BitVector will have a bit set for each register in Regs, // all sub-registers, and all super-registers that are covered by the @@ -591,6 +661,11 @@ namespace llvm { // This is used to compute the mask of call-preserved registers from a list // of callee-saves. BitVector computeCoveredRegisters(ArrayRef Regs); + + // Bit mask of lanes that cover their registers. A sub-register index whose + // LaneMask is contained in CoveringLanes will be completely covered by + // another sub-register with the same or larger lane mask. + unsigned CoveringLanes; }; }