X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeGenSchedule.h;h=e5241b9d5fda67d12716ecd7157ee2cff5ffc295;hb=47f0e3f434e2e43f951c3a826c40906cb15b7285;hp=5e8b711fcbb411f5044499972bfa2f4fc81bd86a;hpb=48605c340614fc1fb2ae1d975fc565a4188182e0;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenSchedule.h b/utils/TableGen/CodeGenSchedule.h index 5e8b711fcbb..e5241b9d5fd 100644 --- a/utils/TableGen/CodeGenSchedule.h +++ b/utils/TableGen/CodeGenSchedule.h @@ -7,18 +7,19 @@ // //===----------------------------------------------------------------------===// // -// This file defines structures to encapsulate the machine model as decribed in +// This file defines structures to encapsulate the machine model as described in // the target description. // //===----------------------------------------------------------------------===// -#ifndef CODEGEN_SCHEDULE_H -#define CODEGEN_SCHEDULE_H +#ifndef LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H +#define LLVM_UTILS_TABLEGEN_CODEGENSCHEDULE_H -#include "llvm/TableGen/Record.h" -#include "llvm/Support/ErrorHandling.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/StringMap.h" +#include "llvm/Support/ErrorHandling.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/SetTheory.h" namespace llvm { @@ -43,17 +44,24 @@ void splitSchedReadWrites(const RecVec &RWDefs, /// IsVariadic controls whether the variants are expanded into multiple operands /// or a sequence of writes on one operand. struct CodeGenSchedRW { + unsigned Index; std::string Name; Record *TheDef; + bool IsRead; + bool IsAlias; bool HasVariants; bool IsVariadic; bool IsSequence; IdxVec Sequence; + RecVec Aliases; - CodeGenSchedRW(): TheDef(0), HasVariants(false), IsVariadic(false), - IsSequence(false) {} - CodeGenSchedRW(Record *Def): TheDef(Def), IsVariadic(false) { + CodeGenSchedRW() + : Index(0), TheDef(nullptr), IsRead(false), IsAlias(false), + HasVariants(false), IsVariadic(false), IsSequence(false) {} + CodeGenSchedRW(unsigned Idx, Record *Def) + : Index(Idx), TheDef(Def), IsAlias(false), IsVariadic(false) { Name = Def->getName(); + IsRead = Def->isSubClassOf("SchedRead"); HasVariants = Def->isSubClassOf("SchedVariant"); if (HasVariants) IsVariadic = Def->getValueAsBit("Variadic"); @@ -64,9 +72,10 @@ struct CodeGenSchedRW { IsSequence = Def->isSubClassOf("WriteSequence"); } - CodeGenSchedRW(const IdxVec &Seq, const std::string &Name): - Name(Name), TheDef(0), HasVariants(false), IsVariadic(false), - IsSequence(true), Sequence(Seq) { + CodeGenSchedRW(unsigned Idx, bool Read, const IdxVec &Seq, + const std::string &Name) + : Index(Idx), Name(Name), TheDef(nullptr), IsRead(Read), IsAlias(false), + HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) { assert(Sequence.size() > 1 && "implied sequence needs >1 RWs"); } @@ -75,6 +84,7 @@ struct CodeGenSchedRW { assert((!IsVariadic || HasVariants) && "Variadic write needs variants"); assert((!IsSequence || !HasVariants) && "Sequence can't have variant"); assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty"); + assert((!IsAlias || Aliases.empty()) && "Alias cannot have aliases"); return TheDef || !Sequence.empty(); } @@ -83,6 +93,13 @@ struct CodeGenSchedRW { #endif }; +/// Represent a transition between SchedClasses induced by SchedVariant. +struct CodeGenSchedTransition { + unsigned ToClassIdx; + IdxVec ProcIndices; + RecVec PredTerm; +}; + /// Scheduling class. /// /// Each instruction description will be mapped to a scheduling class. There are @@ -108,6 +125,7 @@ struct CodeGenSchedRW { /// itinerary class. Each inherits the processor index from the ItinRW record /// that mapped the itinerary class to the variant Writes or Reads. struct CodeGenSchedClass { + unsigned Index; std::string Name; Record *ItinClassDef; @@ -116,16 +134,24 @@ struct CodeGenSchedClass { // Sorted list of ProcIdx, where ProcIdx==0 implies any processor. IdxVec ProcIndices; - // InstReadWrite records associated with this class. Any Instrs that the - // definitions refer to that are not mapped to this class should be ignored. + std::vector Transitions; + + // InstRW records associated with this class. These records may refer to an + // Instruction no longer mapped to this class by InstrClassMap. These + // Instructions should be ignored by this class because they have been split + // off to join another inferred class. RecVec InstRWs; - CodeGenSchedClass(): ItinClassDef(0) {} - CodeGenSchedClass(Record *rec): ItinClassDef(rec) { - Name = rec->getName(); - ProcIndices.push_back(0); + CodeGenSchedClass(): Index(0), ItinClassDef(nullptr) {} + + bool isKeyEqual(Record *IC, const IdxVec &W, const IdxVec &R) { + return ItinClassDef == IC && Writes == W && Reads == R; } + // Is this class generated from a variants if existing classes? Instructions + // are never mapped directly to inferred scheduling classes. + bool isInferred() const { return !ItinClassDef; } + #ifndef NDEBUG void dump(const CodeGenSchedModels *SchedModels) const; #endif @@ -136,7 +162,7 @@ struct CodeGenSchedClass { // ModelName is a unique name used to name an instantiation of MCSchedModel. // // ModelDef is NULL for inferred Models. This happens when a processor defines -// an itinerary but no machine model. If the processer defines neither a machine +// an itinerary but no machine model. If the processor defines neither a machine // model nor itinerary, then ModelDef remains pointing to NoModel. NoModel has // the special "NoModel" field set to true. // @@ -162,10 +188,28 @@ struct CodeGenProcModel { // This list is empty if no ItinRW refers to this Processor. RecVec ItinRWDefs; + // All read/write resources associated with this processor. + RecVec WriteResDefs; + RecVec ReadAdvanceDefs; + + // Per-operand machine model resources associated with this processor. + RecVec ProcResourceDefs; + RecVec ProcResGroupDefs; + CodeGenProcModel(unsigned Idx, const std::string &Name, Record *MDef, Record *IDef) : Index(Idx), ModelName(Name), ModelDef(MDef), ItinsDef(IDef) {} + bool hasItineraries() const { + return !ItinsDef->getValueAsListOfDefs("IID").empty(); + } + + bool hasInstrSchedModel() const { + return !WriteResDefs.empty() || !ItinRWDefs.empty(); + } + + unsigned getProcResourceIdx(Record *PRDef) const; + #ifndef NDEBUG void dump() const; #endif @@ -176,6 +220,9 @@ class CodeGenSchedModels { RecordKeeper &Records; const CodeGenTarget &Target; + // Map dag expressions to Instruction lists. + SetTheory Sets; + // List of unique processor models. std::vector ProcModels; @@ -190,30 +237,39 @@ class CodeGenSchedModels { // List of unique SchedClasses. std::vector SchedClasses; - // Map SchedClass name to itinerary index. - // These are either explicit itinerary classes or classes implied by - // instruction definitions with SchedReadWrite lists. - StringMap SchedClassIdxMap; - - // SchedClass indices 1 up to and including NumItineraryClasses identify - // itinerary classes that are explicitly used for this target's instruction - // definitions. NoItinerary always has index 0 regardless of whether it is - // explicitly referenced. - // - // Any implied SchedClass has an index greater than NumItineraryClasses. - unsigned NumItineraryClasses; - // Any inferred SchedClass has an index greater than NumInstrSchedClassses. unsigned NumInstrSchedClasses; - // Map Instruction to SchedClass index. Only for Instructions mentioned in - // OpReadWrites. + // Map each instruction to its unique SchedClass index considering the + // combination of it's itinerary class, SchedRW list, and InstRW records. typedef DenseMap InstClassMapTy; InstClassMapTy InstrClassMap; public: CodeGenSchedModels(RecordKeeper& RK, const CodeGenTarget &TGT); + // iterator access to the scheduling classes. + typedef std::vector::iterator class_iterator; + typedef std::vector::const_iterator const_class_iterator; + class_iterator classes_begin() { return SchedClasses.begin(); } + const_class_iterator classes_begin() const { return SchedClasses.begin(); } + class_iterator classes_end() { return SchedClasses.end(); } + const_class_iterator classes_end() const { return SchedClasses.end(); } + iterator_range classes() { + return iterator_range(classes_begin(), classes_end()); + } + iterator_range classes() const { + return iterator_range(classes_begin(), classes_end()); + } + iterator_range explicit_classes() { + return iterator_range( + classes_begin(), classes_begin() + NumInstrSchedClasses); + } + iterator_range explicit_classes() const { + return iterator_range( + classes_begin(), classes_begin() + NumInstrSchedClasses); + } + Record *getModelOrItinDef(Record *ProcDef) const { Record *ModelDef = ProcDef->getValueAsDef("SchedModel"); Record *ItinsDef = ProcDef->getValueAsDef("ProcItin"); @@ -232,17 +288,23 @@ public: return ProcModels[I->second]; } - const CodeGenProcModel &getProcModel(Record *ModelDef) const { + CodeGenProcModel &getProcModel(Record *ModelDef) { ProcModelMapTy::const_iterator I = ProcModelMap.find(ModelDef); assert(I != ProcModelMap.end() && "missing machine model"); return ProcModels[I->second]; } + const CodeGenProcModel &getProcModel(Record *ModelDef) const { + return const_cast(this)->getProcModel(ModelDef); + } // Iterate over the unique processor models. typedef std::vector::const_iterator ProcIter; ProcIter procModelBegin() const { return ProcModels.begin(); } ProcIter procModelEnd() const { return ProcModels.end(); } + // Return true if any processors have itineraries. + bool hasItineraries() const; + // Get a SchedWrite from its index. const CodeGenSchedRW &getSchedWrite(unsigned Idx) const { assert(Idx < SchedWrites.size() && "bad SchedWrite index"); @@ -259,18 +321,20 @@ public: const CodeGenSchedRW &getSchedRW(unsigned Idx, bool IsRead) const { return IsRead ? getSchedRead(Idx) : getSchedWrite(Idx); } + CodeGenSchedRW &getSchedRW(Record *Def) { + bool IsRead = Def->isSubClassOf("SchedRead"); + unsigned Idx = getSchedRWIdx(Def, IsRead); + return const_cast( + IsRead ? getSchedRead(Idx) : getSchedWrite(Idx)); + } + const CodeGenSchedRW &getSchedRW(Record*Def) const { + return const_cast(*this).getSchedRW(Def); + } unsigned getSchedRWIdx(Record *Def, bool IsRead, unsigned After = 0) const; - // Check if any instructions are assigned to an explicit itinerary class other - // than NoItinerary. - bool hasItineraryClasses() const { return NumItineraryClasses > 0; } - - // Return the number of itinerary classes in use by this target's instruction - // descriptions, not including "NoItinerary". - unsigned numItineraryClasses() const { - return NumItineraryClasses; - } + // Return true if the given write record is referenced by a ReadAdvance. + bool hasReadOfWrite(Record *WriteDef) const; // Get a SchedClass from its index. CodeGenSchedClass &getSchedClass(unsigned Idx) { @@ -282,39 +346,34 @@ public: return SchedClasses[Idx]; } - // Get an itinerary class's index. Value indices are '0' for NoItinerary up to - // and including numItineraryClasses(). - unsigned getItinClassIdx(Record *ItinDef) const { - assert(SchedClassIdxMap.count(ItinDef->getName()) && "missing ItinClass"); - unsigned Idx = SchedClassIdxMap.lookup(ItinDef->getName()); - assert(Idx <= NumItineraryClasses && "bad ItinClass index"); - return Idx; - } - // Get the SchedClass index for an instruction. Instructions with no // itinerary, no SchedReadWrites, and no InstrReadWrites references return 0 // for NoItinerary. unsigned getSchedClassIdx(const CodeGenInstruction &Inst) const; - unsigned getSchedClassIdx(const RecVec &RWDefs) const; - - unsigned getSchedClassIdxForItin(const Record *ItinDef) { - return SchedClassIdxMap[ItinDef->getName()]; - } - typedef std::vector::const_iterator SchedClassIter; SchedClassIter schedClassBegin() const { return SchedClasses.begin(); } SchedClassIter schedClassEnd() const { return SchedClasses.end(); } + unsigned numInstrSchedClasses() const { return NumInstrSchedClasses; } + void findRWs(const RecVec &RWDefs, IdxVec &Writes, IdxVec &Reads) const; void findRWs(const RecVec &RWDefs, IdxVec &RWs, bool IsRead) const; + void expandRWSequence(unsigned RWIdx, IdxVec &RWSeq, bool IsRead) const; + void expandRWSeqForProc(unsigned RWIdx, IdxVec &RWSeq, bool IsRead, + const CodeGenProcModel &ProcModel) const; - unsigned addSchedClass(const IdxVec &OperWrites, const IdxVec &OperReads, - const IdxVec &ProcIndices); + unsigned addSchedClass(Record *ItinDef, const IdxVec &OperWrites, + const IdxVec &OperReads, const IdxVec &ProcIndices); unsigned findOrInsertRW(ArrayRef Seq, bool IsRead); - unsigned findSchedClassIdx(const IdxVec &Writes, const IdxVec &Reads) const; + unsigned findSchedClassIdx(Record *ItinClassDef, + const IdxVec &Writes, + const IdxVec &Reads) const; + + Record *findProcResUnits(Record *ProcResKind, + const CodeGenProcModel &PM) const; private: void collectProcModels(); @@ -329,7 +388,8 @@ private: void collectSchedClasses(); - std::string createSchedClassName(const IdxVec &OperWrites, + std::string createSchedClassName(Record *ItinClassDef, + const IdxVec &OperWrites, const IdxVec &OperReads); std::string createSchedClassName(const RecVec &InstDefs); void createInstRWClass(Record *InstRWDef); @@ -337,6 +397,32 @@ private: void collectProcItins(); void collectProcItinRW(); + + void inferSchedClasses(); + + void inferFromRW(const IdxVec &OperWrites, const IdxVec &OperReads, + unsigned FromClassIdx, const IdxVec &ProcIndices); + void inferFromItinClass(Record *ItinClassDef, unsigned FromClassIdx); + void inferFromInstRWs(unsigned SCIdx); + + bool hasSuperGroup(RecVec &SubUnits, CodeGenProcModel &PM); + void verifyProcResourceGroups(CodeGenProcModel &PM); + + void collectProcResources(); + + void collectItinProcResources(Record *ItinClassDef); + + void collectRWResources(unsigned RWIdx, bool IsRead, + const IdxVec &ProcIndices); + + void collectRWResources(const IdxVec &Writes, const IdxVec &Reads, + const IdxVec &ProcIndices); + + void addProcResource(Record *ProcResourceKind, CodeGenProcModel &PM); + + void addWriteRes(Record *ProcWriteResDef, unsigned PIdx); + + void addReadAdvance(Record *ProcReadAdvanceDef, unsigned PIdx); }; } // namespace llvm