X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeGenTarget.h;h=24b38514260c3b4c5b87b7234dc65b90a600e69f;hb=47f0e3f434e2e43f951c3a826c40906cb15b7285;hp=4e041548f5f1413ff6c846e29f7d55da232de947;hpb=510207cb1e7427df711ac85002cab622f67bdf7c;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h index 4e041548f5f..24b38514260 100644 --- a/utils/TableGen/CodeGenTarget.h +++ b/utils/TableGen/CodeGenTarget.h @@ -9,23 +9,24 @@ // // This file defines wrappers for the Target class and related global // functionality. This makes it easier to access the data and provides a single -// place that needs to check it for validity. All of these classes throw -// exceptions on error conditions. +// place that needs to check it for validity. All of these classes abort +// on error conditions. // //===----------------------------------------------------------------------===// -#ifndef CODEGEN_TARGET_H -#define CODEGEN_TARGET_H +#ifndef LLVM_UTILS_TABLEGEN_CODEGENTARGET_H +#define LLVM_UTILS_TABLEGEN_CODEGENTARGET_H -#include "CodeGenRegisters.h" #include "CodeGenInstruction.h" -#include "Record.h" +#include "CodeGenRegisters.h" #include "llvm/Support/raw_ostream.h" +#include "llvm/TableGen/Record.h" #include namespace llvm { struct CodeGenRegister; +class CodeGenSchedModels; class CodeGenTarget; // SelectionDAG node properties. @@ -64,20 +65,21 @@ class CodeGenTarget { RecordKeeper &Records; Record *TargetRec; - mutable DenseMap Instructions; - mutable std::vector Registers; - mutable std::vector SubRegIndices; - mutable std::vector RegisterClasses; - mutable std::vector LegalValueTypes; - void ReadRegisters() const; - void ReadSubRegIndices() const; - void ReadRegisterClasses() const; + mutable DenseMap> Instructions; + mutable std::unique_ptr RegBank; + mutable std::vector RegAltNameIndices; + mutable SmallVector LegalValueTypes; + void ReadRegAltNameIndices() const; void ReadInstructions() const; void ReadLegalValueTypes() const; + mutable std::unique_ptr SchedModels; + mutable std::vector InstrsByEnum; public: CodeGenTarget(RecordKeeper &Records); + ~CodeGenTarget(); Record *getTargetRecord() const { return TargetRec; } const std::string &getName() const; @@ -94,106 +96,41 @@ public: /// Record *getAsmParser() const; + /// getAsmParserVariant - Return the AssmblyParserVariant definition for + /// this target. + /// + Record *getAsmParserVariant(unsigned i) const; + + /// getAsmParserVariantCount - Return the AssmblyParserVariant definition + /// available for this target. + /// + unsigned getAsmParserVariantCount() const; + /// getAsmWriter - Return the AssemblyWriter definition for this target. /// Record *getAsmWriter() const; - const std::vector &getRegisters() const { - if (Registers.empty()) ReadRegisters(); - return Registers; - } + /// getRegBank - Return the register bank description. + CodeGenRegBank &getRegBank() const; /// getRegisterByName - If there is a register with the specific AsmName, /// return it. const CodeGenRegister *getRegisterByName(StringRef Name) const; - const std::vector &getSubRegIndices() const { - if (SubRegIndices.empty()) ReadSubRegIndices(); - return SubRegIndices; - } - - // Map a SubRegIndex Record to its number. - unsigned getSubRegIndexNo(Record *idx) const { - if (SubRegIndices.empty()) ReadSubRegIndices(); - std::vector::const_iterator i = - std::find(SubRegIndices.begin(), SubRegIndices.end(), idx); - assert(i != SubRegIndices.end() && "Not a SubRegIndex"); - return (i - SubRegIndices.begin()) + 1; - } - - const std::vector &getRegisterClasses() const { - if (RegisterClasses.empty()) ReadRegisterClasses(); - return RegisterClasses; + const std::vector &getRegAltNameIndices() const { + if (RegAltNameIndices.empty()) ReadRegAltNameIndices(); + return RegAltNameIndices; } const CodeGenRegisterClass &getRegisterClass(Record *R) const { - const std::vector &RC = getRegisterClasses(); - for (unsigned i = 0, e = RC.size(); i != e; ++i) - if (RC[i].TheDef == R) - return RC[i]; - assert(0 && "Didn't find the register class"); - abort(); - } - - /// getRegisterClassForRegister - Find the register class that contains the - /// specified physical register. If the register is not in a register - /// class, return null. If the register is in multiple classes, and the - /// classes have a superset-subset relationship and the same set of - /// types, return the superclass. Otherwise return null. - const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const { - const std::vector &RCs = getRegisterClasses(); - const CodeGenRegisterClass *FoundRC = 0; - for (unsigned i = 0, e = RCs.size(); i != e; ++i) { - const CodeGenRegisterClass &RC = RegisterClasses[i]; - for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { - if (R != RC.Elements[ei]) - continue; - - // If a register's classes have different types, return null. - if (FoundRC && RC.getValueTypes() != FoundRC->getValueTypes()) - return 0; - - // If this is the first class that contains the register, - // make a note of it and go on to the next class. - if (!FoundRC) { - FoundRC = &RC; - break; - } - - std::vector Elements(RC.Elements); - std::vector FoundElements(FoundRC->Elements); - std::sort(Elements.begin(), Elements.end()); - std::sort(FoundElements.begin(), FoundElements.end()); - - // Check to see if the previously found class that contains - // the register is a subclass of the current class. If so, - // prefer the superclass. - if (std::includes(Elements.begin(), Elements.end(), - FoundElements.begin(), FoundElements.end())) { - FoundRC = &RC; - break; - } - - // Check to see if the previously found class that contains - // the register is a superclass of the current class. If so, - // prefer the superclass. - if (std::includes(FoundElements.begin(), FoundElements.end(), - Elements.begin(), Elements.end())) - break; - - // Multiple classes, and neither is a superclass of the other. - // Return null. - return 0; - } - } - return FoundRC; + return *getRegBank().getRegClass(R); } /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the /// specified physical register. std::vector getRegisterVTs(Record *R) const; - const std::vector &getLegalValueTypes() const { + ArrayRef getLegalValueTypes() const { if (LegalValueTypes.empty()) ReadLegalValueTypes(); return LegalValueTypes; } @@ -201,14 +138,17 @@ public: /// isLegalValueType - Return true if the specified value type is natively /// supported by the target (i.e. there are registers that directly hold it). bool isLegalValueType(MVT::SimpleValueType VT) const { - const std::vector &LegalVTs = getLegalValueTypes(); + ArrayRef LegalVTs = getLegalValueTypes(); for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) if (LegalVTs[i] == VT) return true; return false; } + CodeGenSchedModels &getSchedModels() const; + private: - DenseMap &getInstructions() const { + DenseMap> & + getInstructions() const { if (Instructions.empty()) ReadInstructions(); return Instructions; } @@ -216,8 +156,7 @@ public: CodeGenInstruction &getInstruction(const Record *InstRec) const { if (Instructions.empty()) ReadInstructions(); - DenseMap::iterator I = - Instructions.find(InstRec); + auto I = Instructions.find(InstRec); assert(I != Instructions.end() && "Not an instruction"); return *I->second; } @@ -233,12 +172,23 @@ public: typedef std::vector::const_iterator inst_iterator; inst_iterator inst_begin() const{return getInstructionsByEnumValue().begin();} inst_iterator inst_end() const { return getInstructionsByEnumValue().end(); } + iterator_range instructions() const { + return iterator_range(inst_begin(), inst_end()); + } /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? /// bool isLittleEndianEncoding() const; + /// reverseBitsForLittleEndianEncoding - For little-endian instruction bit + /// encodings, reverse the bit order of all instructions. + void reverseBitsForLittleEndianEncoding(); + + /// guessInstructionProperties - should we just guess unset instruction + /// properties? + bool guessInstructionProperties() const; + private: void ComputeInstrsByEnum() const; };