X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FCodeGenTarget.h;h=ef46b6c61851a8f36c6215e3e8cb19506af4f548;hb=62c939d7d5572e57963a5f26fb6fe802e13dc0bf;hp=00ca3fcc60322a1677b52b9d2a03c0e3ae7ed837;hpb=6ad90765541c688d955437548bf6cc3799f6c7af;p=oota-llvm.git diff --git a/utils/TableGen/CodeGenTarget.h b/utils/TableGen/CodeGenTarget.h index 00ca3fcc603..ef46b6c6185 100644 --- a/utils/TableGen/CodeGenTarget.h +++ b/utils/TableGen/CodeGenTarget.h @@ -1,56 +1,207 @@ -//===- CodeGenWrappers.h - Code Generation Class Wrappers -------*- C++ -*-===// +//===- CodeGenTarget.h - Target Class Wrapper -------------------*- C++ -*-===// // -// These classes wrap target description classes used by the various code -// generation TableGen backends. This makes it easier to access the data and -// provides a single place that needs to check it for validity. All of these -// classes throw exceptions on error conditions. +// The LLVM Compiler Infrastructure +// +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. +// +//===----------------------------------------------------------------------===// +// +// This file defines wrappers for the Target class and related global +// functionality. This makes it easier to access the data and provides a single +// place that needs to check it for validity. All of these classes throw +// exceptions on error conditions. // //===----------------------------------------------------------------------===// -#ifndef CODEGENWRAPPERS_H -#define CODEGENWRAPPERS_H +#ifndef CODEGEN_TARGET_H +#define CODEGEN_TARGET_H -#include "llvm/CodeGen/ValueTypes.h" +#include "CodeGenRegisters.h" +#include "CodeGenInstruction.h" #include -#include -#include +#include + +namespace llvm { + class Record; class RecordKeeper; +struct CodeGenRegister; +class CodeGenTarget; + +// SelectionDAG node properties. +// SDNPMemOperand: indicates that a node touches memory and therefore must +// have an associated memory operand that describes the access. +enum SDNP { + SDNPCommutative, + SDNPAssociative, + SDNPHasChain, + SDNPOutFlag, + SDNPInFlag, + SDNPOptInFlag, + SDNPMayLoad, + SDNPMayStore, + SDNPSideEffect, + SDNPMemOperand +}; -/// getValueType - Return the MVT::ValueType that the specified TableGen record -/// corresponds to. -MVT::ValueType getValueType(Record *Rec); +// ComplexPattern attributes. +enum CPAttr { CPAttrParentAsRoot }; -std::ostream &operator<<(std::ostream &OS, MVT::ValueType T); -std::string getName(MVT::ValueType T); -std::string getEnumName(MVT::ValueType T); +/// getValueType - Return the MVT::SimpleValueType that the specified TableGen +/// record corresponds to. +MVT::SimpleValueType getValueType(Record *Rec); +std::string getName(MVT::SimpleValueType T); +std::string getEnumName(MVT::SimpleValueType T); +/// getQualifiedName - Return the name of the specified record, with a +/// namespace qualifier if the record contains one. +std::string getQualifiedName(const Record *R); + /// CodeGenTarget - This class corresponds to the Target class in the .td files. /// class CodeGenTarget { Record *TargetRec; - std::vector CalleeSavedRegisters; - MVT::ValueType PointerType; + mutable std::map Instructions; + mutable std::vector Registers; + mutable std::vector RegisterClasses; + mutable std::vector LegalValueTypes; + void ReadRegisters() const; + void ReadRegisterClasses() const; + void ReadInstructions() const; + void ReadLegalValueTypes() const; public: CodeGenTarget(); Record *getTargetRecord() const { return TargetRec; } const std::string &getName() const; - const std::vector &getCalleeSavedRegisters() const { - return CalleeSavedRegisters; + /// getInstNamespace - Return the target-specific instruction namespace. + /// + std::string getInstNamespace() const; + + /// getInstructionSet - Return the InstructionSet object. + /// + Record *getInstructionSet() const; + + /// getAsmWriter - Return the AssemblyWriter definition for this target. + /// + Record *getAsmWriter() const; + + const std::vector &getRegisters() const { + if (Registers.empty()) ReadRegisters(); + return Registers; } - MVT::ValueType getPointerType() const { return PointerType; } + const std::vector &getRegisterClasses() const { + if (RegisterClasses.empty()) ReadRegisterClasses(); + return RegisterClasses; + } + + const CodeGenRegisterClass &getRegisterClass(Record *R) const { + const std::vector &RC = getRegisterClasses(); + for (unsigned i = 0, e = RC.size(); i != e; ++i) + if (RC[i].TheDef == R) + return RC[i]; + assert(0 && "Didn't find the register class"); + abort(); + } + + /// getRegisterClassForRegister - Find the register class that contains the + /// specified physical register. If there register exists in multiple + /// register classes or is not in a register class, return null. + const CodeGenRegisterClass *getRegisterClassForRegister(Record *R) const { + const std::vector &RCs = getRegisterClasses(); + const CodeGenRegisterClass *FoundRC = 0; + for (unsigned i = 0, e = RCs.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RegisterClasses[i]; + for (unsigned ei = 0, ee = RC.Elements.size(); ei != ee; ++ei) { + if (R == RC.Elements[ei]) { + if (FoundRC) return 0; // In multiple RC's + FoundRC = &RC; + break; + } + } + } + return FoundRC; + } - // getInstructionSet - Return the InstructionSet object... - Record *getInstructionSet() const; + /// getRegisterVTs - Find the union of all possible SimpleValueTypes for the + /// specified physical register. + std::vector getRegisterVTs(Record *R) const; + + const std::vector &getLegalValueTypes() const { + if (LegalValueTypes.empty()) ReadLegalValueTypes(); + return LegalValueTypes; + } + + /// isLegalValueType - Return true if the specified value type is natively + /// supported by the target (i.e. there are registers that directly hold it). + bool isLegalValueType(MVT::SimpleValueType VT) const { + const std::vector &LegalVTs = getLegalValueTypes(); + for (unsigned i = 0, e = LegalVTs.size(); i != e; ++i) + if (LegalVTs[i] == VT) return true; + return false; + } + + /// getInstructions - Return all of the instructions defined for this target. + /// + const std::map &getInstructions() const { + if (Instructions.empty()) ReadInstructions(); + return Instructions; + } + std::map &getInstructions() { + if (Instructions.empty()) ReadInstructions(); + return Instructions; + } + + CodeGenInstruction &getInstruction(const std::string &Name) const { + const std::map &Insts = getInstructions(); + assert(Insts.count(Name) && "Not an instruction!"); + return const_cast(Insts.find(Name)->second); + } + + typedef std::map::const_iterator inst_iterator; + inst_iterator inst_begin() const { return getInstructions().begin(); } + inst_iterator inst_end() const { return Instructions.end(); } - // getInstructionSet - Return the CodeGenInstructionSet object for this - // target, lazily reading it from the record keeper as needed. - // CodeGenInstructionSet *getInstructionSet - + /// getInstructionsByEnumValue - Return all of the instructions defined by the + /// target, ordered by their enum value. + void getInstructionsByEnumValue(std::vector + &NumberedInstructions); + + + /// isLittleEndianEncoding - are instruction bit patterns defined as [0..n]? + /// + bool isLittleEndianEncoding() const; +}; + +/// ComplexPattern - ComplexPattern info, corresponding to the ComplexPattern +/// tablegen class in TargetSelectionDAG.td +class ComplexPattern { + MVT::SimpleValueType Ty; + unsigned NumOperands; + std::string SelectFunc; + std::vector RootNodes; + unsigned Properties; // Node properties + unsigned Attributes; // Pattern attributes +public: + ComplexPattern() : NumOperands(0) {}; + ComplexPattern(Record *R); + + MVT::SimpleValueType getValueType() const { return Ty; } + unsigned getNumOperands() const { return NumOperands; } + const std::string &getSelectFunc() const { return SelectFunc; } + const std::vector &getRootNodes() const { + return RootNodes; + } + bool hasProperty(enum SDNP Prop) const { return Properties & (1 << Prop); } + bool hasAttribute(enum CPAttr Attr) const { return Attributes & (1 << Attr); } }; +} // End llvm namespace + #endif