X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FFastISelEmitter.cpp;h=154f96d3d0230109a4ddbb1ec1885024929214a0;hb=0e9c68e6bc8768143308b0162e900ba8bd10dc01;hp=6c2a76734c552658025e82507361f5e5a3fc2a8f;hpb=7b9cafde5e3faec22bbfbbc90cca0876968abad9;p=oota-llvm.git diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 6c2a76734c5..154f96d3d02 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -17,33 +17,36 @@ // //===----------------------------------------------------------------------===// -#include "FastISelEmitter.h" -#include "Record.h" +#include "CodeGenDAGPatterns.h" #include "llvm/ADT/SmallString.h" -#include "llvm/ADT/VectorExtras.h" #include "llvm/Support/Debug.h" #include "llvm/Support/ErrorHandling.h" +#include "llvm/TableGen/Error.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" using namespace llvm; -namespace { /// InstructionMemo - This class holds additional information about an /// instruction needed to emit code for it. /// +namespace { struct InstructionMemo { std::string Name; const CodeGenRegisterClass *RC; std::string SubRegNo; std::vector* PhysRegs; }; - +} // End anonymous namespace + /// ImmPredicateSet - This uniques predicates (represented as a string) and /// gives them unique (small) integer ID's that start at 0. +namespace { class ImmPredicateSet { DenseMap ImmIDs; std::vector PredsByName; public: - + unsigned getIDFor(TreePredicateFn Pred) { unsigned &Entry = ImmIDs[Pred.getOrigPatFragRecord()]; if (Entry == 0) { @@ -52,29 +55,31 @@ public: } return Entry-1; } - + const TreePredicateFn &getPredicate(unsigned i) { assert(i < PredsByName.size()); return PredsByName[i]; } - + typedef std::vector::const_iterator iterator; iterator begin() const { return PredsByName.begin(); } iterator end() const { return PredsByName.end(); } - + }; +} // End anonymous namespace /// OperandsSignature - This class holds a description of a list of operand /// types. It has utility methods for emitting text based on the operands. /// +namespace { struct OperandsSignature { class OpKind { enum { OK_Reg, OK_FP, OK_Imm, OK_Invalid = -1 }; char Repr; public: - + OpKind() : Repr(OK_Invalid) {} - + bool operator<(OpKind RHS) const { return Repr < RHS.Repr; } bool operator==(OpKind RHS) const { return Repr == RHS.Repr; } @@ -85,13 +90,13 @@ struct OperandsSignature { "Too many integer predicates for the 'Repr' char"); OpKind K; K.Repr = OK_Imm+V; return K; } - + bool isReg() const { return Repr == OK_Reg; } bool isFP() const { return Repr == OK_FP; } bool isImm() const { return Repr >= OK_Imm; } - + unsigned getImmCode() const { assert(isImm()); return Repr-OK_Imm; } - + void printManglingSuffix(raw_ostream &OS, ImmPredicateSet &ImmPredicates, bool StripImmCodes) const { if (isReg()) @@ -106,8 +111,8 @@ struct OperandsSignature { } } }; - - + + SmallVector Operands; bool operator<(const OperandsSignature &O) const { @@ -125,7 +130,7 @@ struct OperandsSignature { return true; return false; } - + /// getWithoutImmCodes - Return a copy of this with any immediate codes forced /// to zero. OperandsSignature getWithoutImmCodes() const { @@ -137,52 +142,53 @@ struct OperandsSignature { Result.Operands.push_back(OpKind::getImm(0)); return Result; } - + void emitImmediatePredicate(raw_ostream &OS, ImmPredicateSet &ImmPredicates) { bool EmittedAnything = false; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (!Operands[i].isImm()) continue; - + unsigned Code = Operands[i].getImmCode(); if (Code == 0) continue; - + if (EmittedAnything) OS << " &&\n "; - + TreePredicateFn PredFn = ImmPredicates.getPredicate(Code-1); - + // Emit the type check. OS << "VT == " << getEnumName(PredFn.getOrigPatFragRecord()->getTree(0)->getType(0)) << " && "; - - + + OS << PredFn.getFnName() << "(imm" << i <<')'; EmittedAnything = true; } } - + /// initialize - Examine the given pattern and initialize the contents /// of the Operands array accordingly. Return true if all the operands /// are supported, false otherwise. /// bool initialize(TreePatternNode *InstPatNode, const CodeGenTarget &Target, MVT::SimpleValueType VT, - ImmPredicateSet &ImmediatePredicates) { + ImmPredicateSet &ImmediatePredicates, + const CodeGenRegisterClass *OrigDstRC) { if (InstPatNode->isLeaf()) return false; - + if (InstPatNode->getOperator()->getName() == "imm") { Operands.push_back(OpKind::getImm(0)); return true; } - + if (InstPatNode->getOperator()->getName() == "fpimm") { Operands.push_back(OpKind::getFP()); return true; } - const CodeGenRegisterClass *DstRC = 0; + const CodeGenRegisterClass *DstRC = nullptr; for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { TreePatternNode *Op = InstPatNode->getChild(i); @@ -205,19 +211,19 @@ struct OperandsSignature { Record *Rec = PredFn.getOrigPatFragRecord()->getRecord(); if (Rec->getValueAsBit("FastIselShouldIgnore")) return false; - + PredNo = ImmediatePredicates.getIDFor(PredFn)+1; } - + // Handle unmatched immediate sizes here. //if (Op->getType(0) != VT) // return false; - + Operands.push_back(OpKind::getImm(PredNo)); continue; } - + // For now, filter out any operand with a predicate. // For now, filter out any operand with multiple values. if (!Op->getPredicateFns().empty() || Op->getNumTypes() != 1) @@ -231,7 +237,7 @@ struct OperandsSignature { // For now, ignore other non-leaf nodes. return false; } - + assert(Op->hasTypeSet(0) && "Type infererence not done?"); // For now, all the operands must have the same type (if they aren't @@ -240,18 +246,22 @@ struct OperandsSignature { if (Op->getType(0) != VT) return false; - DefInit *OpDI = dynamic_cast(Op->getLeafValue()); + DefInit *OpDI = dyn_cast(Op->getLeafValue()); if (!OpDI) return false; Record *OpLeafRec = OpDI->getDef(); - + // For now, the only other thing we accept is register operands. - const CodeGenRegisterClass *RC = 0; + const CodeGenRegisterClass *RC = nullptr; + if (OpLeafRec->isSubClassOf("RegisterOperand")) + OpLeafRec = OpLeafRec->getValueAsDef("RegClass"); if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); else if (OpLeafRec->isSubClassOf("Register")) RC = Target.getRegBank().getRegClassForRegister(OpLeafRec); - else + else if (OpLeafRec->isSubClassOf("ValueType")) { + RC = OrigDstRC; + } else return false; // For now, this needs to be a register class of some sort. @@ -277,7 +287,7 @@ struct OperandsSignature { } else if (Operands[i].isImm()) { OS << "uint64_t imm" << i; } else if (Operands[i].isFP()) { - OS << "ConstantFP *f" << i; + OS << "const ConstantFP *f" << i; } else { llvm_unreachable("Unknown operand kind!"); } @@ -350,7 +360,9 @@ struct OperandsSignature { Operands[i].printManglingSuffix(OS, ImmPredicates, StripImmCodes); } }; +} // End anonymous namespace +namespace { class FastISelMap { typedef std::map PredMap; typedef std::map RetPredMap; @@ -363,7 +375,7 @@ class FastISelMap { std::map > SignaturesWithConstantForms; - + std::string InstNS; ImmPredicateSet ImmediatePredicates; public: @@ -373,8 +385,7 @@ public: void printImmediatePredicates(raw_ostream &OS); void printFunctionDefinitions(raw_ostream &OS); }; - -} +} // End anonymous namespace static std::string getOpcodeName(Record *Op, CodeGenDAGPatterns &CGP) { return CGP.getSDNodeInfo(Op).getEnumName(); @@ -398,23 +409,14 @@ static std::string PhyRegForNode(TreePatternNode *Op, if (!Op->isLeaf()) return PhysReg; - DefInit *OpDI = dynamic_cast(Op->getLeafValue()); - Record *OpLeafRec = OpDI->getDef(); + Record *OpLeafRec = cast(Op->getLeafValue())->getDef(); if (!OpLeafRec->isSubClassOf("Register")) return PhysReg; - PhysReg += static_cast(OpLeafRec->getValue( \ - "Namespace")->getValue())->getValue(); + PhysReg += cast(OpLeafRec->getValue("Namespace")->getValue()) + ->getValue(); PhysReg += "::"; - - std::vector Regs = Target.getRegisters(); - for (unsigned i = 0; i < Regs.size(); ++i) { - if (Regs[i].TheDef == OpLeafRec) { - PhysReg += Regs[i].getName(); - break; - } - } - + PhysReg += Target.getRegBank().getReg(OpLeafRec)->getName(); return PhysReg; } @@ -457,10 +459,12 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // For now, ignore instructions where the first operand is not an // output register. - const CodeGenRegisterClass *DstRC = 0; + const CodeGenRegisterClass *DstRC = nullptr; std::string SubRegNo; if (Op->getName() != "EXTRACT_SUBREG") { Record *Op0Rec = II.Operands[0].Rec; + if (Op0Rec->isSubClassOf("RegisterOperand")) + Op0Rec = Op0Rec->getValueAsDef("RegClass"); if (!Op0Rec->isSubClassOf("RegisterClass")) continue; DstRC = &Target.getRegisterClass(Op0Rec); @@ -471,7 +475,7 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // a bit too complicated for now. if (!Dst->getChild(1)->isLeaf()) continue; - DefInit *SR = dynamic_cast(Dst->getChild(1)->getLeafValue()); + DefInit *SR = dyn_cast(Dst->getChild(1)->getLeafValue()); if (SR) SubRegNo = getQualifiedName(SR->getDef()); else @@ -502,12 +506,13 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { // Check all the operands. OperandsSignature Operands; - if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates)) + if (!Operands.initialize(InstPatNode, Target, VT, ImmediatePredicates, + DstRC)) continue; std::vector* PhysRegInputs = new std::vector(); if (InstPatNode->getOperator()->getName() == "imm" || - InstPatNode->getOperator()->getName() == "fpimmm") + InstPatNode->getOperator()->getName() == "fpimm") PhysRegInputs->push_back(""); else { // Compute the PhysRegs used by the given pattern, and check that @@ -546,13 +551,13 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { SubRegNo, PhysRegInputs }; - + if (SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck)) - throw TGError(Pattern.getSrcRecord()->getLoc(), + PrintFatalError(Pattern.getSrcRecord()->getLoc(), "Duplicate record in FastISel table!"); SimplePatterns[Operands][OpcodeName][VT][RetVT][PredicateCheck] = Memo; - + // If any of the operands were immediates with predicates on them, strip // them down to a signature that doesn't have predicates so that we can // associate them with the stripped predicate version. @@ -566,14 +571,14 @@ void FastISelMap::collectPatterns(CodeGenDAGPatterns &CGP) { void FastISelMap::printImmediatePredicates(raw_ostream &OS) { if (ImmediatePredicates.begin() == ImmediatePredicates.end()) return; - + OS << "\n// FastEmit Immediate Predicate functions.\n"; for (ImmPredicateSet::iterator I = ImmediatePredicates.begin(), E = ImmediatePredicates.end(); I != E; ++I) { OS << "static bool " << I->getFnName() << "(int64_t Imm) {\n"; OS << I->getImmediatePredicateCode() << "\n}\n"; } - + OS << "\n\n"; } @@ -633,7 +638,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { if ((*Memo.PhysRegs)[i] != "") - OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " + OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, " << "TII.get(TargetOpcode::COPY), " << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; } @@ -643,7 +648,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, ImmediatePredicates, true); OS << "(" << InstNS << Memo.Name << ", "; - OS << InstNS << Memo.RC->getName() << "RegisterClass"; + OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; if (!Operands.empty()) OS << ", "; Operands.PrintArguments(OS, *Memo.PhysRegs); @@ -724,7 +729,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { if ((*Memo.PhysRegs)[i] != "") - OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, " + OS << " BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, " << "TII.get(TargetOpcode::COPY), " << (*Memo.PhysRegs)[i] << ").addReg(Op" << i << ");\n"; } @@ -735,7 +740,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { Operands.PrintManglingSuffix(OS, *Memo.PhysRegs, ImmediatePredicates, true); OS << "(" << InstNS << Memo.Name << ", "; - OS << InstNS << Memo.RC->getName() << "RegisterClass"; + OS << "&" << InstNS << Memo.RC->getName() << "RegClass"; if (!Operands.empty()) OS << ", "; Operands.PrintArguments(OS, *Memo.PhysRegs); @@ -799,11 +804,11 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << ", "; Operands.PrintParameters(OS); OS << ") {\n"; - - // If there are any forms of this signature available that operand on - // constrained forms of the immediate (e.g. 32-bit sext immediate in a + + // If there are any forms of this signature available that operate on + // constrained forms of the immediate (e.g., 32-bit sext immediate in a // 64-bit operand), check them first. - + std::map >::iterator MI = SignaturesWithConstantForms.find(Operands); if (MI != SignaturesWithConstantForms.end()) { @@ -811,7 +816,7 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { std::sort(MI->second.begin(), MI->second.end()); MI->second.erase(std::unique(MI->second.begin(), MI->second.end()), MI->second.end()); - + // Check each in order it was seen. It would be nice to have a good // relative ordering between them, but we're not going for optimality // here. @@ -826,11 +831,11 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { MI->second[i].PrintArguments(OS); OS << "))\n return Reg;\n\n"; } - + // Done with this, remove it. SignaturesWithConstantForms.erase(MI); } - + OS << " switch (Opcode) {\n"; for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); I != E; ++I) { @@ -850,27 +855,26 @@ void FastISelMap::printFunctionDefinitions(raw_ostream &OS) { OS << "}\n"; OS << "\n"; } - + // TODO: SignaturesWithConstantForms should be empty here. } -void FastISelEmitter::run(raw_ostream &OS) { +namespace llvm { + +void EmitFastISel(RecordKeeper &RK, raw_ostream &OS) { + CodeGenDAGPatterns CGP(RK); const CodeGenTarget &Target = CGP.getTargetInfo(); + emitSourceFileHeader("\"Fast\" Instruction Selector for the " + + Target.getName() + " target", OS); // Determine the target's namespace name. std::string InstNS = Target.getInstNamespace() + "::"; assert(InstNS.size() > 2 && "Can't determine target-specific namespace!"); - EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + - Target.getName() + " target", OS); - FastISelMap F(InstNS); F.collectPatterns(CGP); F.printImmediatePredicates(OS); F.printFunctionDefinitions(OS); } -FastISelEmitter::FastISelEmitter(RecordKeeper &R) - : Records(R), CGP(R) { -} - +} // End llvm namespace