X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FFastISelEmitter.cpp;h=3ce764259898e39887f7286b812eba9696ec9254;hb=20072af3b0b22d90afbce769409f4ed822520366;hp=290676ae7a524073d93e33fc8de2996a05bd372e;hpb=10df0fa73e396bbc93a8940e8b53827390c54d10;p=oota-llvm.git diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 290676ae7a5..3ce76425989 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -7,32 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This tablegen backend emits a "fast" instruction selector. +// This tablegen backend emits code for use by the "fast" instruction +// selection algorithm. See the comments at the top of +// lib/CodeGen/SelectionDAG/FastISel.cpp for background. // -// This instruction selection method is designed to emit very poor code -// quickly. Also, it is not designed to do much lowering, so most illegal -// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not -// supported and cannot easily be added. Blocks containing operations -// that are not supported need to be handled by a more capable selector, -// such as the SelectionDAG selector. +// This file scans through the target's tablegen instruction-info files +// and extracts instructions with obvious-looking patterns, and it emits +// code to look up these instructions by type and operator. // -// The intended use for "fast" instruction selection is "-O0" mode -// compilation, where the quality of the generated code is irrelevant when -// weighed against the speed at which the code can be generated. -// -// If compile time is so important, you might wonder why we don't just -// skip codegen all-together, emit LLVM bytecode files, and execute them -// with an interpreter. The answer is that it would complicate linking and -// debugging, and also because that isn't how a compiler is expected to -// work in some circles. -// -// If you need better generated code or more lowering than what this -// instruction selector provides, use the SelectionDAG (DAGISel) instruction -// selector instead. If you're looking here because SelectionDAG isn't fast -// enough, consider looking into improving the SelectionDAG infastructure -// instead. At the time of this writing there remain several major -// opportunities for improvement. -// //===----------------------------------------------------------------------===// #include "FastISelEmitter.h" @@ -44,6 +26,16 @@ using namespace llvm; namespace { +/// InstructionMemo - This class holds additional information about an +/// instruction needed to emit code for it. +/// +struct InstructionMemo { + std::string Name; + const CodeGenRegisterClass *RC; + unsigned char SubRegNo; + std::vector* PhysRegs; +}; + /// OperandsSignature - This class holds a description of a list of operand /// types. It has utility methods for emitting text based on the operands. /// @@ -79,7 +71,7 @@ struct OperandsSignature { for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { TreePatternNode *Op = InstPatNode->getChild(i); // For now, filter out any operand with a predicate. - if (!Op->getPredicateFn().empty()) + if (!Op->getPredicateFns().empty()) return false; // For now, filter out any operand with multiple values. if (Op->getExtTypes().size() != 1) @@ -96,22 +88,24 @@ struct OperandsSignature { Operands.push_back("f"); return true; } - // For now, ignore fpimm and other non-leaf nodes. + // For now, ignore other non-leaf nodes. return false; } DefInit *OpDI = dynamic_cast(Op->getLeafValue()); if (!OpDI) return false; Record *OpLeafRec = OpDI->getDef(); - // TODO: handle instructions which have physreg operands. - if (OpLeafRec->isSubClassOf("Register")) - return false; // For now, the only other thing we accept is register operands. - if (!OpLeafRec->isSubClassOf("RegisterClass")) + + const CodeGenRegisterClass *RC = 0; + if (OpLeafRec->isSubClassOf("RegisterClass")) + RC = &Target.getRegisterClass(OpLeafRec); + else if (OpLeafRec->isSubClassOf("Register")) + RC = Target.getRegisterClassForRegister(OpLeafRec); + else return false; // For now, require the register operands' register classes to all // be the same. - const CodeGenRegisterClass *RC = &Target.getRegisterClass(OpLeafRec); if (!RC) return false; // For now, all the operands must have the same register class. @@ -142,6 +136,33 @@ struct OperandsSignature { } } + void PrintArguments(std::ostream &OS, + const std::vector& PR) const { + assert(PR.size() == Operands.size()); + bool PrintedArg = false; + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (PR[i] != "") + // Implicit physical register operand. + continue; + + if (PrintedArg) + OS << ", "; + if (Operands[i] == "r") { + OS << "Op" << i; + PrintedArg = true; + } else if (Operands[i] == "i") { + OS << "imm" << i; + PrintedArg = true; + } else if (Operands[i] == "f") { + OS << "f" << i; + PrintedArg = true; + } else { + assert("Unknown operand kind!"); + abort(); + } + } + } + void PrintArguments(std::ostream &OS) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { if (Operands[i] == "r") { @@ -159,19 +180,26 @@ struct OperandsSignature { } } - void PrintManglingSuffix(std::ostream &OS) const { + + void PrintManglingSuffix(std::ostream &OS, + const std::vector& PR) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (PR[i] != "") + // Implicit physical register operand. e.g. Instruction::Mul expect to + // select to a binary op. On x86, mul may take a single operand with + // the other operand being implicit. We must emit something that looks + // like a binary instruction except for the very inner FastEmitInst_* + // call. + continue; OS << Operands[i]; } } -}; -/// InstructionMemo - This class holds additional information about an -/// instruction needed to emit code for it. -/// -struct InstructionMemo { - std::string Name; - const CodeGenRegisterClass *RC; + void PrintManglingSuffix(std::ostream &OS) const { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + OS << Operands[i]; + } + } }; class FastISelMap { @@ -233,14 +261,35 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { if (II.OperandList.empty()) continue; + // For now, ignore multi-instruction patterns. + bool MultiInsts = false; + for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { + TreePatternNode *ChildOp = Dst->getChild(i); + if (ChildOp->isLeaf()) + continue; + if (ChildOp->getOperator()->isSubClassOf("Instruction")) { + MultiInsts = true; + break; + } + } + if (MultiInsts) + continue; + // For now, ignore instructions where the first operand is not an // output register. - Record *Op0Rec = II.OperandList[0].Rec; - if (!Op0Rec->isSubClassOf("RegisterClass")) - continue; - const CodeGenRegisterClass *DstRC = &Target.getRegisterClass(Op0Rec); - if (!DstRC) - continue; + const CodeGenRegisterClass *DstRC = 0; + unsigned SubRegNo = ~0; + if (Op->getName() != "EXTRACT_SUBREG") { + Record *Op0Rec = II.OperandList[0].Rec; + if (!Op0Rec->isSubClassOf("RegisterClass")) + continue; + DstRC = &Target.getRegisterClass(Op0Rec); + if (!DstRC) + continue; + } else { + SubRegNo = static_cast( + Dst->getChild(1)->getLeafValue())->getValue(); + } // Inspect the pattern. TreePatternNode *InstPatNode = Pattern.getSrcPattern(); @@ -260,13 +309,48 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { continue; // For now, filter out any instructions with predicates. - if (!InstPatNode->getPredicateFn().empty()) + if (!InstPatNode->getPredicateFns().empty()) continue; // Check all the operands. OperandsSignature Operands; if (!Operands.initialize(InstPatNode, Target, VT)) continue; + + std::vector* PhysRegInputs = new std::vector(); + if (!InstPatNode->isLeaf() && + (InstPatNode->getOperator()->getName() == "imm" || + InstPatNode->getOperator()->getName() == "fpimmm")) + PhysRegInputs->push_back(""); + else if (!InstPatNode->isLeaf()) { + for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { + TreePatternNode *Op = InstPatNode->getChild(i); + if (!Op->isLeaf()) { + PhysRegInputs->push_back(""); + continue; + } + + DefInit *OpDI = dynamic_cast(Op->getLeafValue()); + Record *OpLeafRec = OpDI->getDef(); + std::string PhysReg; + if (OpLeafRec->isSubClassOf("Register")) { + PhysReg += static_cast(OpLeafRec->getValue( \ + "Namespace")->getValue())->getValue(); + PhysReg += "::"; + + std::vector Regs = Target.getRegisters(); + for (unsigned i = 0; i < Regs.size(); ++i) { + if (Regs[i].TheDef == OpLeafRec) { + PhysReg += Regs[i].getName(); + break; + } + } + } + + PhysRegInputs->push_back(PhysReg); + } + } else + PhysRegInputs->push_back(""); // Get the predicate that guards this pattern. std::string PredicateCheck = Pattern.getPredicateCheck(); @@ -274,7 +358,9 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { // Ok, we found a pattern that we can handle. Remember it. InstructionMemo Memo = { Pattern.getDstPattern()->getOperator()->getName(), - DstRC + DstRC, + SubRegNo, + PhysRegInputs }; assert(!SimplePatterns[Operands][OpcodeName][VT][RetVT].count(PredicateCheck) && "Duplicate pattern!"); @@ -282,81 +368,6 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { } } -void FastISelMap::PrintClass(std::ostream &OS) { - // Declare the target FastISel class. - OS << "class FastISel : public llvm::FastISel {\n"; - for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), - OE = SimplePatterns.end(); OI != OE; ++OI) { - const OperandsSignature &Operands = OI->first; - const OpcodeTypeRetPredMap &OTM = OI->second; - - for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); - I != E; ++I) { - const std::string &Opcode = I->first; - const TypeRetPredMap &TM = I->second; - - for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); - TI != TE; ++TI) { - MVT::SimpleValueType VT = TI->first; - const RetPredMap &RM = TI->second; - - if (RM.size() != 1) - for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); - RI != RE; ++RI) { - MVT::SimpleValueType RetVT = RI->first; - OS << " unsigned FastEmit_" << getLegalCName(Opcode) - << "_" << getLegalCName(getName(VT)) << "_" - << getLegalCName(getName(RetVT)) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "("; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_" << getLegalCName(Opcode) - << "_" << getLegalCName(getName(VT)) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType RetVT"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - OS << "\n"; - - // Declare the Subtarget member, which is used for predicate checks. - OS << " const " << InstNS.substr(0, InstNS.size() - 2) - << "Subtarget *Subtarget;\n"; - OS << "\n"; - - // Declare the constructor. - OS << "public:\n"; - OS << " explicit FastISel(MachineFunction &mf)\n"; - OS << " : llvm::FastISel(mf),\n"; - OS << " Subtarget(&TM.getSubtarget<" << InstNS.substr(0, InstNS.size() - 2) - << "Subtarget>()) {}\n"; - OS << "};\n"; - OS << "\n"; -} - void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Now emit code for all the patterns that we collected. for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), @@ -384,7 +395,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { const PredMap &PM = RI->second; bool HasPred = false; - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_" << getLegalCName(getName(RetVT)) << "_"; @@ -405,18 +416,38 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { "Multiple instructions match, at least one has " "a predicate and at least one doesn't!"); } else { - OS << " if (" + PredicateCheck + ")\n"; + OS << " if (" + PredicateCheck + ") {\n"; OS << " "; HasPred = true; } + + for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { + if ((*Memo.PhysRegs)[i] != "") + OS << " TII.copyRegToReg(*MBB, MBB->end(), " + << (*Memo.PhysRegs)[i] << ", Op" << i << ", " + << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" + << (*Memo.PhysRegs)[i] << "), " + << "MRI.getRegClass(Op" << i << "));\n"; + } + OS << " return FastEmitInst_"; - Operands.PrintManglingSuffix(OS); - OS << "(" << InstNS << Memo.Name << ", "; - OS << InstNS << Memo.RC->getName() << "RegisterClass"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintArguments(OS); - OS << ");\n"; + if (Memo.SubRegNo == (unsigned char)~0) { + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); + OS << "(" << InstNS << Memo.Name << ", "; + OS << InstNS << Memo.RC->getName() << "RegisterClass"; + if (!Operands.empty()) + OS << ", "; + Operands.PrintArguments(OS, *Memo.PhysRegs); + OS << ");\n"; + } else { + OS << "extractsubreg(Op0, "; + OS << (unsigned)Memo.SubRegNo; + OS << ");\n"; + } + + if (HasPred) + OS << " }\n"; + } // Return 0 if none of the predicates were satisfied. if (HasPred) @@ -426,7 +457,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } // Emit one function for the type that demultiplexes on return type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; Operands.PrintManglingSuffix(OS); @@ -450,7 +481,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } else { // Non-variadic return type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; Operands.PrintManglingSuffix(OS); @@ -468,7 +499,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Emit code for each possible instruction. There may be // multiple if there are subtarget concerns. - for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) { + for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; + ++PI) { std::string PredicateCheck = PI->first; const InstructionMemo &Memo = PI->second; @@ -477,18 +509,38 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { "Multiple instructions match, at least one has " "a predicate and at least one doesn't!"); } else { - OS << " if (" + PredicateCheck + ")\n"; + OS << " if (" + PredicateCheck + ") {\n"; OS << " "; HasPred = true; } + + for (unsigned i = 0; i < Memo.PhysRegs->size(); ++i) { + if ((*Memo.PhysRegs)[i] != "") + OS << " TII.copyRegToReg(*MBB, MBB->end(), " + << (*Memo.PhysRegs)[i] << ", Op" << i << ", " + << "TM.getRegisterInfo()->getPhysicalRegisterRegClass(" + << (*Memo.PhysRegs)[i] << "), " + << "MRI.getRegClass(Op" << i << "));\n"; + } + OS << " return FastEmitInst_"; - Operands.PrintManglingSuffix(OS); - OS << "(" << InstNS << Memo.Name << ", "; - OS << InstNS << Memo.RC->getName() << "RegisterClass"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintArguments(OS); - OS << ");\n"; + + if (Memo.SubRegNo == (unsigned char)~0) { + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); + OS << "(" << InstNS << Memo.Name << ", "; + OS << InstNS << Memo.RC->getName() << "RegisterClass"; + if (!Operands.empty()) + OS << ", "; + Operands.PrintArguments(OS, *Memo.PhysRegs); + OS << ");\n"; + } else { + OS << "extractsubreg(Op0, "; + OS << (unsigned)Memo.SubRegNo; + OS << ");\n"; + } + + if (HasPred) + OS << " }\n"; } // Return 0 if none of the predicates were satisfied. @@ -500,7 +552,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } // Emit one function for the opcode that demultiplexes based on the type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_"; Operands.PrintManglingSuffix(OS); OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT"; @@ -533,7 +585,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Emit one function for the operand signature that demultiplexes based // on opcode and type. - OS << "unsigned FastISel::FastEmit_"; + OS << "unsigned FastEmit_"; Operands.PrintManglingSuffix(OS); OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode"; if (!Operands.empty()) @@ -571,27 +623,9 @@ void FastISelEmitter::run(std::ostream &OS) { EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + Target.getName() + " target", OS); - OS << "#include \"llvm/CodeGen/FastISel.h\"\n"; - OS << "\n"; - OS << "namespace llvm {\n"; - OS << "\n"; - OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n"; - OS << "\n"; - FastISelMap F(InstNS); F.CollectPatterns(CGP); - F.PrintClass(OS); F.PrintFunctionDefinitions(OS); - - // Define the target FastISel creation function. - OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n"; - OS << " return new FastISel(mf);\n"; - OS << "}\n"; - OS << "\n"; - - OS << "} // namespace X86\n"; - OS << "\n"; - OS << "} // namespace llvm\n"; } FastISelEmitter::FastISelEmitter(RecordKeeper &R)