X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FFastISelEmitter.cpp;h=3ce764259898e39887f7286b812eba9696ec9254;hb=b2a14325079f64debd7df6d5a8ed2037b3128154;hp=4f0124310400bc225924bc73882d8409a9e0c271;hpb=667d8f7607f021c66c854ff3ea35a9df107eabfe;p=oota-llvm.git diff --git a/utils/TableGen/FastISelEmitter.cpp b/utils/TableGen/FastISelEmitter.cpp index 4f012431040..3ce76425989 100644 --- a/utils/TableGen/FastISelEmitter.cpp +++ b/utils/TableGen/FastISelEmitter.cpp @@ -7,32 +7,14 @@ // //===----------------------------------------------------------------------===// // -// This tablegen backend emits a "fast" instruction selector. +// This tablegen backend emits code for use by the "fast" instruction +// selection algorithm. See the comments at the top of +// lib/CodeGen/SelectionDAG/FastISel.cpp for background. // -// This instruction selection method is designed to emit very poor code -// quickly. Also, it is not designed to do much lowering, so most illegal -// types (e.g. i64 on 32-bit targets) and operations (e.g. calls) are not -// supported and cannot easily be added. Blocks containing operations -// that are not supported need to be handled by a more capable selector, -// such as the SelectionDAG selector. +// This file scans through the target's tablegen instruction-info files +// and extracts instructions with obvious-looking patterns, and it emits +// code to look up these instructions by type and operator. // -// The intended use for "fast" instruction selection is "-O0" mode -// compilation, where the quality of the generated code is irrelevant when -// weighed against the speed at which the code can be generated. -// -// If compile time is so important, you might wonder why we don't just -// skip codegen all-together, emit LLVM bytecode files, and execute them -// with an interpreter. The answer is that it would complicate linking and -// debugging, and also because that isn't how a compiler is expected to -// work in some circles. -// -// If you need better generated code or more lowering than what this -// instruction selector provides, use the SelectionDAG (DAGISel) instruction -// selector instead. If you're looking here because SelectionDAG isn't fast -// enough, consider looking into improving the SelectionDAG infastructure -// instead. At the time of this writing there remain several major -// opportunities for improvement. -// //===----------------------------------------------------------------------===// #include "FastISelEmitter.h" @@ -89,7 +71,7 @@ struct OperandsSignature { for (unsigned i = 0, e = InstPatNode->getNumChildren(); i != e; ++i) { TreePatternNode *Op = InstPatNode->getChild(i); // For now, filter out any operand with a predicate. - if (!Op->getPredicateFn().empty()) + if (!Op->getPredicateFns().empty()) return false; // For now, filter out any operand with multiple values. if (Op->getExtTypes().size() != 1) @@ -114,7 +96,7 @@ struct OperandsSignature { return false; Record *OpLeafRec = OpDI->getDef(); // For now, the only other thing we accept is register operands. - + const CodeGenRegisterClass *RC = 0; if (OpLeafRec->isSubClassOf("RegisterClass")) RC = &Target.getRegisterClass(OpLeafRec); @@ -157,21 +139,27 @@ struct OperandsSignature { void PrintArguments(std::ostream &OS, const std::vector& PR) const { assert(PR.size() == Operands.size()); + bool PrintedArg = false; for (unsigned i = 0, e = Operands.size(); i != e; ++i) { - if (PR[i] != "") { - OS << PR[i]; - } else if (Operands[i] == "r") { + if (PR[i] != "") + // Implicit physical register operand. + continue; + + if (PrintedArg) + OS << ", "; + if (Operands[i] == "r") { OS << "Op" << i; + PrintedArg = true; } else if (Operands[i] == "i") { OS << "imm" << i; + PrintedArg = true; } else if (Operands[i] == "f") { OS << "f" << i; + PrintedArg = true; } else { assert("Unknown operand kind!"); abort(); } - if (i + 1 != e) - OS << ", "; } } @@ -193,6 +181,20 @@ struct OperandsSignature { } + void PrintManglingSuffix(std::ostream &OS, + const std::vector& PR) const { + for (unsigned i = 0, e = Operands.size(); i != e; ++i) { + if (PR[i] != "") + // Implicit physical register operand. e.g. Instruction::Mul expect to + // select to a binary op. On x86, mul may take a single operand with + // the other operand being implicit. We must emit something that looks + // like a binary instruction except for the very inner FastEmitInst_* + // call. + continue; + OS << Operands[i]; + } + } + void PrintManglingSuffix(std::ostream &OS) const { for (unsigned i = 0, e = Operands.size(); i != e; ++i) { OS << Operands[i]; @@ -259,6 +261,20 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { if (II.OperandList.empty()) continue; + // For now, ignore multi-instruction patterns. + bool MultiInsts = false; + for (unsigned i = 0, e = Dst->getNumChildren(); i != e; ++i) { + TreePatternNode *ChildOp = Dst->getChild(i); + if (ChildOp->isLeaf()) + continue; + if (ChildOp->getOperator()->isSubClassOf("Instruction")) { + MultiInsts = true; + break; + } + } + if (MultiInsts) + continue; + // For now, ignore instructions where the first operand is not an // output register. const CodeGenRegisterClass *DstRC = 0; @@ -293,7 +309,7 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { continue; // For now, filter out any instructions with predicates. - if (!InstPatNode->getPredicateFn().empty()) + if (!InstPatNode->getPredicateFns().empty()) continue; // Check all the operands. @@ -352,89 +368,6 @@ void FastISelMap::CollectPatterns(CodeGenDAGPatterns &CGP) { } } -void FastISelMap::PrintClass(std::ostream &OS) { - // Declare the target FastISel class. - OS << "class FastISel : public llvm::FastISel {\n"; - for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), - OE = SimplePatterns.end(); OI != OE; ++OI) { - const OperandsSignature &Operands = OI->first; - const OpcodeTypeRetPredMap &OTM = OI->second; - - for (OpcodeTypeRetPredMap::const_iterator I = OTM.begin(), E = OTM.end(); - I != E; ++I) { - const std::string &Opcode = I->first; - const TypeRetPredMap &TM = I->second; - - for (TypeRetPredMap::const_iterator TI = TM.begin(), TE = TM.end(); - TI != TE; ++TI) { - MVT::SimpleValueType VT = TI->first; - const RetPredMap &RM = TI->second; - - if (RM.size() != 1) - for (RetPredMap::const_iterator RI = RM.begin(), RE = RM.end(); - RI != RE; ++RI) { - MVT::SimpleValueType RetVT = RI->first; - OS << " unsigned FastEmit_" << getLegalCName(Opcode) - << "_" << getLegalCName(getName(VT)) << "_" - << getLegalCName(getName(RetVT)) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "("; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_" << getLegalCName(Opcode) - << "_" << getLegalCName(getName(VT)) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType RetVT"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_" << getLegalCName(Opcode) << "_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - - OS << " unsigned FastEmit_"; - Operands.PrintManglingSuffix(OS); - OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode"; - if (!Operands.empty()) - OS << ", "; - Operands.PrintParameters(OS); - OS << ");\n"; - } - OS << "\n"; - - OS << "bool TargetSelectInstruction(Instruction *I,\n"; - OS << " " - "DenseMap &ValueMap,\n"; - OS << " " - "DenseMap &MBBMap,\n"; - OS << " " - "MachineBasicBlock *MBB);\n"; - - // Declare the Subtarget member, which is used for predicate checks. - OS << " const " << InstNS.substr(0, InstNS.size() - 2) - << "Subtarget *Subtarget;\n"; - OS << "\n"; - - // Declare the constructor. - OS << "public:\n"; - OS << " explicit FastISel(MachineFunction &mf)\n"; - OS << " : llvm::FastISel(mf),\n"; - OS << " Subtarget(&TM.getSubtarget<" << InstNS.substr(0, InstNS.size() - 2) - << "Subtarget>()) {}\n"; - OS << "};\n"; - OS << "\n"; -} - void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Now emit code for all the patterns that we collected. for (OperandsOpcodeTypeRetPredMap::const_iterator OI = SimplePatterns.begin(), @@ -462,7 +395,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { const PredMap &PM = RI->second; bool HasPred = false; - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_" << getLegalCName(getName(RetVT)) << "_"; @@ -499,7 +432,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { OS << " return FastEmitInst_"; if (Memo.SubRegNo == (unsigned char)~0) { - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); OS << "(" << InstNS << Memo.Name << ", "; OS << InstNS << Memo.RC->getName() << "RegisterClass"; if (!Operands.empty()) @@ -513,7 +446,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } if (HasPred) - OS << "}\n"; + OS << " }\n"; } // Return 0 if none of the predicates were satisfied. @@ -524,7 +457,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } // Emit one function for the type that demultiplexes on return type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; Operands.PrintManglingSuffix(OS); @@ -548,7 +481,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } else { // Non-variadic return type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_" << getLegalCName(getName(VT)) << "_"; Operands.PrintManglingSuffix(OS); @@ -566,7 +499,8 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Emit code for each possible instruction. There may be // multiple if there are subtarget concerns. - for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; ++PI) { + for (PredMap::const_iterator PI = PM.begin(), PE = PM.end(); PI != PE; + ++PI) { std::string PredicateCheck = PI->first; const InstructionMemo &Memo = PI->second; @@ -592,7 +526,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { OS << " return FastEmitInst_"; if (Memo.SubRegNo == (unsigned char)~0) { - Operands.PrintManglingSuffix(OS); + Operands.PrintManglingSuffix(OS, *Memo.PhysRegs); OS << "(" << InstNS << Memo.Name << ", "; OS << InstNS << Memo.RC->getName() << "RegisterClass"; if (!Operands.empty()) @@ -618,7 +552,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { } // Emit one function for the opcode that demultiplexes based on the type. - OS << "unsigned FastISel::FastEmit_" + OS << "unsigned FastEmit_" << getLegalCName(Opcode) << "_"; Operands.PrintManglingSuffix(OS); OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT"; @@ -651,7 +585,7 @@ void FastISelMap::PrintFunctionDefinitions(std::ostream &OS) { // Emit one function for the operand signature that demultiplexes based // on opcode and type. - OS << "unsigned FastISel::FastEmit_"; + OS << "unsigned FastEmit_"; Operands.PrintManglingSuffix(OS); OS << "(MVT::SimpleValueType VT, MVT::SimpleValueType RetVT, ISD::NodeType Opcode"; if (!Operands.empty()) @@ -689,27 +623,9 @@ void FastISelEmitter::run(std::ostream &OS) { EmitSourceFileHeader("\"Fast\" Instruction Selector for the " + Target.getName() + " target", OS); - OS << "#include \"llvm/CodeGen/FastISel.h\"\n"; - OS << "\n"; - OS << "namespace llvm {\n"; - OS << "\n"; - OS << "namespace " << InstNS.substr(0, InstNS.size() - 2) << " {\n"; - OS << "\n"; - FastISelMap F(InstNS); F.CollectPatterns(CGP); - F.PrintClass(OS); F.PrintFunctionDefinitions(OS); - - // Define the target FastISel creation function. - OS << "llvm::FastISel *createFastISel(MachineFunction &mf) {\n"; - OS << " return new FastISel(mf);\n"; - OS << "}\n"; - OS << "\n"; - - OS << "} // namespace X86\n"; - OS << "\n"; - OS << "} // namespace llvm\n"; } FastISelEmitter::FastISelEmitter(RecordKeeper &R)