X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=6201690b10ef75c62daaa5f1fd15d3dcd2aa110e;hb=a62c302ddd79c525d6fac050974911d36662ebfe;hp=3f2b49fda659c2ad873cde5712f44ed8e25b6e57;hpb=5fbe27530415dcacd7afd591c4ba1d6df4374873;p=oota-llvm.git diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 3f2b49fda65..6201690b10e 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -27,6 +27,14 @@ static void PrintDefList(const std::vector &Uses, OS << "0 };\n"; } +static void PrintBarriers(std::vector &Barriers, + unsigned Num, std::ostream &OS) { + OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; + for (unsigned i = 0, e = Barriers.size(); i != e; ++i) + OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; + OS << "NULL };\n"; +} + //===----------------------------------------------------------------------===// // Instruction Itinerary Information. //===----------------------------------------------------------------------===// @@ -94,17 +102,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { // Ptr value whose register class is resolved via callback. if (OpR->getName() == "ptr_rc") - Res += "|M_LOOK_UP_PTR_REG_CLASS"; + Res += "|(1<isSubClassOf("PredicateOperand")) - Res += "|M_PREDICATE_OPERAND"; + Res += "|(1<isSubClassOf("OptionalDefOperand")) - Res += "|M_OPTIONAL_DEF_OPERAND"; + Res += "|(1< &Defs, + const std::vector &RCs, + std::vector &Barriers) { + std::set DefSet; + unsigned NumDefs = Defs.size(); + for (unsigned i = 0; i < NumDefs; ++i) + DefSet.insert(Defs[i]); + + for (unsigned i = 0, e = RCs.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RCs[i]; + unsigned NumRegs = RC.Elements.size(); + if (NumRegs > NumDefs) + continue; // Can't possibly clobber this RC. + + bool Clobber = true; + for (unsigned j = 0; j < NumRegs; ++j) { + Record *Reg = RC.Elements[j]; + if (!DefSet.count(Reg)) { + Clobber = false; + break; + } + } + if (Clobber) + Barriers.push_back(RC.TheDef); + } +} + //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -148,13 +183,17 @@ void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); OS << "namespace llvm {\n\n"; - CodeGenTarget Target; + CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); + const std::vector &RCs = Target.getRegisterClasses(); // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; + std::map, unsigned> EmittedBarriers; + unsigned BarrierNumber = 0; + std::map BarriersMap; // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -167,6 +206,14 @@ void InstrInfoEmitter::run(std::ostream &OS) { } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { + std::vector RCBarriers; + DetectRegisterClassBarriers(Defs, RCs, RCBarriers); + if (!RCBarriers.empty()) { + unsigned &IB = EmittedBarriers[RCBarriers]; + if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); + BarriersMap.insert(std::make_pair(Inst, IB)); + } + unsigned &IL = EmittedLists[Defs]; if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } @@ -177,16 +224,16 @@ void InstrInfoEmitter::run(std::ostream &OS) { // Emit all of the operand info records. EmitOperandInfo(OS, OperandInfoIDs); - // Emit all of the TargetInstrDescriptor records in their ENUM ordering. + // Emit all of the TargetInstrDesc records in their ENUM ordering. // - OS << "\nstatic const TargetInstrDescriptor " << TargetName + OS << "\nstatic const TargetInstrDesc " << TargetName << "Insts[] = {\n"; std::vector NumberedInstructions; Target.getInstructionsByEnumValue(NumberedInstructions); for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - OperandInfoIDs, OS); + BarriersMap, OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -194,67 +241,42 @@ void InstrInfoEmitter::run(std::ostream &OS) { void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, + std::map &BarriersMap, const OperandInfoMapTy &OpInfo, std::ostream &OS) { - int MinOperands; + int MinOperands = 0; if (!Inst.OperandList.empty()) // Each logical operand can be multiple MI operands. MinOperands = Inst.OperandList.back().MIOperandNo + Inst.OperandList.back().MINumOperands; - else - MinOperands = 0; - + OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" - << Inst.NumDefs << ",\t\""; - - if (Inst.Name.empty()) - OS << Inst.TheDef->getName(); - else - OS << Inst.Name; - - OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0"; - - // Try to determine (from the pattern), if the instruction is a store. - bool isStore = false; - if (dynamic_cast(Inst.TheDef->getValueInit("Pattern"))) { - ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern"); - if (LI && LI->getSize() > 0) { - DagInit *Dag = (DagInit *)LI->getElement(0); - DefInit *OpDef = dynamic_cast(Dag->getOperator()); - if (OpDef) { - Record *Operator = OpDef->getDef(); - if (Operator->isSubClassOf("SDNode")) { - const std::string Opcode = Operator->getValueAsString("Opcode"); - if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE") - isStore = true; - } - } - } - } + << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) + << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|M_RET_FLAG"; - if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; - if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; - if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; - if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; - if (Inst.isCall) OS << "|M_CALL_FLAG"; - if (Inst.isLoad) OS << "|M_LOAD_FLAG"; - if (Inst.isStore || isStore) OS << "|M_STORE_FLAG"; - if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG"; - if (Inst.isPredicable) OS << "|M_PREDICABLE"; - if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; - if (Inst.isCommutable) OS << "|M_COMMUTABLE"; - if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; - if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; - if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE"; - if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF"; + if (Inst.isReturn) OS << "|(1<::iterator BI = BarriersMap.find(Inst.TheDef); + if (BI == BarriersMap.end()) + OS << "NULL, "; + else + OS << "Barriers" << BI->second << ", "; + // Emit the operand info. std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) @@ -305,9 +333,14 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, // This isn't an error if this is a builtin instruction. if (R->getName() != "PHI" && R->getName() != "INLINEASM" && - R->getName() != "LABEL" && + R->getName() != "DBG_LABEL" && + R->getName() != "EH_LABEL" && + R->getName() != "GC_LABEL" && + R->getName() != "DECLARE" && R->getName() != "EXTRACT_SUBREG" && - R->getName() != "INSERT_SUBREG") + R->getName() != "INSERT_SUBREG" && + R->getName() != "IMPLICIT_DEF" && + R->getName() != "SUBREG_TO_REG") throw R->getName() + " doesn't have a field named '" + Val->getValue() + "'!"; return;