X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=6201690b10ef75c62daaa5f1fd15d3dcd2aa110e;hb=f45a82890e34984ad1e1e259f8fb902caddfb0b1;hp=40dd1f023e69ce53ffe8620d3e40089b5315771d;hpb=af3eb7c7583555ea5fd08e99f28b0042811e4dc2;p=oota-llvm.git diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 40dd1f023e6..6201690b10e 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -27,6 +27,14 @@ static void PrintDefList(const std::vector &Uses, OS << "0 };\n"; } +static void PrintBarriers(std::vector &Barriers, + unsigned Num, std::ostream &OS) { + OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; + for (unsigned i = 0, e = Barriers.size(); i != e; ++i) + OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; + OS << "NULL };\n"; +} + //===----------------------------------------------------------------------===// // Instruction Itinerary Information. //===----------------------------------------------------------------------===// @@ -94,17 +102,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { // Ptr value whose register class is resolved via callback. if (OpR->getName() == "ptr_rc") - Res += "|TOI::LookupPtrRegClass"; + Res += "|(1<isSubClassOf("PredicateOperand")) - Res += "|TOI::Predicate"; + Res += "|(1<isSubClassOf("OptionalDefOperand")) - Res += "|TOI::OptionalDef"; + Res += "|(1<getTree(0)); - } - -private: - void AnalyzeNode(const TreePatternNode *N) { - if (N->isLeaf()) { - return; - } - - if (N->getOperator()->getName() != "set") { - // Get information about the SDNode for the operator. - const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); - - // If node writes to memory, it obviously stores to memory. - if (OpInfo.hasProperty(SDNPMayStore)) { - mayStore = true; - } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { - // If this is an intrinsic, analyze it. - if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) - mayStore = true;// Intrinsics that can write to memory are 'mayStore'. +void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector &Defs, + const std::vector &RCs, + std::vector &Barriers) { + std::set DefSet; + unsigned NumDefs = Defs.size(); + for (unsigned i = 0; i < NumDefs; ++i) + DefSet.insert(Defs[i]); + + for (unsigned i = 0, e = RCs.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RCs[i]; + unsigned NumRegs = RC.Elements.size(); + if (NumRegs > NumDefs) + continue; // Can't possibly clobber this RC. + + bool Clobber = true; + for (unsigned j = 0; j < NumRegs; ++j) { + Record *Reg = RC.Elements[j]; + if (!DefSet.count(Reg)) { + Clobber = false; + break; } } - - for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) - AnalyzeNode(N->getChild(i)); + if (Clobber) + Barriers.push_back(RC.TheDef); } - -}; - -void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, - bool &mayStore, bool &isLoad, - bool &NeverHasSideEffects) { - mayStore = isLoad = NeverHasSideEffects = false; - - InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef); - - // InstAnalyzer only correctly analyzes mayStore so far. - if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it. - // If we decided that this is a store from the pattern, then the .td file - // entry is redundant. - if (mayStore) - fprintf(stderr, - "Warning: mayStore flag explicitly set on instruction '%s'" - " but flag already inferred from pattern.\n", - Inst.TheDef->getName().c_str()); - mayStore = true; - } - - // These two override everything. - isLoad = Inst.isSimpleLoad; - NeverHasSideEffects = Inst.neverHasSideEffects; - -#if 0 - // If the .td file explicitly says there is no side effect, believe it. - if (Inst.neverHasSideEffects) - NeverHasSideEffects = true; -#endif } - //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -232,13 +183,17 @@ void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); OS << "namespace llvm {\n\n"; - CodeGenTarget Target; + CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); + const std::vector &RCs = Target.getRegisterClasses(); // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; + std::map, unsigned> EmittedBarriers; + unsigned BarrierNumber = 0; + std::map BarriersMap; // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -251,6 +206,14 @@ void InstrInfoEmitter::run(std::ostream &OS) { } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { + std::vector RCBarriers; + DetectRegisterClassBarriers(Defs, RCs, RCBarriers); + if (!RCBarriers.empty()) { + unsigned &IB = EmittedBarriers[RCBarriers]; + if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); + BarriersMap.insert(std::make_pair(Inst, IB)); + } + unsigned &IL = EmittedLists[Defs]; if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } @@ -261,16 +224,16 @@ void InstrInfoEmitter::run(std::ostream &OS) { // Emit all of the operand info records. EmitOperandInfo(OS, OperandInfoIDs); - // Emit all of the TargetInstrDescriptor records in their ENUM ordering. + // Emit all of the TargetInstrDesc records in their ENUM ordering. // - OS << "\nstatic const TargetInstrDescriptor " << TargetName + OS << "\nstatic const TargetInstrDesc " << TargetName << "Insts[] = {\n"; std::vector NumberedInstructions; Target.getInstructionsByEnumValue(NumberedInstructions); for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - OperandInfoIDs, OS); + BarriersMap, OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -278,51 +241,42 @@ void InstrInfoEmitter::run(std::ostream &OS) { void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, + std::map &BarriersMap, const OperandInfoMapTy &OpInfo, std::ostream &OS) { - // Determine properties of the instruction from its pattern. - bool mayStore, isLoad, NeverHasSideEffects; - InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects); - - if (NeverHasSideEffects && Inst.mayHaveSideEffects) { - std::cerr << "error: Instruction '" << Inst.TheDef->getName() - << "' is marked with 'mayHaveSideEffects', but it can never have them!\n"; - exit(1); - } - int MinOperands = 0; if (!Inst.OperandList.empty()) // Each logical operand can be multiple MI operands. MinOperands = Inst.OperandList.back().MIOperandNo + Inst.OperandList.back().MINumOperands; - + OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" - << Inst.NumDefs << ",\t\"" << Inst.TheDef->getName(); - OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0"; + << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) + << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|M_RET_FLAG"; - if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; - if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; - if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; - if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; - if (Inst.isCall) OS << "|M_CALL_FLAG"; - if (isLoad) OS << "|M_SIMPLE_LOAD_FLAG"; - if (mayStore) OS << "|M_MAY_STORE_FLAG"; - if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG"; - if (Inst.isPredicable) OS << "|M_PREDICABLE"; - if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; - if (Inst.isCommutable) OS << "|M_COMMUTABLE"; - if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; - if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; - if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE"; - if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF"; + if (Inst.isReturn) OS << "|(1<::iterator BI = BarriersMap.find(Inst.TheDef); + if (BI == BarriersMap.end()) + OS << "NULL, "; + else + OS << "Barriers" << BI->second << ", "; + // Emit the operand info. std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) @@ -373,9 +333,14 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, // This isn't an error if this is a builtin instruction. if (R->getName() != "PHI" && R->getName() != "INLINEASM" && - R->getName() != "LABEL" && + R->getName() != "DBG_LABEL" && + R->getName() != "EH_LABEL" && + R->getName() != "GC_LABEL" && + R->getName() != "DECLARE" && R->getName() != "EXTRACT_SUBREG" && - R->getName() != "INSERT_SUBREG") + R->getName() != "INSERT_SUBREG" && + R->getName() != "IMPLICIT_DEF" && + R->getName() != "SUBREG_TO_REG") throw R->getName() + " doesn't have a field named '" + Val->getValue() + "'!"; return;