X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=6201690b10ef75c62daaa5f1fd15d3dcd2aa110e;hb=f45a82890e34984ad1e1e259f8fb902caddfb0b1;hp=66d17cb86bb8cdbaf29eba682034ad291cfc7c51;hpb=21d03f2de0087d60dbf575d95924404a97852879;p=oota-llvm.git

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 66d17cb86bb..6201690b10e 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -16,78 +16,165 @@
 #include "CodeGenTarget.h"
 #include "Record.h"
 #include <algorithm>
+#include <iostream>
 using namespace llvm;
 
-// runEnums - Print out enum values for all of the instructions.
-void InstrInfoEmitter::runEnums(std::ostream &OS) {
-  EmitSourceFileHeader("Target Instruction Enum Values", OS);
-  OS << "namespace llvm {\n\n";
-
-  CodeGenTarget Target;
+static void PrintDefList(const std::vector<Record*> &Uses,
+                         unsigned Num, std::ostream &OS) {
+  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
+  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
+    OS << getQualifiedName(Uses[i]) << ", ";
+  OS << "0 };\n";
+}
 
-  // We must emit the PHI opcode first...
-  std::string Namespace;
-  for (CodeGenTarget::inst_iterator II = Target.inst_begin(), 
-       E = Target.inst_end(); II != E; ++II) {
-    if (II->second.Namespace != "TargetInstrInfo") {
-      Namespace = II->second.Namespace;
-      break;
-    }
-  }
-  
-  if (Namespace.empty()) {
-    std::cerr << "No instructions defined!\n";
-    exit(1);
-  }
+static void PrintBarriers(std::vector<Record*> &Barriers,
+                          unsigned Num, std::ostream &OS) {
+  OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
+  for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
+    OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
+  OS << "NULL };\n";
+}
 
-  std::vector<const CodeGenInstruction*> NumberedInstructions;
-  Target.getInstructionsByEnumValue(NumberedInstructions);
+//===----------------------------------------------------------------------===//
+// Instruction Itinerary Information.
+//===----------------------------------------------------------------------===//
 
-  OS << "namespace " << Namespace << " {\n";
-  OS << "  enum {\n";
-  for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) {
-    OS << "    " << NumberedInstructions[i]->TheDef->getName()
-       << "\t= " << i << ",\n";
+struct RecordNameComparator {
+  bool operator()(const Record *Rec1, const Record *Rec2) const {
+    return Rec1->getName() < Rec2->getName();
   }
-  OS << "    INSTRUCTION_LIST_END = " << NumberedInstructions.size() << "\n";
-  OS << "  };\n}\n";
-  OS << "} // End llvm namespace \n";
-}
+};
 
-void InstrInfoEmitter::printDefList(const std::vector<Record*> &Uses,
-                                    unsigned Num, std::ostream &OS) const {
-  OS << "static const unsigned ImplicitList" << Num << "[] = { ";
-  for (unsigned i = 0, e = Uses.size(); i != e; ++i)
-    OS << getQualifiedName(Uses[i]) << ", ";
-  OS << "0 };\n";
+void InstrInfoEmitter::GatherItinClasses() {
+  std::vector<Record*> DefList =
+  Records.getAllDerivedDefinitions("InstrItinClass");
+  std::sort(DefList.begin(), DefList.end(), RecordNameComparator());
+  
+  for (unsigned i = 0, N = DefList.size(); i < N; i++)
+    ItinClassMap[DefList[i]->getName()] = i;
+}  
+
+unsigned InstrInfoEmitter::getItinClassNumber(const Record *InstRec) {
+  return ItinClassMap[InstRec->getValueAsDef("Itinerary")->getName()];
 }
 
-static std::vector<Record*> GetOperandInfo(const CodeGenInstruction &Inst) {
-  std::vector<Record*> Result;
-  if (Inst.hasVariableNumberOfOperands)
-    return Result;  // No info for variable operand instrs.
+//===----------------------------------------------------------------------===//
+// Operand Info Emission.
+//===----------------------------------------------------------------------===//
 
+std::vector<std::string>
+InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
+  std::vector<std::string> Result;
+  
   for (unsigned i = 0, e = Inst.OperandList.size(); i != e; ++i) {
-    if (Inst.OperandList[i].Rec->isSubClassOf("RegisterClass")) {
-      Result.push_back(Inst.OperandList[i].Rec);
+    // Handle aggregate operands and normal operands the same way by expanding
+    // either case into a list of operands for this op.
+    std::vector<CodeGenInstruction::OperandInfo> OperandList;
+
+    // This might be a multiple operand thing.  Targets like X86 have
+    // registers in their multi-operand operands.  It may also be an anonymous
+    // operand, which has a single operand, but no declared class for the
+    // operand.
+    DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
+    
+    if (!MIOI || MIOI->getNumArgs() == 0) {
+      // Single, anonymous, operand.
+      OperandList.push_back(Inst.OperandList[i]);
     } else {
-      // This might be a multiple operand thing.
-      // Targets like X86 have registers in their multi-operand operands.
-      DagInit *MIOI = Inst.OperandList[i].MIOperandInfo;
-      unsigned NumDefs = MIOI->getNumArgs();
       for (unsigned j = 0, e = Inst.OperandList[i].MINumOperands; j != e; ++j) {
-        if (NumDefs <= j) {
-          Result.push_back(0);
-        } else {
-          DefInit *Def = dynamic_cast<DefInit*>(MIOI->getArg(j));
-          Result.push_back(Def ? Def->getDef() : 0);
-        }
+        OperandList.push_back(Inst.OperandList[i]);
+
+        Record *OpR = dynamic_cast<DefInit*>(MIOI->getArg(j))->getDef();
+        OperandList.back().Rec = OpR;
       }
     }
+
+    for (unsigned j = 0, e = OperandList.size(); j != e; ++j) {
+      Record *OpR = OperandList[j].Rec;
+      std::string Res;
+      
+      if (OpR->isSubClassOf("RegisterClass"))
+        Res += getQualifiedName(OpR) + "RegClassID, ";
+      else
+        Res += "0, ";
+      // Fill in applicable flags.
+      Res += "0";
+        
+      // Ptr value whose register class is resolved via callback.
+      if (OpR->getName() == "ptr_rc")
+        Res += "|(1<<TOI::LookupPtrRegClass)";
+
+      // Predicate operands.  Check to see if the original unexpanded operand
+      // was of type PredicateOperand.
+      if (Inst.OperandList[i].Rec->isSubClassOf("PredicateOperand"))
+        Res += "|(1<<TOI::Predicate)";
+        
+      // Optional def operands.  Check to see if the original unexpanded operand
+      // was of type OptionalDefOperand.
+      if (Inst.OperandList[i].Rec->isSubClassOf("OptionalDefOperand"))
+        Res += "|(1<<TOI::OptionalDef)";
+
+      // Fill in constraint info.
+      Res += ", " + Inst.OperandList[i].Constraints[j];
+      Result.push_back(Res);
+    }
   }
+
   return Result;
 }
 
+void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS, 
+                                       OperandInfoMapTy &OperandInfoIDs) {
+  // ID #0 is for no operand info.
+  unsigned OperandListNum = 0;
+  OperandInfoIDs[std::vector<std::string>()] = ++OperandListNum;
+  
+  OS << "\n";
+  const CodeGenTarget &Target = CDP.getTargetInfo();
+  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
+       E = Target.inst_end(); II != E; ++II) {
+    std::vector<std::string> OperandInfo = GetOperandInfo(II->second);
+    unsigned &N = OperandInfoIDs[OperandInfo];
+    if (N != 0) continue;
+    
+    N = ++OperandListNum;
+    OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
+    for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i)
+      OS << "{ " << OperandInfo[i] << " }, ";
+    OS << "};\n";
+  }
+}
+
+void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
+                                  const std::vector<CodeGenRegisterClass> &RCs,
+                                  std::vector<Record*> &Barriers) {
+  std::set<Record*> DefSet;
+  unsigned NumDefs = Defs.size();
+  for (unsigned i = 0; i < NumDefs; ++i)
+    DefSet.insert(Defs[i]);
+
+  for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+    const CodeGenRegisterClass &RC = RCs[i];
+    unsigned NumRegs = RC.Elements.size();
+    if (NumRegs > NumDefs)
+      continue; // Can't possibly clobber this RC.
+
+    bool Clobber = true;
+    for (unsigned j = 0; j < NumRegs; ++j) {
+      Record *Reg = RC.Elements[j];
+      if (!DefSet.count(Reg)) {
+        Clobber = false;
+        break;
+      }
+    }
+    if (Clobber)
+      Barriers.push_back(RC.TheDef);
+  }
+}
+
+//===----------------------------------------------------------------------===//
+// Main Output.
+//===----------------------------------------------------------------------===//
 
 // run - Emit the main instruction description records for the target...
 void InstrInfoEmitter::run(std::ostream &OS) {
@@ -96,16 +183,17 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   EmitSourceFileHeader("Target Instruction Descriptors", OS);
   OS << "namespace llvm {\n\n";
 
-  CodeGenTarget Target;
+  CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
-
-  // Emit empty implicit uses and defs lists
-  OS << "static const unsigned EmptyImpList[] = { 0 };\n";
+  const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
+  std::map<std::vector<Record*>, unsigned> EmittedBarriers;
+  unsigned BarrierNumber = 0;
+  std::map<Record*, unsigned> BarriersMap;
  
   // Emit all of the instruction's implicit uses and defs.
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
@@ -114,53 +202,38 @@ void InstrInfoEmitter::run(std::ostream &OS) {
     std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
     if (!Uses.empty()) {
       unsigned &IL = EmittedLists[Uses];
-      if (!IL) printDefList(Uses, IL = ++ListNumber, OS);
+      if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
     }
     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
     if (!Defs.empty()) {
+      std::vector<Record*> RCBarriers;
+      DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
+      if (!RCBarriers.empty()) {
+        unsigned &IB = EmittedBarriers[RCBarriers];
+        if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
+        BarriersMap.insert(std::make_pair(Inst, IB));
+      }
+
       unsigned &IL = EmittedLists[Defs];
-      if (!IL) printDefList(Defs, IL = ++ListNumber, OS);
+      if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
     }
   }
 
-  std::map<std::vector<Record*>, unsigned> OperandInfosEmitted;
-  unsigned OperandListNum = 0;
-  OperandInfosEmitted[std::vector<Record*>()] = ++OperandListNum;
+  OperandInfoMapTy OperandInfoIDs;
   
   // Emit all of the operand info records.
-  OS << "\n";
-  for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
-       E = Target.inst_end(); II != E; ++II) {
-    std::vector<Record*> OperandInfo = GetOperandInfo(II->second);
-    unsigned &N = OperandInfosEmitted[OperandInfo];
-    if (N == 0) {
-      N = ++OperandListNum;
-      OS << "static const TargetOperandInfo OperandInfo" << N << "[] = { ";
-      for (unsigned i = 0, e = OperandInfo.size(); i != e; ++i) {
-        Record *RC = OperandInfo[i];
-        // FIXME: We only care about register operands for now.
-        if (RC && RC->isSubClassOf("RegisterClass"))
-          OS << "{ &" << getQualifiedName(RC) << "RegClass, 0 }, ";
-        else if (RC && RC->getName() == "ptr_rc")
-          // Ptr value whose register class is resolved via callback.
-          OS << "{ 0, 1 }, ";
-        else
-          OS << "{ 0, 0 }, ";
-      }
-      OS << "};\n";
-    }
-  }
+  EmitOperandInfo(OS, OperandInfoIDs);
   
-  // Emit all of the TargetInstrDescriptor records in their ENUM ordering.
+  // Emit all of the TargetInstrDesc records in their ENUM ordering.
   //
-  OS << "\nstatic const TargetInstrDescriptor " << TargetName
+  OS << "\nstatic const TargetInstrDesc " << TargetName
      << "Insts[] = {\n";
   std::vector<const CodeGenInstruction*> NumberedInstructions;
   Target.getInstructionsByEnumValue(NumberedInstructions);
 
   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
     emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
-               OperandInfosEmitted, OS);
+               BarriersMap, OperandInfoIDs, OS);
   OS << "};\n";
   OS << "} // End llvm namespace \n";
 }
@@ -168,62 +241,42 @@ void InstrInfoEmitter::run(std::ostream &OS) {
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
-                               std::map<std::vector<Record*>, unsigned> &OpInfo,
+                                  std::map<Record*, unsigned> &BarriersMap,
+                                  const OperandInfoMapTy &OpInfo,
                                   std::ostream &OS) {
-  int NumOperands;
-  if (Inst.hasVariableNumberOfOperands)
-    NumOperands = -1;
-  else if (!Inst.OperandList.empty())
+  int MinOperands = 0;
+  if (!Inst.OperandList.empty())
     // Each logical operand can be multiple MI operands.
-    NumOperands = Inst.OperandList.back().MIOperandNo +
+    MinOperands = Inst.OperandList.back().MIOperandNo +
                   Inst.OperandList.back().MINumOperands;
-  else
-    NumOperands = 0;
-  
-  OS << "  { \"";
-  if (Inst.Name.empty())
-    OS << Inst.TheDef->getName();
-  else
-    OS << Inst.Name;
-  
-  unsigned ItinClass = !IsItineraries ? 0 :
-            ItinClassNumber(Inst.TheDef->getValueAsDef("Itinerary")->getName());
-  
-  OS << "\",\t" << NumOperands << ", " << ItinClass
-     << ", 0";
-
-  // Try to determine (from the pattern), if the instruction is a store.
-  bool isStore = false;
-  if (dynamic_cast<ListInit*>(Inst.TheDef->getValueInit("Pattern"))) {
-    ListInit *LI = Inst.TheDef->getValueAsListInit("Pattern");
-    if (LI && LI->getSize() > 0) {
-      DagInit *Dag = (DagInit *)LI->getElement(0);
-      DefInit *OpDef = dynamic_cast<DefInit*>(Dag->getOperator());
-      if (OpDef) {
-        Record *Operator = OpDef->getDef();
-        if (Operator->isSubClassOf("SDNode")) {
-          const std::string Opcode = Operator->getValueAsString("Opcode");
-          if (Opcode == "ISD::STORE" || Opcode == "ISD::TRUNCSTORE")
-            isStore = true;
-        }
-      }
-    }
-  }
+
+  OS << "  { ";
+  OS << Num << ",\t" << MinOperands << ",\t"
+     << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
+     << ",\t\"" << Inst.TheDef->getName() << "\", 0";
 
   // Emit all of the target indepedent flags...
-  if (Inst.isReturn)     OS << "|M_RET_FLAG";
-  if (Inst.isBranch)     OS << "|M_BRANCH_FLAG";
-  if (Inst.isBarrier)    OS << "|M_BARRIER_FLAG";
-  if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG";
-  if (Inst.isCall)       OS << "|M_CALL_FLAG";
-  if (Inst.isLoad)       OS << "|M_LOAD_FLAG";
-  if (Inst.isStore || isStore) OS << "|M_STORE_FLAG";
-  if (Inst.isTwoAddress) OS << "|M_2_ADDR_FLAG";
-  if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR";
-  if (Inst.isCommutable) OS << "|M_COMMUTABLE";
-  if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG";
+  if (Inst.isReturn)           OS << "|(1<<TID::Return)";
+  if (Inst.isBranch)           OS << "|(1<<TID::Branch)";
+  if (Inst.isIndirectBranch)   OS << "|(1<<TID::IndirectBranch)";
+  if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
+  if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
+  if (Inst.isCall)             OS << "|(1<<TID::Call)";
+  if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
+  if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
+  if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
+  if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";
+  if (Inst.isConvertibleToThreeAddress) OS << "|(1<<TID::ConvertibleTo3Addr)";
+  if (Inst.isCommutable)       OS << "|(1<<TID::Commutable)";
+  if (Inst.isTerminator)       OS << "|(1<<TID::Terminator)";
+  if (Inst.isReMaterializable) OS << "|(1<<TID::Rematerializable)";
+  if (Inst.isNotDuplicable)    OS << "|(1<<TID::NotDuplicable)";
+  if (Inst.hasOptionalDef)     OS << "|(1<<TID::HasOptionalDef)";
   if (Inst.usesCustomDAGSchedInserter)
-    OS << "|M_USES_CUSTOM_DAG_SCHED_INSERTION";
+    OS << "|(1<<TID::UsesCustomDAGSchedInserter)";
+  if (Inst.isVariadic)         OS << "|(1<<TID::Variadic)";
+  if (Inst.hasSideEffects)     OS << "|(1<<TID::UnmodeledSideEffects)";
+  if (Inst.isAsCheapAsAMove)   OS << "|(1<<TID::CheapAsAMove)";
   OS << ", 0";
 
   // Emit all of the target-specific flags...
@@ -242,49 +295,32 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   // Emit the implicit uses and defs lists...
   std::vector<Record*> UseList = Inst.TheDef->getValueAsListOfDefs("Uses");
   if (UseList.empty())
-    OS << "EmptyImpList, ";
+    OS << "NULL, ";
   else
     OS << "ImplicitList" << EmittedLists[UseList] << ", ";
 
   std::vector<Record*> DefList = Inst.TheDef->getValueAsListOfDefs("Defs");
   if (DefList.empty())
-    OS << "EmptyImpList, ";
+    OS << "NULL, ";
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
+  std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
+  if (BI == BarriersMap.end())
+    OS << "NULL, ";
+  else
+    OS << "Barriers" << BI->second << ", ";
+
   // Emit the operand info.
-  std::vector<Record*> OperandInfo = GetOperandInfo(Inst);
+  std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
     OS << "0";
   else
-    OS << "OperandInfo" << OpInfo[OperandInfo];
+    OS << "OperandInfo" << OpInfo.find(OperandInfo)->second;
   
   OS << " },  // Inst #" << Num << " = " << Inst.TheDef->getName() << "\n";
 }
 
-struct LessRecord {
-  bool operator()(const Record *Rec1, const Record *Rec2) const {
-    return Rec1->getName() < Rec2->getName();
-  }
-};
-void InstrInfoEmitter::GatherItinClasses() {
-  std::vector<Record*> DefList =
-                          Records.getAllDerivedDefinitions("InstrItinClass");
-  IsItineraries = !DefList.empty();
-  
-  if (!IsItineraries) return;
-  
-  std::sort(DefList.begin(), DefList.end(), LessRecord());
-
-  for (unsigned i = 0, N = DefList.size(); i < N; i++) {
-    Record *Def = DefList[i];
-    ItinClassMap[Def->getName()] = i;
-  }
-}  
-  
-unsigned InstrInfoEmitter::ItinClassNumber(std::string ItinName) {
-  return ItinClassMap[ItinName];
-}
 
 void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
                                         IntInit *ShiftInt, std::ostream &OS) {
@@ -295,7 +331,16 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
 
   if (RV == 0 || RV->getValue() == 0) {
     // This isn't an error if this is a builtin instruction.
-    if (R->getName() != "PHI" && R->getName() != "INLINEASM")
+    if (R->getName() != "PHI" &&
+        R->getName() != "INLINEASM" &&
+        R->getName() != "DBG_LABEL" &&
+        R->getName() != "EH_LABEL" &&
+        R->getName() != "GC_LABEL" &&
+        R->getName() != "DECLARE" &&
+        R->getName() != "EXTRACT_SUBREG" &&
+        R->getName() != "INSERT_SUBREG" &&
+        R->getName() != "IMPLICIT_DEF" &&
+        R->getName() != "SUBREG_TO_REG")
       throw R->getName() + " doesn't have a field named '" + 
             Val->getValue() + "'!";
     return;