X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=6201690b10ef75c62daaa5f1fd15d3dcd2aa110e;hb=f45a82890e34984ad1e1e259f8fb902caddfb0b1;hp=7f25f3c462ca1178e3f7619e1eed8d7d5c993a08;hpb=bc0b9f70ae072d695e0eb7ceb729b3306b0679fe;p=oota-llvm.git diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 7f25f3c462c..6201690b10e 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -27,6 +27,14 @@ static void PrintDefList(const std::vector &Uses, OS << "0 };\n"; } +static void PrintBarriers(std::vector &Barriers, + unsigned Num, std::ostream &OS) { + OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { "; + for (unsigned i = 0, e = Barriers.size(); i != e; ++i) + OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, "; + OS << "NULL };\n"; +} + //===----------------------------------------------------------------------===// // Instruction Itinerary Information. //===----------------------------------------------------------------------===// @@ -137,117 +145,33 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS, } } -//===----------------------------------------------------------------------===// -// Instruction Analysis -//===----------------------------------------------------------------------===// - -class InstAnalyzer { - const CodeGenDAGPatterns &CDP; - bool &mayStore; - bool &mayLoad; - bool &HasSideEffects; -public: - InstAnalyzer(const CodeGenDAGPatterns &cdp, - bool &maystore, bool &mayload, bool &hse) - : CDP(cdp), mayStore(maystore), mayLoad(mayload), HasSideEffects(hse){ - } - - void Analyze(Record *InstRecord) { - const TreePattern *Pattern = CDP.getInstruction(InstRecord).getPattern(); - if (Pattern == 0) return; // No pattern. - - // FIXME: Assume only the first tree is the pattern. The others are clobber - // nodes. - AnalyzeNode(Pattern->getTree(0)); - } - -private: - void AnalyzeNode(const TreePatternNode *N) { - if (N->isLeaf()) - return; - - // Analyze children. - for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) - AnalyzeNode(N->getChild(i)); - - // Ignore set nodes, which are not SDNodes. - if (N->getOperator()->getName() == "set") - return; - - // Get information about the SDNode for the operator. - const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); - - // If node writes to memory, it obviously stores to memory. - if (OpInfo.hasProperty(SDNPMayStore)) - mayStore = true; - - // If it reads memory, remember this. - if (OpInfo.hasProperty(SDNPMayLoad)) - mayLoad = true; - - // If it reads memory, remember this. - if (OpInfo.hasProperty(SDNPSideEffect)) - HasSideEffects = true; - - if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { - // If this is an intrinsic, analyze it. - if (IntInfo->ModRef >= CodeGenIntrinsic::ReadArgMem) - mayLoad = true;// These may load memory. - - if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) - mayStore = true;// Intrinsics that can write to memory are 'mayStore'. - - if (IntInfo->ModRef >= CodeGenIntrinsic::WriteMem) - // WriteMem intrinsics can have other strange effects. - HasSideEffects = true; +void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector &Defs, + const std::vector &RCs, + std::vector &Barriers) { + std::set DefSet; + unsigned NumDefs = Defs.size(); + for (unsigned i = 0; i < NumDefs; ++i) + DefSet.insert(Defs[i]); + + for (unsigned i = 0, e = RCs.size(); i != e; ++i) { + const CodeGenRegisterClass &RC = RCs[i]; + unsigned NumRegs = RC.Elements.size(); + if (NumRegs > NumDefs) + continue; // Can't possibly clobber this RC. + + bool Clobber = true; + for (unsigned j = 0; j < NumRegs; ++j) { + Record *Reg = RC.Elements[j]; + if (!DefSet.count(Reg)) { + Clobber = false; + break; + } } - } - -}; - -void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, - bool &MayStore, bool &MayLoad, - bool &HasSideEffects) { - MayStore = MayLoad = HasSideEffects = false; - - InstAnalyzer(CDP, MayStore, MayLoad, HasSideEffects).Analyze(Inst.TheDef); - - // InstAnalyzer only correctly analyzes mayStore/mayLoad so far. - if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it. - // If we decided that this is a store from the pattern, then the .td file - // entry is redundant. - if (MayStore) - fprintf(stderr, - "Warning: mayStore flag explicitly set on instruction '%s'" - " but flag already inferred from pattern.\n", - Inst.TheDef->getName().c_str()); - MayStore = true; - } - - if (Inst.mayLoad) { // If the .td file explicitly sets mayLoad, use it. - // If we decided that this is a load from the pattern, then the .td file - // entry is redundant. - if (MayLoad) - fprintf(stderr, - "Warning: mayLoad flag explicitly set on instruction '%s'" - " but flag already inferred from pattern.\n", - Inst.TheDef->getName().c_str()); - MayLoad = true; - } - - if (Inst.neverHasSideEffects) { - // If we already decided that this instruction has no side effects, then the - // .td file entry is redundant. - if (!HasSideEffects) - fprintf(stderr, - "Warning: neverHasSideEffects flag explicitly set on instruction" - " '%s' but flag already inferred from pattern.\n", - Inst.TheDef->getName().c_str()); - HasSideEffects = false; + if (Clobber) + Barriers.push_back(RC.TheDef); } } - //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -259,13 +183,17 @@ void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); OS << "namespace llvm {\n\n"; - CodeGenTarget Target; + CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); + const std::vector &RCs = Target.getRegisterClasses(); // Keep track of all of the def lists we have emitted already. std::map, unsigned> EmittedLists; unsigned ListNumber = 0; + std::map, unsigned> EmittedBarriers; + unsigned BarrierNumber = 0; + std::map BarriersMap; // Emit all of the instruction's implicit uses and defs. for (CodeGenTarget::inst_iterator II = Target.inst_begin(), @@ -278,6 +206,14 @@ void InstrInfoEmitter::run(std::ostream &OS) { } std::vector Defs = Inst->getValueAsListOfDefs("Defs"); if (!Defs.empty()) { + std::vector RCBarriers; + DetectRegisterClassBarriers(Defs, RCs, RCBarriers); + if (!RCBarriers.empty()) { + unsigned &IB = EmittedBarriers[RCBarriers]; + if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS); + BarriersMap.insert(std::make_pair(Inst, IB)); + } + unsigned &IL = EmittedLists[Defs]; if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS); } @@ -297,7 +233,7 @@ void InstrInfoEmitter::run(std::ostream &OS) { for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i) emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists, - OperandInfoIDs, OS); + BarriersMap, OperandInfoIDs, OS); OS << "};\n"; OS << "} // End llvm namespace \n"; } @@ -305,46 +241,42 @@ void InstrInfoEmitter::run(std::ostream &OS) { void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, Record *InstrInfo, std::map, unsigned> &EmittedLists, + std::map &BarriersMap, const OperandInfoMapTy &OpInfo, std::ostream &OS) { - // Determine properties of the instruction from its pattern. - bool mayStore, mayLoad, HasSideEffects; - InferFromPattern(Inst, mayStore, mayLoad, HasSideEffects); - int MinOperands = 0; if (!Inst.OperandList.empty()) // Each logical operand can be multiple MI operands. MinOperands = Inst.OperandList.back().MIOperandNo + Inst.OperandList.back().MINumOperands; - + OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|(1<::iterator BI = BarriersMap.find(Inst.TheDef); + if (BI == BarriersMap.end()) + OS << "NULL, "; + else + OS << "Barriers" << BI->second << ", "; + // Emit the operand info. std::vector OperandInfo = GetOperandInfo(Inst); if (OperandInfo.empty()) @@ -395,9 +333,14 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val, // This isn't an error if this is a builtin instruction. if (R->getName() != "PHI" && R->getName() != "INLINEASM" && - R->getName() != "LABEL" && + R->getName() != "DBG_LABEL" && + R->getName() != "EH_LABEL" && + R->getName() != "GC_LABEL" && + R->getName() != "DECLARE" && R->getName() != "EXTRACT_SUBREG" && - R->getName() != "INSERT_SUBREG") + R->getName() != "INSERT_SUBREG" && + R->getName() != "IMPLICIT_DEF" && + R->getName() != "SUBREG_TO_REG") throw R->getName() + " doesn't have a field named '" + Val->getValue() + "'!"; return;