X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=6201690b10ef75c62daaa5f1fd15d3dcd2aa110e;hb=f45a82890e34984ad1e1e259f8fb902caddfb0b1;hp=8390c90660426bbb3b5517ac00b4572ca48781c9;hpb=d35121ad00667d93ea779a722dbee7d022410815;p=oota-llvm.git

diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index 8390c906604..6201690b10e 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -27,6 +27,14 @@ static void PrintDefList(const std::vector<Record*> &Uses,
   OS << "0 };\n";
 }
 
+static void PrintBarriers(std::vector<Record*> &Barriers,
+                          unsigned Num, std::ostream &OS) {
+  OS << "static const TargetRegisterClass* Barriers" << Num << "[] = { ";
+  for (unsigned i = 0, e = Barriers.size(); i != e; ++i)
+    OS << "&" << getQualifiedName(Barriers[i]) << "RegClass, ";
+  OS << "NULL };\n";
+}
+
 //===----------------------------------------------------------------------===//
 // Instruction Itinerary Information.
 //===----------------------------------------------------------------------===//
@@ -85,10 +93,6 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) {
       Record *OpR = OperandList[j].Rec;
       std::string Res;
       
-      // Discard "discard" operands.
-      if (OpR->getName() == "discard")
-        continue;
-
       if (OpR->isSubClassOf("RegisterClass"))
         Res += getQualifiedName(OpR) + "RegClassID, ";
       else
@@ -141,6 +145,33 @@ void InstrInfoEmitter::EmitOperandInfo(std::ostream &OS,
   }
 }
 
+void InstrInfoEmitter::DetectRegisterClassBarriers(std::vector<Record*> &Defs,
+                                  const std::vector<CodeGenRegisterClass> &RCs,
+                                  std::vector<Record*> &Barriers) {
+  std::set<Record*> DefSet;
+  unsigned NumDefs = Defs.size();
+  for (unsigned i = 0; i < NumDefs; ++i)
+    DefSet.insert(Defs[i]);
+
+  for (unsigned i = 0, e = RCs.size(); i != e; ++i) {
+    const CodeGenRegisterClass &RC = RCs[i];
+    unsigned NumRegs = RC.Elements.size();
+    if (NumRegs > NumDefs)
+      continue; // Can't possibly clobber this RC.
+
+    bool Clobber = true;
+    for (unsigned j = 0; j < NumRegs; ++j) {
+      Record *Reg = RC.Elements[j];
+      if (!DefSet.count(Reg)) {
+        Clobber = false;
+        break;
+      }
+    }
+    if (Clobber)
+      Barriers.push_back(RC.TheDef);
+  }
+}
+
 //===----------------------------------------------------------------------===//
 // Main Output.
 //===----------------------------------------------------------------------===//
@@ -155,10 +186,14 @@ void InstrInfoEmitter::run(std::ostream &OS) {
   CodeGenTarget &Target = CDP.getTargetInfo();
   const std::string &TargetName = Target.getName();
   Record *InstrInfo = Target.getInstructionSet();
+  const std::vector<CodeGenRegisterClass> &RCs = Target.getRegisterClasses();
 
   // Keep track of all of the def lists we have emitted already.
   std::map<std::vector<Record*>, unsigned> EmittedLists;
   unsigned ListNumber = 0;
+  std::map<std::vector<Record*>, unsigned> EmittedBarriers;
+  unsigned BarrierNumber = 0;
+  std::map<Record*, unsigned> BarriersMap;
  
   // Emit all of the instruction's implicit uses and defs.
   for (CodeGenTarget::inst_iterator II = Target.inst_begin(),
@@ -171,6 +206,14 @@ void InstrInfoEmitter::run(std::ostream &OS) {
     }
     std::vector<Record*> Defs = Inst->getValueAsListOfDefs("Defs");
     if (!Defs.empty()) {
+      std::vector<Record*> RCBarriers;
+      DetectRegisterClassBarriers(Defs, RCs, RCBarriers);
+      if (!RCBarriers.empty()) {
+        unsigned &IB = EmittedBarriers[RCBarriers];
+        if (!IB) PrintBarriers(RCBarriers, IB = ++BarrierNumber, OS);
+        BarriersMap.insert(std::make_pair(Inst, IB));
+      }
+
       unsigned &IL = EmittedLists[Defs];
       if (!IL) PrintDefList(Defs, IL = ++ListNumber, OS);
     }
@@ -190,7 +233,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
 
   for (unsigned i = 0, e = NumberedInstructions.size(); i != e; ++i)
     emitRecord(*NumberedInstructions[i], i, InstrInfo, EmittedLists,
-               OperandInfoIDs, OS);
+               BarriersMap, OperandInfoIDs, OS);
   OS << "};\n";
   OS << "} // End llvm namespace \n";
 }
@@ -198,6 +241,7 @@ void InstrInfoEmitter::run(std::ostream &OS) {
 void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
                                   Record *InstrInfo,
                          std::map<std::vector<Record*>, unsigned> &EmittedLists,
+                                  std::map<Record*, unsigned> &BarriersMap,
                                   const OperandInfoMapTy &OpInfo,
                                   std::ostream &OS) {
   int MinOperands = 0;
@@ -206,14 +250,6 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
     MinOperands = Inst.OperandList.back().MIOperandNo +
                   Inst.OperandList.back().MINumOperands;
 
-  // Subtract the number of "discard" operands, which we'll be skipping
-  // when emitting OperandInfo records.
-  for (unsigned j = 0, e = Inst.OperandList.size(); j != e; ++j) {
-    Record *OpR = Inst.OperandList[j].Rec;
-    if (OpR->getName() == "discard")
-      --MinOperands;
-  }
-  
   OS << "  { ";
   OS << Num << ",\t" << MinOperands << ",\t"
      << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef)
@@ -226,7 +262,7 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   if (Inst.isBarrier)          OS << "|(1<<TID::Barrier)";
   if (Inst.hasDelaySlot)       OS << "|(1<<TID::DelaySlot)";
   if (Inst.isCall)             OS << "|(1<<TID::Call)";
-  if (Inst.isSimpleLoad)       OS << "|(1<<TID::SimpleLoad)";
+  if (Inst.canFoldAsLoad)      OS << "|(1<<TID::FoldableAsLoad)";
   if (Inst.mayLoad)            OS << "|(1<<TID::MayLoad)";
   if (Inst.mayStore)           OS << "|(1<<TID::MayStore)";
   if (Inst.isPredicable)       OS << "|(1<<TID::Predicable)";
@@ -269,6 +305,12 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num,
   else
     OS << "ImplicitList" << EmittedLists[DefList] << ", ";
 
+  std::map<Record*, unsigned>::iterator BI = BarriersMap.find(Inst.TheDef);
+  if (BI == BarriersMap.end())
+    OS << "NULL, ";
+  else
+    OS << "Barriers" << BI->second << ", ";
+
   // Emit the operand info.
   std::vector<std::string> OperandInfo = GetOperandInfo(Inst);
   if (OperandInfo.empty())
@@ -291,7 +333,9 @@ void InstrInfoEmitter::emitShiftedValue(Record *R, StringInit *Val,
     // This isn't an error if this is a builtin instruction.
     if (R->getName() != "PHI" &&
         R->getName() != "INLINEASM" &&
-        R->getName() != "LABEL" &&
+        R->getName() != "DBG_LABEL" &&
+        R->getName() != "EH_LABEL" &&
+        R->getName() != "GC_LABEL" &&
         R->getName() != "DECLARE" &&
         R->getName() != "EXTRACT_SUBREG" &&
         R->getName() != "INSERT_SUBREG" &&