X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FInstrInfoEmitter.cpp;h=fb8dd371efd11265399059eb30097b7f56d3180e;hb=56867520990a4fea1353d55f71bb74a0126554e6;hp=2283274ce45951734d1a1628d3bed83f184083ad;hpb=2e48a70b35635165703838fc8d3796b664207aa1;p=oota-llvm.git diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp index 2283274ce45..fb8dd371efd 100644 --- a/utils/TableGen/InstrInfoEmitter.cpp +++ b/utils/TableGen/InstrInfoEmitter.cpp @@ -94,17 +94,17 @@ InstrInfoEmitter::GetOperandInfo(const CodeGenInstruction &Inst) { // Ptr value whose register class is resolved via callback. if (OpR->getName() == "ptr_rc") - Res += "|M_LOOK_UP_PTR_REG_CLASS"; + Res += "|(1<isSubClassOf("PredicateOperand")) - Res += "|M_PREDICATE_OPERAND"; + Res += "|(1<isSubClassOf("OptionalDefOperand")) - Res += "|M_OPTIONAL_DEF_OPERAND"; + Res += "|(1<getTree(0)); - } - -private: - void AnalyzeNode(const TreePatternNode *N) { - if (N->isLeaf()) { - return; - } - - if (N->getOperator()->getName() != "set") { - // Get information about the SDNode for the operator. - const SDNodeInfo &OpInfo = CDP.getSDNodeInfo(N->getOperator()); - - // If node writes to memory, it obviously stores to memory. - if (OpInfo.hasProperty(SDNPMayStore)) { - mayStore = true; - } else if (const CodeGenIntrinsic *IntInfo = N->getIntrinsicInfo(CDP)) { - // If this is an intrinsic, analyze it. - if (IntInfo->ModRef >= CodeGenIntrinsic::WriteArgMem) - mayStore = true;// Intrinsics that can write to memory are 'mayStore'. - } - } - - for (unsigned i = 0, e = N->getNumChildren(); i != e; ++i) - AnalyzeNode(N->getChild(i)); - } - -}; - -void InstrInfoEmitter::InferFromPattern(const CodeGenInstruction &Inst, - bool &mayStore, bool &isLoad, - bool &NeverHasSideEffects) { - mayStore = isLoad = NeverHasSideEffects = false; - - InstAnalyzer(CDP, mayStore, isLoad, NeverHasSideEffects).Analyze(Inst.TheDef); - - // InstAnalyzer only correctly analyzes mayStore so far. - if (Inst.mayStore) { // If the .td file explicitly sets mayStore, use it. - // If we decided that this is a store from the pattern, then the .td file - // entry is redundant. - if (mayStore) - fprintf(stderr, - "Warning: mayStore flag explicitly set on instruction '%s'" - " but flag already inferred from pattern.\n", - Inst.getName().c_str()); - mayStore = true; - } - - // These two override everything. - isLoad = Inst.isLoad; - NeverHasSideEffects = Inst.neverHasSideEffects; - -#if 0 - // If the .td file explicitly says there is no side effect, believe it. - if (Inst.neverHasSideEffects) - NeverHasSideEffects = true; -#endif -} - - //===----------------------------------------------------------------------===// // Main Output. //===----------------------------------------------------------------------===// @@ -232,7 +148,7 @@ void InstrInfoEmitter::run(std::ostream &OS) { EmitSourceFileHeader("Target Instruction Descriptors", OS); OS << "namespace llvm {\n\n"; - CodeGenTarget Target; + CodeGenTarget &Target = CDP.getTargetInfo(); const std::string &TargetName = Target.getName(); Record *InstrInfo = Target.getInstructionSet(); @@ -261,9 +177,9 @@ void InstrInfoEmitter::run(std::ostream &OS) { // Emit all of the operand info records. EmitOperandInfo(OS, OperandInfoIDs); - // Emit all of the TargetInstrDescriptor records in their ENUM ordering. + // Emit all of the TargetInstrDesc records in their ENUM ordering. // - OS << "\nstatic const TargetInstrDescriptor " << TargetName + OS << "\nstatic const TargetInstrDesc " << TargetName << "Insts[] = {\n"; std::vector NumberedInstructions; Target.getInstructionsByEnumValue(NumberedInstructions); @@ -280,49 +196,39 @@ void InstrInfoEmitter::emitRecord(const CodeGenInstruction &Inst, unsigned Num, std::map, unsigned> &EmittedLists, const OperandInfoMapTy &OpInfo, std::ostream &OS) { - // Determine properties of the instruction from its pattern. - bool mayStore, isLoad, NeverHasSideEffects; - InferFromPattern(Inst, mayStore, isLoad, NeverHasSideEffects); - - if (NeverHasSideEffects && Inst.mayHaveSideEffects) { - std::cerr << "error: Instruction '" << Inst.getName() - << "' is marked with 'mayHaveSideEffects', but it can never have them!\n"; - exit(1); - } - int MinOperands = 0; if (!Inst.OperandList.empty()) // Each logical operand can be multiple MI operands. MinOperands = Inst.OperandList.back().MIOperandNo + Inst.OperandList.back().MINumOperands; - + OS << " { "; OS << Num << ",\t" << MinOperands << ",\t" - << Inst.NumDefs << ",\t\"" << Inst.getName(); - OS << "\",\t" << getItinClassNumber(Inst.TheDef) << ", 0"; + << Inst.NumDefs << ",\t" << getItinClassNumber(Inst.TheDef) + << ",\t\"" << Inst.TheDef->getName() << "\", 0"; // Emit all of the target indepedent flags... - if (Inst.isReturn) OS << "|M_RET_FLAG"; - if (Inst.isBranch) OS << "|M_BRANCH_FLAG"; - if (Inst.isIndirectBranch) OS << "|M_INDIRECT_FLAG"; - if (Inst.isBarrier) OS << "|M_BARRIER_FLAG"; - if (Inst.hasDelaySlot) OS << "|M_DELAY_SLOT_FLAG"; - if (Inst.isCall) OS << "|M_CALL_FLAG"; - if (isLoad) OS << "|M_LOAD_FLAG"; - if (mayStore) OS << "|M_MAY_STORE_FLAG"; - if (Inst.isImplicitDef)OS << "|M_IMPLICIT_DEF_FLAG"; - if (Inst.isPredicable) OS << "|M_PREDICABLE"; - if (Inst.isConvertibleToThreeAddress) OS << "|M_CONVERTIBLE_TO_3_ADDR"; - if (Inst.isCommutable) OS << "|M_COMMUTABLE"; - if (Inst.isTerminator) OS << "|M_TERMINATOR_FLAG"; - if (Inst.isReMaterializable) OS << "|M_REMATERIALIZIBLE"; - if (Inst.isNotDuplicable) OS << "|M_NOT_DUPLICABLE"; - if (Inst.hasOptionalDef) OS << "|M_HAS_OPTIONAL_DEF"; + if (Inst.isReturn) OS << "|(1<getName() != "PHI" && R->getName() != "INLINEASM" && R->getName() != "LABEL" && + R->getName() != "DECLARE" && R->getName() != "EXTRACT_SUBREG" && - R->getName() != "INSERT_SUBREG") + R->getName() != "INSERT_SUBREG" && + R->getName() != "IMPLICIT_DEF" && + R->getName() != "SUBREG_TO_REG") throw R->getName() + " doesn't have a field named '" + Val->getValue() + "'!"; return;