X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=06f43d5d2d2c99c74674af656eaf2a30d40e4d86;hb=62c939d7d5572e57963a5f26fb6fe802e13dc0bf;hp=fad0331a112cb9a709efc5a3c26482d9edf2d00c;hpb=b97aec663b1591e71c9ddee6dbb327d1b827eda5;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index fad0331a112..06f43d5d2d2 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -21,6 +21,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" #include +#include using namespace llvm; // runEnums - Print out enum values for all of the registers. @@ -52,17 +53,19 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; - OS << "#include \"llvm/Target/MRegisterInfo.h\"\n"; + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; OS << "#include \n\n"; OS << "namespace llvm {\n\n"; - OS << "struct " << ClassName << " : public MRegisterInfo {\n" - << " " << ClassName + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" + << " explicit " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n"; @@ -77,7 +80,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; OS << " " << RegisterClasses[i].getName() << "RegClassID"; - if (!i) OS << " = 1"; + OS << " = " << (i+1); } OS << "\n };\n\n"; @@ -111,13 +114,12 @@ bool isSubRegisterClass(const CodeGenRegisterClass &RC, } static void addSuperReg(Record *R, Record *S, - std::map > &SubRegs, - std::map > &SuperRegs, - std::map > &Aliases, - RegisterInfoEmitter &RIE) { + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" - << " register " << RIE.getQualifiedName(R) + << " register " << getQualifiedName(R) << " and its sub-registers?\n"; abort(); } @@ -129,32 +131,45 @@ static void addSuperReg(Record *R, Record *S, if (SuperRegs.count(S)) for (std::set::iterator I = SuperRegs[S].begin(), E = SuperRegs[S].end(); I != E; ++I) - addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE); + addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } static void addSubSuperReg(Record *R, Record *S, - std::map > &SubRegs, - std::map > &SuperRegs, - std::map > &Aliases, - RegisterInfoEmitter &RIE) { + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" - << " register " << RIE.getQualifiedName(R) + << " register " << getQualifiedName(R) << " and its sub-registers?\n"; abort(); } if (!SubRegs[R].insert(S).second) return; - addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE); + addSuperReg(S, R, SubRegs, SuperRegs, Aliases); Aliases[R].insert(S); Aliases[S].insert(R); if (SubRegs.count(S)) for (std::set::iterator I = SubRegs[S].begin(), E = SubRegs[S].end(); I != E; ++I) - addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE); + addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } +class RegisterSorter { +private: + std::map, LessRecord> &RegisterSubRegs; + +public: + RegisterSorter(std::map, LessRecord> &RS) + : RegisterSubRegs(RS) {}; + + bool operator()(Record *RegA, Record *RegB) { + // B is sub-register of A. + return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); + } +}; + // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(std::ostream &OS) { @@ -208,7 +223,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) OS << getEnumName(RC.VTs[i]) << ", "; @@ -236,7 +251,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { std::string Name = RC.TheDef->getName(); OS << " // " << Name - << " Sub-register Classess...\n" + << " Sub-register Classes...\n" << " static const TargetRegisterClass* const " << Name << "SubRegClasses [] = {\n "; @@ -281,7 +296,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { std::string Name = RC.TheDef->getName(); OS << " // " << Name - << " Super-register Classess...\n" + << " Super-register Classes...\n" << " static const TargetRegisterClass* const " << Name << "SuperRegClasses [] = {\n "; @@ -403,12 +418,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " };\n"; // Emit register sub-registers / super-registers, aliases... - std::map > RegisterImmSubRegs; - std::map > RegisterSubRegs; - std::map > RegisterSuperRegs; - std::map > RegisterAliases; + std::map, LessRecord> RegisterSubRegs; + std::map, LessRecord> RegisterSuperRegs; + std::map, LessRecord> RegisterAliases; std::map > > SubRegVectors; - std::map > DwarfRegNums; + typedef std::map, LessRecord> DwarfRegNumsMapTy; + DwarfRegNumsMapTy DwarfRegNums; const std::vector &Regs = Target.getRegisters(); @@ -444,11 +459,86 @@ void RegisterInfoEmitter::run(std::ostream &OS) { cerr << "Warning: register " << getQualifiedName(SubReg) << " specified as a sub-register of " << getQualifiedName(R) << " multiple times!\n"; - RegisterImmSubRegs[R].insert(SubReg); addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, - RegisterAliases, *this); + RegisterAliases); + } + } + + // Print the SubregHashTable, a simple quadratically probed + // hash table for determining if a register is a subregister + // of another register. + unsigned NumSubRegs = 0; + std::map RegNo; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + RegNo[Regs[i].TheDef] = i; + NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); + } + + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); + unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; + std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); + + unsigned hashMisses = 0; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record* R = Regs[i].TheDef; + for (std::set::iterator I = RegisterSubRegs[R].begin(), + E = RegisterSubRegs[R].end(); I != E; ++I) { + Record* RJ = *I; + // We have to increase the indices of both registers by one when + // computing the hash because, in the generated code, there + // will be an extra empty slot at register 0. + size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); + unsigned ProbeAmt = 2; + while (SubregHashTable[index*2] != ~0U && + SubregHashTable[index*2+1] != ~0U) { + index = (index + ProbeAmt) & (SubregHashTableSize-1); + ProbeAmt += 2; + + hashMisses++; + } + + SubregHashTable[index*2] = i; + SubregHashTable[index*2+1] = RegNo[RJ]; + } + } + + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; + + if (SubregHashTableSize) { + std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); + + OS << " const unsigned SubregHashTable[] = { "; + for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { + if (i != 0) + // Insert spaces for nice formatting. + OS << " "; + + if (SubregHashTable[2*i] != ~0U) { + OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; + } + } + + unsigned Idx = SubregHashTableSize*2-2; + if (SubregHashTable[Idx] != ~0U) { + OS << " " + << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } + + OS << " const unsigned SubregHashTableSize = " + << SubregHashTableSize << ";\n"; + } else { + OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" + << " const unsigned SubregHashTableSize = 1;\n"; } + + delete [] SubregHashTable; if (!RegisterAliases.empty()) OS << "\n\n // Register Alias Sets...\n"; @@ -457,7 +547,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; // Loop over all of the registers which have aliases, emitting the alias list // to memory. - for (std::map >::iterator + for (std::map, LessRecord >::iterator I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; for (std::set::iterator ASI = I->second.begin(), @@ -473,27 +563,17 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; // Loop over all of the registers which have sub-registers, emitting the // sub-registers list to memory. - for (std::map >::iterator + for (std::map, LessRecord>::iterator I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; + std::vector SubRegsVector; for (std::set::iterator ASI = I->second.begin(), E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; - OS << "0 };\n"; - } - - if (!RegisterImmSubRegs.empty()) - OS << "\n\n // Register Immediate Sub-registers Sets...\n"; - - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (std::map >::iterator - I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end(); - I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { "; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; + SubRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); + for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SubRegsVector[i]) << ", "; OS << "0 };\n"; } @@ -504,17 +584,23 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; // Loop over all of the registers which have super-registers, emitting the // super-registers list to memory. - for (std::map >::iterator + for (std::map, LessRecord >::iterator I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; + + std::vector SuperRegsVector; for (std::set::iterator ASI = I->second.begin(), E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; + SuperRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); + for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SuperRegsVector[i]) << ", "; OS << "0 };\n"; } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -522,11 +608,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) { for (unsigned i = 0, e = Registers.size(); i != e; ++i) { const CodeGenRegister &Reg = Registers[i]; OS << " { \""; - if (!Reg.TheDef->getValueAsString("Name").empty()) - OS << Reg.TheDef->getValueAsString("Name"); + if (!Reg.TheDef->getValueAsString("AsmName").empty()) + OS << Reg.TheDef->getValueAsString("AsmName"); else OS << Reg.getName(); - OS << "\",\t"; + OS << "\",\t\""; + OS << Reg.getName() << "\",\t"; if (RegisterAliases.count(Reg.TheDef)) OS << Reg.getName() << "_AliasSet,\t"; else @@ -535,10 +622,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (RegisterImmSubRegs.count(Reg.TheDef)) - OS << Reg.getName() << "_ImmSubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; if (RegisterSuperRegs.count(Reg.TheDef)) OS << Reg.getName() << "_SuperRegsSet },\n"; else @@ -572,16 +655,16 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << "unsigned " << ClassName << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" << " switch (RegNo) {\n" - << " default: abort(); break;\n"; + << " default:\n return 0;\n"; for (std::map > >::iterator I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { OS << " case " << getQualifiedName(I->first) << ":\n"; OS << " switch (Index) {\n"; - OS << " default: abort(); break;\n"; + OS << " default: return 0;\n"; for (unsigned i = 0, e = I->second.size(); i != e; ++i) OS << " case " << (I->second)[i].first << ": return " << getQualifiedName((I->second)[i].second) << ";\n"; - OS << " }; break;\n"; + OS << " };\n" << " break;\n"; } OS << " };\n"; OS << " return 0;\n"; @@ -590,9 +673,11 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the constructor of the class... OS << ClassName << "::" << ClassName << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" - << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1 + << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; + << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" + << " SubregHashTable, SubregHashTableSize) {\n" + << "}\n\n"; // Collect all information about dwarf register numbers @@ -600,7 +685,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { unsigned maxLength = 0; for (unsigned i = 0, e = Registers.size(); i != e; ++i) { Record *Reg = Registers[i].TheDef; - std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); + std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); maxLength = std::max((size_t)maxLength, RegNums.size()); if (DwarfRegNums.count(Reg)) cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) @@ -609,8 +694,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) { } // Now we know maximal length of number list. Append -1's, where needed - for (std::map >::iterator - I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); @@ -628,8 +713,11 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << " default:\n" << " assert(0 && \"Invalid RegNum\");\n" << " return -1;\n"; + + // Sort by name to get a stable order. + - for (std::map >::iterator + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { int RegNo = I->second[i]; if (RegNo != -2)