X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=67d1cfcf4d3438bbf58054f7da011ae453fc4726;hb=0d52ff1f7b993750a74a5d4432273092de9af069;hp=608b6dc6396074a0933a2ba4b82be809b1d25c12;hpb=f5da13367f88f06e3b585dc2263ab6e9ca6c4bf8;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 608b6dc6396..67d1cfcf4d3 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -21,6 +21,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" #include +#include using namespace llvm; // runEnums - Print out enum values for all of the registers. @@ -38,8 +39,8 @@ void RegisterInfoEmitter::runEnums(std::ostream &OS) { OS << " enum {\n NoRegister,\n"; for (unsigned i = 0, e = Registers.size(); i != e; ++i) - OS << " " << Registers[i].getName() << (i != (e-1) ? ", \t// " : " \t// ") << i+1 << "\n"; - + OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; + OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; OS << " };\n"; if (!Namespace.empty()) OS << "}\n"; @@ -52,15 +53,20 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; - OS << "#include \"llvm/Target/MRegisterInfo.h\"\n"; + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; OS << "#include \n\n"; OS << "namespace llvm {\n\n"; - OS << "struct " << ClassName << " : public MRegisterInfo {\n" - << " " << ClassName + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" + << " explicit " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" - << " int getDwarfRegNum(unsigned RegNum) const;\n" + << " virtual int getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" + << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n"; const std::vector &RegisterClasses = @@ -74,7 +80,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; OS << " " << RegisterClasses[i].getName() << "RegClassID"; - if (!i) OS << " = 1"; + OS << " = " << (i+1); } OS << "\n };\n\n"; @@ -107,6 +113,63 @@ bool isSubRegisterClass(const CodeGenRegisterClass &RC, return true; } +static void addSuperReg(Record *R, Record *S, + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { + if (R == S) { + cerr << "Error: recursive sub-register relationship between" + << " register " << getQualifiedName(R) + << " and its sub-registers?\n"; + abort(); + } + if (!SuperRegs[R].insert(S).second) + return; + SubRegs[S].insert(R); + Aliases[R].insert(S); + Aliases[S].insert(R); + if (SuperRegs.count(S)) + for (std::set::iterator I = SuperRegs[S].begin(), + E = SuperRegs[S].end(); I != E; ++I) + addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); +} + +static void addSubSuperReg(Record *R, Record *S, + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { + if (R == S) { + cerr << "Error: recursive sub-register relationship between" + << " register " << getQualifiedName(R) + << " and its sub-registers?\n"; + abort(); + } + + if (!SubRegs[R].insert(S).second) + return; + addSuperReg(S, R, SubRegs, SuperRegs, Aliases); + Aliases[R].insert(S); + Aliases[S].insert(R); + if (SubRegs.count(S)) + for (std::set::iterator I = SubRegs[S].begin(), + E = SubRegs[S].end(); I != E; ++I) + addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); +} + +class RegisterSorter { +private: + std::map, LessRecord> &RegisterSubRegs; + +public: + RegisterSorter(std::map, LessRecord> &RS) + : RegisterSubRegs(RS) {}; + + bool operator()(Record *RegA, Record *RegB) { + // B is sub-register of A. + return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); + } +}; + // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(std::ostream &OS) { @@ -160,10 +223,10 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) - OS << RC.VTs[i] << ", "; + OS << getEnumName(RC.VTs[i]) << ", "; OS << "MVT::Other\n };\n\n"; } OS << "} // end anonymous namespace\n\n"; @@ -178,6 +241,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { std::map > SuperClassMap; OS << "\n"; + // Emit the sub-classes array for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = RegisterClasses[rc]; @@ -259,8 +323,10 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RC.getName() + "Subclasses" << ", " << RC.getName() + "Superclasses" << ", " << RC.SpillSize/8 << ", " - << RC.SpillAlignment/8 << ", " << RC.getName() << ", " - << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; + << RC.SpillAlignment/8 << ", " + << RC.CopyCost << ", " + << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() + << ") {}\n"; } OS << "}\n"; @@ -273,8 +339,14 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << "RegClass,\n"; OS << " };\n"; - // Emit register class aliases... - std::map > RegisterAliases; + // Emit register sub-registers / super-registers, aliases... + std::map, LessRecord> RegisterSubRegs; + std::map, LessRecord> RegisterSuperRegs; + std::map, LessRecord> RegisterAliases; + std::map > > SubRegVectors; + typedef std::map, LessRecord> DwarfRegNumsMapTy; + DwarfRegNumsMapTy DwarfRegNums; + const std::vector &Regs = Target.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -298,6 +370,98 @@ void RegisterInfoEmitter::run(std::ostream &OS) { } } + // Process sub-register sets. + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record *R = Regs[i].TheDef; + std::vector LI = Regs[i].TheDef->getValueAsListOfDefs("SubRegs"); + // Process sub-register set and add aliases information. + for (unsigned j = 0, e = LI.size(); j != e; ++j) { + Record *SubReg = LI[j]; + if (RegisterSubRegs[R].count(SubReg)) + cerr << "Warning: register " << getQualifiedName(SubReg) + << " specified as a sub-register of " << getQualifiedName(R) + << " multiple times!\n"; + addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, + RegisterAliases); + } + } + + // Print the SubregHashTable, a simple quadratically probed + // hash table for determining if a register is a subregister + // of another register. + unsigned NumSubRegs = 0; + std::map RegNo; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + RegNo[Regs[i].TheDef] = i; + NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); + } + + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); + unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; + std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); + + unsigned hashMisses = 0; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record* R = Regs[i].TheDef; + for (std::set::iterator I = RegisterSubRegs[R].begin(), + E = RegisterSubRegs[R].end(); I != E; ++I) { + Record* RJ = *I; + // We have to increase the indices of both registers by one when + // computing the hash because, in the generated code, there + // will be an extra empty slot at register 0. + size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); + unsigned ProbeAmt = 2; + while (SubregHashTable[index*2] != ~0U && + SubregHashTable[index*2+1] != ~0U) { + index = (index + ProbeAmt) & (SubregHashTableSize-1); + ProbeAmt += 2; + + hashMisses++; + } + + SubregHashTable[index*2] = i; + SubregHashTable[index*2+1] = RegNo[RJ]; + } + } + + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; + + if (SubregHashTableSize) { + std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); + + OS << " const unsigned SubregHashTable[] = { "; + for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { + if (i != 0) + // Insert spaces for nice formatting. + OS << " "; + + if (SubregHashTable[2*i] != ~0U) { + OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; + } + } + + unsigned Idx = SubregHashTableSize*2-2; + if (SubregHashTable[Idx] != ~0U) { + OS << " " + << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; + } + + OS << " const unsigned SubregHashTableSize = " + << SubregHashTableSize << ";\n"; + } else { + OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" + << " const unsigned SubregHashTableSize = 1;\n"; + } + + delete [] SubregHashTable; + if (!RegisterAliases.empty()) OS << "\n\n // Register Alias Sets...\n"; @@ -305,7 +469,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; // Loop over all of the registers which have aliases, emitting the alias list // to memory. - for (std::map >::iterator + for (std::map, LessRecord >::iterator I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; for (std::set::iterator ASI = I->second.begin(), @@ -314,53 +478,182 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << "0 };\n"; } - OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0 },\n"; + if (!RegisterSubRegs.empty()) + OS << "\n\n // Register Sub-registers Sets...\n"; + + // Emit the empty sub-registers list + OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have sub-registers, emitting the + // sub-registers list to memory. + for (std::map, LessRecord>::iterator + I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { + OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; + std::vector SubRegsVector; + for (std::set::iterator ASI = I->second.begin(), + E = I->second.end(); ASI != E; ++ASI) + SubRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); + for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SubRegsVector[i]) << ", "; + OS << "0 };\n"; + } + + if (!RegisterSuperRegs.empty()) + OS << "\n\n // Register Super-registers Sets...\n"; + + // Emit the empty super-registers list + OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; + // Loop over all of the registers which have super-registers, emitting the + // super-registers list to memory. + for (std::map, LessRecord >::iterator + I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { + OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; + + std::vector SuperRegsVector; + for (std::set::iterator ASI = I->second.begin(), + E = I->second.end(); ASI != E; ++ASI) + SuperRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); + for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SuperRegsVector[i]) << ", "; + OS << "0 };\n"; + } + OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; + OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; - // Now that register alias sets have been emitted, emit the register - // descriptors now. + // Now that register alias and sub-registers sets have been emitted, emit the + // register descriptors now. const std::vector &Registers = Target.getRegisters(); for (unsigned i = 0, e = Registers.size(); i != e; ++i) { const CodeGenRegister &Reg = Registers[i]; OS << " { \""; - if (!Reg.TheDef->getValueAsString("Name").empty()) - OS << Reg.TheDef->getValueAsString("Name"); + if (!Reg.TheDef->getValueAsString("AsmName").empty()) + OS << Reg.TheDef->getValueAsString("AsmName"); else OS << Reg.getName(); - OS << "\",\t"; + OS << "\",\t\""; + OS << Reg.getName() << "\",\t"; if (RegisterAliases.count(Reg.TheDef)) - OS << Reg.getName() << "_AliasSet },\n"; + OS << Reg.getName() << "_AliasSet,\t"; else - OS << "Empty_AliasSet },\n"; + OS << "Empty_AliasSet,\t"; + if (RegisterSubRegs.count(Reg.TheDef)) + OS << Reg.getName() << "_SubRegsSet,\t"; + else + OS << "Empty_SubRegsSet,\t"; + if (RegisterSuperRegs.count(Reg.TheDef)) + OS << Reg.getName() << "_SuperRegsSet },\n"; + else + OS << "Empty_SuperRegsSet },\n"; } OS << " };\n"; // End of register descriptors... OS << "}\n\n"; // End of anonymous namespace... std::string ClassName = Target.getName() + "GenRegisterInfo"; + // Calculate the mapping of subregister+index pairs to physical registers. + std::vector SubRegs = Records.getAllDerivedDefinitions("SubRegSet"); + for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { + int subRegIndex = SubRegs[i]->getValueAsInt("index"); + std::vector From = SubRegs[i]->getValueAsListOfDefs("From"); + std::vector To = SubRegs[i]->getValueAsListOfDefs("To"); + + if (From.size() != To.size()) { + cerr << "Error: register list and sub-register list not of equal length" + << " in SubRegSet\n"; + exit(1); + } + + // For each entry in from/to vectors, insert the to register at index + for (unsigned ii = 0, ee = From.size(); ii != ee; ++ii) + SubRegVectors[From[ii]].push_back(std::make_pair(subRegIndex, To[ii])); + } + + // Emit the subregister + index mapping function based on the information + // calculated above. + OS << "unsigned " << ClassName + << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" + << " switch (RegNo) {\n" + << " default:\n return 0;\n"; + for (std::map > >::iterator + I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { + OS << " case " << getQualifiedName(I->first) << ":\n"; + OS << " switch (Index) {\n"; + OS << " default: return 0;\n"; + for (unsigned i = 0, e = I->second.size(); i != e; ++i) + OS << " case " << (I->second)[i].first << ": return " + << getQualifiedName((I->second)[i].second) << ";\n"; + OS << " };\n" << " break;\n"; + } + OS << " };\n"; + OS << " return 0;\n"; + OS << "}\n\n"; + // Emit the constructor of the class... OS << ClassName << "::" << ClassName << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" - << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1 + << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; + << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" + << " SubregHashTable, SubregHashTableSize) {\n" + << "}\n\n"; - // Emit information about the dwarf register numbers. - OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n"; - OS << " static const int DwarfRegNums[] = { -1, // NoRegister"; + // Collect all information about dwarf register numbers + + // First, just pull all provided information to the map + unsigned maxLength = 0; for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - if (!(i % 16)) OS << "\n "; - const CodeGenRegister &Reg = Registers[i]; - int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber"); - OS << DwarfRegNum; - if ((i + 1) != e) OS << ", "; + Record *Reg = Registers[i].TheDef; + std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); + maxLength = std::max((size_t)maxLength, RegNums.size()); + if (DwarfRegNums.count(Reg)) + cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) + << "specified multiple times\n"; + DwarfRegNums[Reg] = RegNums; } - OS << "\n };\n"; - OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n"; - OS << " \"RegNum exceeds number of registers\");\n"; - OS << " return DwarfRegNums[RegNum];\n"; - OS << "}\n\n"; + + // Now we know maximal length of number list. Append -1's, where needed + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) + for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) + I->second.push_back(-1); + + // Emit information about the dwarf register numbers. + OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const {\n" + << " switch (Flavour) {\n" + << " default:\n" + << " assert(0 && \"Unknown DWARF flavour\");\n" + << " return -1;\n"; + + for (unsigned i = 0, e = maxLength; i != e; ++i) { + OS << " case " << i << ":\n" + << " switch (RegNum) {\n" + << " default:\n" + << " assert(0 && \"Invalid RegNum\");\n" + << " return -1;\n"; + + // Sort by name to get a stable order. + + + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { + int RegNo = I->second[i]; + if (RegNo != -2) + OS << " case " << getQualifiedName(I->first) << ":\n" + << " return " << RegNo << ";\n"; + else + OS << " case " << getQualifiedName(I->first) << ":\n" + << " assert(0 && \"Invalid register for this mode\");\n" + << " return -1;\n"; + } + OS << " };\n"; + } + + OS << " };\n}\n\n"; OS << "} // End llvm namespace \n"; }