X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=67d1cfcf4d3438bbf58054f7da011ae453fc4726;hb=0d52ff1f7b993750a74a5d4432273092de9af069;hp=ce95390054f8aa27550d2265ce90c7f75672a5ff;hpb=8102703d708e5d399926c6ba71ffa49bbd31fc8a;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index ce95390054f..67d1cfcf4d3 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -21,6 +21,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" #include +#include using namespace llvm; // runEnums - Print out enum values for all of the registers. @@ -63,6 +64,8 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n"; @@ -111,9 +114,9 @@ bool isSubRegisterClass(const CodeGenRegisterClass &RC, } static void addSuperReg(Record *R, Record *S, - std::map > &SubRegs, - std::map > &SuperRegs, - std::map > &Aliases) { + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" << " register " << getQualifiedName(R) @@ -132,9 +135,9 @@ static void addSuperReg(Record *R, Record *S, } static void addSubSuperReg(Record *R, Record *S, - std::map > &SubRegs, - std::map > &SuperRegs, - std::map > &Aliases) { + std::map, LessRecord> &SubRegs, + std::map, LessRecord> &SuperRegs, + std::map, LessRecord> &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" << " register " << getQualifiedName(R) @@ -155,10 +158,10 @@ static void addSubSuperReg(Record *R, Record *S, class RegisterSorter { private: - std::map > &RegisterSubRegs; + std::map, LessRecord> &RegisterSubRegs; public: - RegisterSorter(std::map > &RS) + RegisterSorter(std::map, LessRecord> &RS) : RegisterSubRegs(RS) {}; bool operator()(Record *RegA, Record *RegB) { @@ -220,7 +223,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) OS << getEnumName(RC.VTs[i]) << ", "; @@ -237,83 +240,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RegisterClasses[i].getName() << "RegClass;\n"; std::map > SuperClassMap; - std::map > SuperRegClassMap; OS << "\n"; - - // Emit the sub-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = RegisterClasses[rc]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); - - OS << " // " << Name - << " Sub-register Classess...\n" - << " static const TargetRegisterClass* const " - << Name << "SubRegClasses [] = {\n "; - - bool Empty = true; - - for (unsigned subrc = 0, subrcMax = RC.SubRegClasses.size(); - subrc != subrcMax; ++subrc) { - unsigned rc2 = 0, e2 = RegisterClasses.size(); - for (; rc2 != e2; ++rc2) { - const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; - if (RC.SubRegClasses[subrc]->getName() == RC2.getName()) { - if (!Empty) - OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; - - std::map >::iterator SCMI = - SuperRegClassMap.find(rc2); - if (SCMI == SuperRegClassMap.end()) { - SuperRegClassMap.insert(std::make_pair(rc2, std::set())); - SCMI = SuperRegClassMap.find(rc2); - } - SCMI->second.insert(rc); - break; - } - } - if (rc2 == e2) - throw "Register Class member '" + - RC.SubRegClasses[subrc]->getName() + - "' is not a valid RegisterClass!"; - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n };\n\n"; - } - - // Emit the super-register classes for each RegisterClass - for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { - const CodeGenRegisterClass &RC = RegisterClasses[rc]; - - // Give the register class a legal C name if it's anonymous. - std::string Name = RC.TheDef->getName(); - - OS << " // " << Name - << " Super-register Classess...\n" - << " static const TargetRegisterClass* const " - << Name << "SuperRegClasses [] = {\n "; - - bool Empty = true; - std::map >::iterator I = - SuperRegClassMap.find(rc); - if (I != SuperRegClassMap.end()) { - for (std::set::iterator II = I->second.begin(), - EE = I->second.end(); II != EE; ++II) { - const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; - if (!Empty) - OS << ", "; - OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; - } - } - - OS << (!Empty ? ", " : "") << "NULL"; - OS << "\n };\n\n"; - } // Emit the sub-classes array for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { @@ -395,8 +322,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << RC.getName() + "VTs" << ", " << RC.getName() + "Subclasses" << ", " << RC.getName() + "Superclasses" << ", " - << RC.getName() + "SubRegClasses" << ", " - << RC.getName() + "SuperRegClasses" << ", " << RC.SpillSize/8 << ", " << RC.SpillAlignment/8 << ", " << RC.CopyCost << ", " @@ -415,12 +340,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " };\n"; // Emit register sub-registers / super-registers, aliases... - std::map > RegisterImmSubRegs; - std::map > RegisterSubRegs; - std::map > RegisterSuperRegs; - std::map > RegisterAliases; + std::map, LessRecord> RegisterSubRegs; + std::map, LessRecord> RegisterSuperRegs; + std::map, LessRecord> RegisterAliases; std::map > > SubRegVectors; - std::map > DwarfRegNums; + typedef std::map, LessRecord> DwarfRegNumsMapTy; + DwarfRegNumsMapTy DwarfRegNums; const std::vector &Regs = Target.getRegisters(); @@ -456,11 +381,86 @@ void RegisterInfoEmitter::run(std::ostream &OS) { cerr << "Warning: register " << getQualifiedName(SubReg) << " specified as a sub-register of " << getQualifiedName(R) << " multiple times!\n"; - RegisterImmSubRegs[R].insert(SubReg); addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, RegisterAliases); } } + + // Print the SubregHashTable, a simple quadratically probed + // hash table for determining if a register is a subregister + // of another register. + unsigned NumSubRegs = 0; + std::map RegNo; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + RegNo[Regs[i].TheDef] = i; + NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); + } + + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); + unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; + std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); + + unsigned hashMisses = 0; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record* R = Regs[i].TheDef; + for (std::set::iterator I = RegisterSubRegs[R].begin(), + E = RegisterSubRegs[R].end(); I != E; ++I) { + Record* RJ = *I; + // We have to increase the indices of both registers by one when + // computing the hash because, in the generated code, there + // will be an extra empty slot at register 0. + size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); + unsigned ProbeAmt = 2; + while (SubregHashTable[index*2] != ~0U && + SubregHashTable[index*2+1] != ~0U) { + index = (index + ProbeAmt) & (SubregHashTableSize-1); + ProbeAmt += 2; + + hashMisses++; + } + + SubregHashTable[index*2] = i; + SubregHashTable[index*2+1] = RegNo[RJ]; + } + } + + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; + + if (SubregHashTableSize) { + std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); + + OS << " const unsigned SubregHashTable[] = { "; + for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { + if (i != 0) + // Insert spaces for nice formatting. + OS << " "; + + if (SubregHashTable[2*i] != ~0U) { + OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; + } + } + + unsigned Idx = SubregHashTableSize*2-2; + if (SubregHashTable[Idx] != ~0U) { + OS << " " + << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; + } + + OS << " const unsigned SubregHashTableSize = " + << SubregHashTableSize << ";\n"; + } else { + OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" + << " const unsigned SubregHashTableSize = 1;\n"; + } + + delete [] SubregHashTable; if (!RegisterAliases.empty()) OS << "\n\n // Register Alias Sets...\n"; @@ -469,7 +469,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; // Loop over all of the registers which have aliases, emitting the alias list // to memory. - for (std::map >::iterator + for (std::map, LessRecord >::iterator I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; for (std::set::iterator ASI = I->second.begin(), @@ -485,7 +485,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_SubRegsSet[] = { 0 };\n"; // Loop over all of the registers which have sub-registers, emitting the // sub-registers list to memory. - for (std::map >::iterator + for (std::map, LessRecord>::iterator I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; std::vector SubRegsVector; @@ -499,21 +499,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << "0 };\n"; } - if (!RegisterImmSubRegs.empty()) - OS << "\n\n // Register Immediate Sub-registers Sets...\n"; - - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (std::map >::iterator - I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end(); - I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { "; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; - OS << "0 };\n"; - } - if (!RegisterSuperRegs.empty()) OS << "\n\n // Register Super-registers Sets...\n"; @@ -521,7 +506,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " const unsigned Empty_SuperRegsSet[] = { 0 };\n"; // Loop over all of the registers which have super-registers, emitting the // super-registers list to memory. - for (std::map >::iterator + for (std::map, LessRecord >::iterator I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; @@ -537,7 +522,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -550,16 +535,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { else OS << Reg.getName(); OS << "\",\t\""; - if (!Reg.TheDef->getValueAsString("Name").empty()) { - OS << Reg.TheDef->getValueAsString("Name"); - } else { - // Default to "name". - if (!Reg.TheDef->getValueAsString("AsmName").empty()) - OS << Reg.TheDef->getValueAsString("AsmName"); - else - OS << Reg.getName(); - } - OS << "\",\t"; + OS << Reg.getName() << "\",\t"; if (RegisterAliases.count(Reg.TheDef)) OS << Reg.getName() << "_AliasSet,\t"; else @@ -568,10 +544,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (RegisterImmSubRegs.count(Reg.TheDef)) - OS << Reg.getName() << "_ImmSubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; if (RegisterSuperRegs.count(Reg.TheDef)) OS << Reg.getName() << "_SuperRegsSet },\n"; else @@ -605,16 +577,16 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << "unsigned " << ClassName << "::getSubReg(unsigned RegNo, unsigned Index) const {\n" << " switch (RegNo) {\n" - << " default: abort(); break;\n"; + << " default:\n return 0;\n"; for (std::map > >::iterator I = SubRegVectors.begin(), E = SubRegVectors.end(); I != E; ++I) { OS << " case " << getQualifiedName(I->first) << ":\n"; OS << " switch (Index) {\n"; - OS << " default: abort(); break;\n"; + OS << " default: return 0;\n"; for (unsigned i = 0, e = I->second.size(); i != e; ++i) OS << " case " << (I->second)[i].first << ": return " << getQualifiedName((I->second)[i].second) << ";\n"; - OS << " }; break;\n"; + OS << " };\n" << " break;\n"; } OS << " };\n"; OS << " return 0;\n"; @@ -625,7 +597,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; + << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" + << " SubregHashTable, SubregHashTableSize) {\n" + << "}\n\n"; // Collect all information about dwarf register numbers @@ -633,7 +607,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { unsigned maxLength = 0; for (unsigned i = 0, e = Registers.size(); i != e; ++i) { Record *Reg = Registers[i].TheDef; - std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); + std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); maxLength = std::max((size_t)maxLength, RegNums.size()); if (DwarfRegNums.count(Reg)) cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) @@ -642,8 +616,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) { } // Now we know maximal length of number list. Append -1's, where needed - for (std::map >::iterator - I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) + for (DwarfRegNumsMapTy::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); @@ -661,8 +635,11 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << " default:\n" << " assert(0 && \"Invalid RegNum\");\n" << " return -1;\n"; + + // Sort by name to get a stable order. + - for (std::map >::iterator + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { int RegNo = I->second[i]; if (RegNo != -2)