X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=b3a9dea3beca2c1ea415d6b02f270bf39f21b170;hb=202a7a1e3fa661bf78b98d77de7e2d575facd9ee;hp=702ca7c377247457cc934e23f1b1f8cbda38ca03;hpb=ca561ffcf320e9dbfafcac5efcee81471f3259c3;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 702ca7c3772..b3a9dea3bec 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -25,7 +25,7 @@ using namespace llvm; // runEnums - Print out enum values for all of the registers. void RegisterInfoEmitter::runEnums(raw_ostream &OS) { - CodeGenTarget Target; + CodeGenTarget Target(Records); const std::vector &Registers = Target.getRegisters(); std::string Namespace = Registers[0].TheDef->getValueAsString("Namespace"); @@ -38,7 +38,10 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { OS << "enum {\n NoRegister,\n"; for (unsigned i = 0, e = Registers.size(); i != e; ++i) - OS << " " << Registers[i].getName() << ", \t// " << i+1 << "\n"; + OS << " " << Registers[i].getName() << " = " << + Registers[i].EnumValue << ",\n"; + assert(Registers.size() == Registers[Registers.size()-1].EnumValue && + "Register enum value mismatch!"); OS << " NUM_TARGET_REGS \t// " << Registers.size()+1 << "\n"; OS << "};\n"; if (!Namespace.empty()) @@ -63,7 +66,7 @@ void RegisterInfoEmitter::runEnums(raw_ostream &OS) { void RegisterInfoEmitter::runHeader(raw_ostream &OS) { EmitSourceFileHeader("Register Information Header Fragment", OS); - CodeGenTarget Target; + CodeGenTarget Target(Records); const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; @@ -82,6 +85,7 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { << " { return false; }\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << " unsigned getSubRegIndex(unsigned RegNo, unsigned SubRegNo) const;\n" + << " unsigned composeSubRegIndices(unsigned, unsigned) const;\n" << "};\n\n"; const std::vector &RegisterClasses = @@ -90,12 +94,12 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace << " { // Register classes\n"; - + OS << " enum {\n"; for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; OS << " " << RegisterClasses[i].getName() << "RegClassID"; - OS << " = " << (i+1); + OS << " = " << i; } OS << "\n };\n\n"; @@ -118,16 +122,6 @@ void RegisterInfoEmitter::runHeader(raw_ostream &OS) { OS << "} // End llvm namespace \n"; } -bool isSubRegisterClass(const CodeGenRegisterClass &RC, - std::set &RegSet) { - for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { - Record *Reg = RC.Elements[i]; - if (!RegSet.count(Reg)) - return false; - } - return true; -} - static void addSuperReg(Record *R, Record *S, std::map, LessRecord> &SubRegs, std::map, LessRecord> &SuperRegs, @@ -171,14 +165,28 @@ static void addSubSuperReg(Record *R, Record *S, addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } -// Map SubRegIndex -> Register -typedef std::map SubRegMap; -// Map Register -> SubRegMap -typedef std::map AllSubRegMap; +struct RegisterMaps { + // Map SubRegIndex -> Register + typedef std::map SubRegMap; + // Map Register -> SubRegMap + typedef std::map SubRegMaps; + + SubRegMaps SubReg; + SubRegMap &inferSubRegIndices(Record *Reg); + + // Composite SubRegIndex instances. + // Map (SubRegIndex,SubRegIndex) -> SubRegIndex + typedef DenseMap,Record*> CompositeMap; + CompositeMap Composite; + + // Compute SubRegIndex compositions after inferSubRegIndices has run on all + // registers. + void computeComposites(); +}; // Calculate all subregindices for Reg. Loopy subregs cause infinite recursion. -static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) { - SubRegMap &SRM = ASRM[Reg]; +RegisterMaps::SubRegMap &RegisterMaps::inferSubRegIndices(Record *Reg) { + SubRegMap &SRM = SubReg[Reg]; if (!SRM.empty()) return SRM; std::vector SubRegs = Reg->getValueAsListOfDefs("SubRegs"); @@ -186,19 +194,26 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) { if (SubRegs.size() != Indices.size()) throw "Register " + Reg->getName() + " SubRegIndices doesn't match SubRegs"; - // First insert the direct subregs. + // First insert the direct subregs and make sure they are fully indexed. for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { if (!SRM.insert(std::make_pair(Indices[i], SubRegs[i])).second) throw "SubRegIndex " + Indices[i]->getName() + " appears twice in Register " + Reg->getName(); - inferSubRegIndices(SubRegs[i], ASRM); + inferSubRegIndices(SubRegs[i]); } + // Keep track of inherited subregs and how they can be reached. + // Register -> (SubRegIndex, SubRegIndex) + typedef std::map, LessRecord> OrphanMap; + OrphanMap Orphans; + // Clone inherited subregs. Here the order is important - earlier subregs take // precedence. for (unsigned i = 0, e = SubRegs.size(); i != e; ++i) { - SubRegMap &M = ASRM[SubRegs[i]]; - SRM.insert(M.begin(), M.end()); + SubRegMap &M = SubReg[SubRegs[i]]; + for (SubRegMap::iterator si = M.begin(), se = M.end(); si != se; ++si) + if (!SRM.insert(*si).second) + Orphans[si->second] = std::make_pair(Indices[i], si->first); } // Finally process the composites. @@ -219,8 +234,8 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) { DefInit *IdxInit = dynamic_cast(*di); if (!IdxInit || !IdxInit->getDef()->isSubClassOf("SubRegIndex")) throw "Invalid SubClassIndex in " + Pat->getAsString(); - SubRegMap::const_iterator ni = ASRM[R2].find(IdxInit->getDef()); - if (ni == ASRM[R2].end()) + SubRegMap::const_iterator ni = SubReg[R2].find(IdxInit->getDef()); + if (ni == SubReg[R2].end()) throw "Composite " + Pat->getAsString() + " refers to bad index in " + R2->getName(); R2 = ni->second; @@ -228,10 +243,82 @@ static SubRegMap &inferSubRegIndices(Record *Reg, AllSubRegMap &ASRM) { // Insert composite index. Allow overriding inherited indices etc. SRM[BaseIdxInit->getDef()] = R2; + + // R2 is now directly addressable, no longer an orphan. + Orphans.erase(R2); + } + + // Now, Orphans contains the inherited subregisters without a direct index. + if (!Orphans.empty()) { + errs() << "Error: Register " << getQualifiedName(Reg) + << " inherited subregisters without an index:\n"; + for (OrphanMap::iterator i = Orphans.begin(), e = Orphans.end(); i != e; + ++i) { + errs() << " " << getQualifiedName(i->first) + << " = " << i->second.first->getName() + << ", " << i->second.second->getName() << "\n"; + } + abort(); } return SRM; } +void RegisterMaps::computeComposites() { + for (SubRegMaps::const_iterator sri = SubReg.begin(), sre = SubReg.end(); + sri != sre; ++sri) { + Record *Reg1 = sri->first; + const SubRegMap &SRM1 = sri->second; + for (SubRegMap::const_iterator i1 = SRM1.begin(), e1 = SRM1.end(); + i1 != e1; ++i1) { + Record *Idx1 = i1->first; + Record *Reg2 = i1->second; + // Ignore identity compositions. + if (Reg1 == Reg2) + continue; + // If Reg2 has no subregs, Idx1 doesn't compose. + if (!SubReg.count(Reg2)) + continue; + const SubRegMap &SRM2 = SubReg[Reg2]; + // Try composing Idx1 with another SubRegIndex. + for (SubRegMap::const_iterator i2 = SRM2.begin(), e2 = SRM2.end(); + i2 != e2; ++i2) { + std::pair IdxPair(Idx1, i2->first); + Record *Reg3 = i2->second; + // OK Reg1:IdxPair == Reg3. Find the index with Reg:Idx == Reg3. + for (SubRegMap::const_iterator i1d = SRM1.begin(), e1d = SRM1.end(); + i1d != e1d; ++i1d) { + // Ignore identity compositions. + if (Reg2 == Reg3) + continue; + if (i1d->second == Reg3) { + std::pair Ins = + Composite.insert(std::make_pair(IdxPair, i1d->first)); + // Conflicting composition? + if (!Ins.second && Ins.first->second != i1d->first) { + errs() << "Error: SubRegIndex " << getQualifiedName(Idx1) + << " and " << getQualifiedName(IdxPair.second) + << " compose ambiguously as " + << getQualifiedName(Ins.first->second) << " or " + << getQualifiedName(i1d->first) << "\n"; + abort(); + } + } + } + } + } + } + + // We don't care about the difference between (Idx1, Idx2) -> Idx2 and invalid + // compositions, so remove any mappings of that form. + for (CompositeMap::iterator i = Composite.begin(), e = Composite.end(); + i != e;) { + CompositeMap::iterator j = i; + ++i; + if (j->first.second == j->second) + Composite.erase(j); + } +} + class RegisterSorter { private: std::map, LessRecord> &RegisterSubRegs; @@ -249,7 +336,7 @@ public: // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(raw_ostream &OS) { - CodeGenTarget Target; + CodeGenTarget Target(Records); EmitSourceFileHeader("Register Information Source Fragment", OS); OS << "namespace llvm {\n\n"; @@ -274,7 +361,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - + // Emit the register list now. OS << " // " << Name << " Register Class...\n" << " static const unsigned " << Name @@ -292,12 +379,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Emit the ValueType arrays for each RegisterClass for (unsigned rc = 0, e = RegisterClasses.size(); rc != e; ++rc) { const CodeGenRegisterClass &RC = RegisterClasses[rc]; - + // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName() + "VTs"; - + // Emit the register list now. - OS << " // " << Name + OS << " // " << Name << " Register Class Value Types...\n" << " static const EVT " << Name << "[] = {\n "; @@ -306,7 +393,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << "MVT::Other\n };\n\n"; } OS << "} // end anonymous namespace\n\n"; - + // Now that all of the structs have been emitted, emit the instances. if (!RegisterClasses.empty()) { OS << "namespace " << RegisterClasses[0].Namespace @@ -314,7 +401,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) OS << " " << RegisterClasses[i].getName() << "Class\t" << RegisterClasses[i].getName() << "RegClass;\n"; - + std::map > SuperClassMap; std::map > SuperRegClassMap; OS << "\n"; @@ -404,13 +491,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - std::set RegSet; - for (unsigned i = 0, e = RC.Elements.size(); i != e; ++i) { - Record *Reg = RC.Elements[i]; - RegSet.insert(Reg); - } - - OS << " // " << Name + OS << " // " << Name << " Register Class sub-classes...\n" << " static const TargetRegisterClass* const " << Name << "Subclasses[] = {\n "; @@ -419,22 +500,10 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned rc2 = 0, e2 = RegisterClasses.size(); rc2 != e2; ++rc2) { const CodeGenRegisterClass &RC2 = RegisterClasses[rc2]; - // RC2 is a sub-class of RC if it is a valid replacement for any - // instruction operand where an RC register is required. It must satisfy - // these conditions: - // - // 1. All RC2 registers are also in RC. - // 2. The RC2 spill size must not be smaller that the RC spill size. - // 3. RC2 spill alignment must be compatible with RC. - // // Sub-classes are used to determine if a virtual register can be used // as an instruction operand, or if it must be copied first. + if (rc == rc2 || !RC.hasSubClass(&RC2)) continue; - if (rc == rc2 || RC2.Elements.size() > RC.Elements.size() || - (RC.SpillAlignment && RC2.SpillAlignment % RC.SpillAlignment) || - RC.SpillSize > RC2.SpillSize || !isSubRegisterClass(RC2, RegSet)) - continue; - if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; Empty = false; @@ -458,7 +527,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // Give the register class a legal C name if it's anonymous. std::string Name = RC.TheDef->getName(); - OS << " // " << Name + OS << " // " << Name << " Register Class super-classes...\n" << " static const TargetRegisterClass* const " << Name << "Superclasses[] = {\n "; @@ -472,7 +541,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { const CodeGenRegisterClass &RC2 = RegisterClasses[*II]; if (!Empty) OS << ", "; OS << "&" << getQualifiedName(RC2.TheDef) << "RegClass"; - Empty = false; + Empty = false; } } @@ -484,7 +553,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { const CodeGenRegisterClass &RC = RegisterClasses[i]; OS << RC.MethodBodies << "\n"; - OS << RC.getName() << "Class::" << RC.getName() + OS << RC.getName() << "Class::" << RC.getName() << "Class() : TargetRegisterClass(" << RC.getName() + "RegClassID" << ", " << '\"' << RC.getName() << "\", " @@ -501,7 +570,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << RC.getName() << ", " << RC.getName() << " + " << RC.Elements.size() << ") {}\n"; } - + OS << "}\n"; } @@ -518,7 +587,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { std::map, LessRecord> RegisterAliases; typedef std::map, LessRecord> DwarfRegNumsMapTy; DwarfRegNumsMapTy DwarfRegNums; - + const std::vector &Regs = Target.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -557,7 +626,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegisterAliases); } } - + // Print the SubregHashTable, a simple quadratically probed // hash table for determining if a register is a subregister // of another register. @@ -567,13 +636,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); } - + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); - + unsigned hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set::iterator I = RegisterSubRegs[R].begin(), @@ -588,26 +657,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { SubregHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (SubregHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + SubregHashTable[index*2] = i; SubregHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (SubregHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned SubregHashTable[] = { "; for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (SubregHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; @@ -615,7 +684,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = SubregHashTableSize*2-2; if (SubregHashTable[Idx] != ~0U) { OS << " " @@ -624,14 +693,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned SubregHashTableSize = " << SubregHashTableSize << ";\n"; } else { OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" << " const unsigned SubregHashTableSize = 1;\n"; } - + delete [] SubregHashTable; @@ -643,13 +712,13 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { RegNo[Regs[i].TheDef] = i; NumAliases += RegisterAliases[Regs[i].TheDef].size(); } - + unsigned AliasesHashTableSize = 2 * NextPowerOf2(2 * NumAliases); unsigned* AliasesHashTable = new unsigned[2 * AliasesHashTableSize]; std::fill(AliasesHashTable, AliasesHashTable + 2 * AliasesHashTableSize, ~0U); - + hashMisses = 0; - + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { Record* R = Regs[i].TheDef; for (std::set::iterator I = RegisterAliases[R].begin(), @@ -664,26 +733,26 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { AliasesHashTable[index*2+1] != ~0U) { index = (index + ProbeAmt) & (AliasesHashTableSize-1); ProbeAmt += 2; - + hashMisses++; } - + AliasesHashTable[index*2] = i; AliasesHashTable[index*2+1] = RegNo[RJ]; } } - + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; - + if (AliasesHashTableSize) { std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); - + OS << " const unsigned AliasesHashTable[] = { "; for (unsigned i = 0; i < AliasesHashTableSize - 1; ++i) { if (i != 0) // Insert spaces for nice formatting. OS << " "; - + if (AliasesHashTable[2*i] != ~0U) { OS << getQualifiedName(Regs[AliasesHashTable[2*i]].TheDef) << ", " << getQualifiedName(Regs[AliasesHashTable[2*i+1]].TheDef) << ", \n"; @@ -691,7 +760,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; } } - + unsigned Idx = AliasesHashTableSize*2-2; if (AliasesHashTable[Idx] != ~0U) { OS << " " @@ -700,26 +769,24 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } else { OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; } - + OS << " const unsigned AliasesHashTableSize = " << AliasesHashTableSize << ";\n"; } else { OS << " const unsigned AliasesHashTable[] = { ~0U, ~0U };\n" << " const unsigned AliasesHashTableSize = 1;\n"; } - + delete [] AliasesHashTable; if (!RegisterAliases.empty()) - OS << "\n\n // Register Alias Sets...\n"; + OS << "\n\n // Register Overlap Lists...\n"; - // Emit the empty alias list - OS << " const unsigned Empty_AliasSet[] = { 0 };\n"; - // Loop over all of the registers which have aliases, emitting the alias list - // to memory. + // Emit an overlap list for all registers. for (std::map, LessRecord >::iterator I = RegisterAliases.begin(), E = RegisterAliases.end(); I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_AliasSet[] = { "; + OS << " const unsigned " << I->first->getName() << "_Overlaps[] = { " + << getQualifiedName(I->first) << ", "; for (std::set::iterator ASI = I->second.begin(), E = I->second.end(); ASI != E; ++ASI) OS << getQualifiedName(*ASI) << ", "; @@ -735,6 +802,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // sub-registers list to memory. for (std::map, LessRecord>::iterator I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { + if (I->second.empty()) + continue; OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; std::vector SubRegsVector; for (std::set::iterator ASI = I->second.begin(), @@ -756,6 +825,8 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { // super-registers list to memory. for (std::map, LessRecord >::iterator I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { + if (I->second.empty()) + continue; OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; std::vector SuperRegsVector; @@ -777,16 +848,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { for (unsigned i = 0, e = Regs.size(); i != e; ++i) { const CodeGenRegister &Reg = Regs[i]; OS << " { \""; - OS << Reg.getName() << "\",\t"; - if (RegisterAliases.count(Reg.TheDef)) - OS << Reg.getName() << "_AliasSet,\t"; - else - OS << "Empty_AliasSet,\t"; - if (RegisterSubRegs.count(Reg.TheDef)) + OS << Reg.getName() << "\",\t" << Reg.getName() << "_Overlaps,\t"; + if (!RegisterSubRegs[Reg.TheDef].empty()) OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (RegisterSuperRegs.count(Reg.TheDef)) + if (!RegisterSuperRegs[Reg.TheDef].empty()) OS << Reg.getName() << "_SuperRegsSet },\n"; else OS << "Empty_SuperRegsSet },\n"; @@ -807,7 +874,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { std::string ClassName = Target.getName() + "GenRegisterInfo"; // Calculate the mapping of subregister+index pairs to physical registers. - AllSubRegMap AllSRM; + RegisterMaps RegMaps; // Emit the subregister + index mapping function based on the information // calculated above. @@ -816,14 +883,14 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " switch (RegNo) {\n" << " default:\n return 0;\n"; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - SubRegMap &SRM = inferSubRegIndices(Regs[i].TheDef, AllSRM); + RegisterMaps::SubRegMap &SRM = RegMaps.inferSubRegIndices(Regs[i].TheDef); if (SRM.empty()) continue; OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; OS << " switch (Index) {\n"; OS << " default: return 0;\n"; - for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie; - ++ii) + for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(), + ie = SRM.end(); ii != ie; ++ii) OS << " case " << getQualifiedName(ii->first) << ": return " << getQualifiedName(ii->second) << ";\n"; OS << " };\n" << " break;\n"; @@ -837,12 +904,12 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " switch (RegNo) {\n" << " default:\n return 0;\n"; for (unsigned i = 0, e = Regs.size(); i != e; ++i) { - SubRegMap &SRM = AllSRM[Regs[i].TheDef]; + RegisterMaps::SubRegMap &SRM = RegMaps.SubReg[Regs[i].TheDef]; if (SRM.empty()) continue; OS << " case " << getQualifiedName(Regs[i].TheDef) << ":\n"; - for (SubRegMap::const_iterator ii = SRM.begin(), ie = SRM.end(); ii != ie; - ++ii) + for (RegisterMaps::SubRegMap::const_iterator ii = SRM.begin(), + ie = SRM.end(); ii != ie; ++ii) OS << " if (SubRegNo == " << getQualifiedName(ii->second) << ") return " << getQualifiedName(ii->first) << ";\n"; OS << " return 0;\n"; @@ -850,7 +917,32 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { OS << " };\n"; OS << " return 0;\n"; OS << "}\n\n"; - + + // Emit composeSubRegIndices + RegMaps.computeComposites(); + OS << "unsigned " << ClassName + << "::composeSubRegIndices(unsigned IdxA, unsigned IdxB) const {\n" + << " switch (IdxA) {\n" + << " default:\n return IdxB;\n"; + for (unsigned i = 0, e = SubRegIndices.size(); i != e; ++i) { + bool Open = false; + for (unsigned j = 0; j != e; ++j) { + if (Record *Comp = RegMaps.Composite.lookup( + std::make_pair(SubRegIndices[i], SubRegIndices[j]))) { + if (!Open) { + OS << " case " << getQualifiedName(SubRegIndices[i]) + << ": switch(IdxB) {\n default: return IdxB;\n"; + Open = true; + } + OS << " case " << getQualifiedName(SubRegIndices[j]) + << ": return " << getQualifiedName(Comp) << ";\n"; + } + } + if (Open) + OS << " }\n"; + } + OS << " }\n}\n\n"; + // Emit the constructor of the class... OS << ClassName << "::" << ClassName << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" @@ -877,7 +969,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } // Now we know maximal length of number list. Append -1's, where needed - for (DwarfRegNumsMapTy::iterator + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) I->second.push_back(-1); @@ -889,18 +981,18 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { << " default:\n" << " assert(0 && \"Unknown DWARF flavour\");\n" << " return -1;\n"; - + for (unsigned i = 0, e = maxLength; i != e; ++i) { OS << " case " << i << ":\n" << " switch (RegNum) {\n" << " default:\n" << " assert(0 && \"Invalid RegNum\");\n" << " return -1;\n"; - + // Sort by name to get a stable order. - - for (DwarfRegNumsMapTy::iterator + + for (DwarfRegNumsMapTy::iterator I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { int RegNo = I->second[i]; if (RegNo != -2) @@ -913,7 +1005,7 @@ void RegisterInfoEmitter::run(raw_ostream &OS) { } OS << " };\n"; } - + OS << " };\n}\n\n"; OS << "} // End llvm namespace \n";