X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=d514bf7deb8fc02e5a7fb0ce9e1725cc9f855dae;hb=56e0f87dcc8dcb004c8f2c421c4806377439fc21;hp=b9253cfd3e84e408227a29e6361d265ae65fcca7;hpb=cc51c3195374645b18918458bac02e85b8c27db6;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index b9253cfd3e8..d514bf7deb8 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -64,6 +64,8 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { << " virtual int getDwarfRegNumFull(unsigned RegNum, " << "unsigned Flavour) const;\n" << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n"; @@ -221,7 +223,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) OS << getEnumName(RC.VTs[i]) << ", "; @@ -416,7 +418,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " };\n"; // Emit register sub-registers / super-registers, aliases... - std::map > RegisterImmSubRegs; std::map > RegisterSubRegs; std::map > RegisterSuperRegs; std::map > RegisterAliases; @@ -457,11 +458,86 @@ void RegisterInfoEmitter::run(std::ostream &OS) { cerr << "Warning: register " << getQualifiedName(SubReg) << " specified as a sub-register of " << getQualifiedName(R) << " multiple times!\n"; - RegisterImmSubRegs[R].insert(SubReg); addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, RegisterAliases); } } + + // Print the SubregHashTable, a simple quadratically probed + // hash table for determining if a register is a subregister + // of another register. + unsigned NumSubRegs = 0; + std::map RegNo; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + RegNo[Regs[i].TheDef] = i; + NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); + } + + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); + unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; + std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); + + unsigned hashMisses = 0; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record* R = Regs[i].TheDef; + for (std::set::iterator I = RegisterSubRegs[R].begin(), + E = RegisterSubRegs[R].end(); I != E; ++I) { + Record* RJ = *I; + // We have to increase the indices of both registers by one when + // computing the hash because, in the generated code, there + // will be an extra empty slot at register 0. + size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); + unsigned ProbeAmt = 2; + while (SubregHashTable[index*2] != ~0U && + SubregHashTable[index*2+1] != ~0U) { + index = (index + ProbeAmt) & (SubregHashTableSize-1); + ProbeAmt += 2; + + hashMisses++; + } + + SubregHashTable[index*2] = i; + SubregHashTable[index*2+1] = RegNo[RJ]; + } + } + + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; + + if (SubregHashTableSize) { + std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); + + OS << " const unsigned SubregHashTable[] = { "; + for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { + if (i != 0) + // Insert spaces for nice formatting. + OS << " "; + + if (SubregHashTable[2*i] != ~0U) { + OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; + } + } + + unsigned Idx = SubregHashTableSize*2-2; + if (SubregHashTable[Idx] != ~0U) { + OS << " " + << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; + } + + OS << " const unsigned SubregHashTableSize = " + << SubregHashTableSize << ";\n"; + } else { + OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" + << " const unsigned SubregHashTableSize = 1;\n"; + } + + delete [] SubregHashTable; if (!RegisterAliases.empty()) OS << "\n\n // Register Alias Sets...\n"; @@ -500,21 +576,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << "0 };\n"; } - if (!RegisterImmSubRegs.empty()) - OS << "\n\n // Register Immediate Sub-registers Sets...\n"; - - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (std::map >::iterator - I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end(); - I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { "; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; - OS << "0 };\n"; - } - if (!RegisterSuperRegs.empty()) OS << "\n\n // Register Super-registers Sets...\n"; @@ -538,7 +599,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -551,16 +612,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { else OS << Reg.getName(); OS << "\",\t\""; - if (!Reg.TheDef->getValueAsString("Name").empty()) { - OS << Reg.TheDef->getValueAsString("Name"); - } else { - // Default to "name". - if (!Reg.TheDef->getValueAsString("AsmName").empty()) - OS << Reg.TheDef->getValueAsString("AsmName"); - else - OS << Reg.getName(); - } - OS << "\",\t"; + OS << Reg.getName() << "\",\t"; if (RegisterAliases.count(Reg.TheDef)) OS << Reg.getName() << "_AliasSet,\t"; else @@ -569,10 +621,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (RegisterImmSubRegs.count(Reg.TheDef)) - OS << Reg.getName() << "_ImmSubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; if (RegisterSuperRegs.count(Reg.TheDef)) OS << Reg.getName() << "_SuperRegsSet },\n"; else @@ -626,7 +674,9 @@ void RegisterInfoEmitter::run(std::ostream &OS) { << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; + << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" + << " SubregHashTable, SubregHashTableSize) {\n" + << "}\n\n"; // Collect all information about dwarf register numbers