X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FRegisterInfoEmitter.cpp;h=d514bf7deb8fc02e5a7fb0ce9e1725cc9f855dae;hb=abb1f1688172cf6f3c5bc539841da76053f23533;hp=48262babdf163f8d7b2968b19d1ca8a88e30dbbc;hpb=483ec21d90295c146b5555ed66c16860bcfff942;p=oota-llvm.git diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp index 48262babdf1..d514bf7deb8 100644 --- a/utils/TableGen/RegisterInfoEmitter.cpp +++ b/utils/TableGen/RegisterInfoEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by the LLVM research group and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -21,6 +21,7 @@ #include "llvm/ADT/STLExtras.h" #include "llvm/Support/Streams.h" #include +#include using namespace llvm; // runEnums - Print out enum values for all of the registers. @@ -52,15 +53,19 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { const std::string &TargetName = Target.getName(); std::string ClassName = TargetName + "GenRegisterInfo"; - OS << "#include \"llvm/Target/MRegisterInfo.h\"\n"; + OS << "#include \"llvm/Target/TargetRegisterInfo.h\"\n"; OS << "#include \n\n"; OS << "namespace llvm {\n\n"; - OS << "struct " << ClassName << " : public MRegisterInfo {\n" - << " " << ClassName + OS << "struct " << ClassName << " : public TargetRegisterInfo {\n" + << " explicit " << ClassName << "(int CallFrameSetupOpcode = -1, int CallFrameDestroyOpcode = -1);\n" - << " virtual int getDwarfRegNum(unsigned RegNum) const;\n" + << " virtual int getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const;\n" + << " virtual int getDwarfRegNum(unsigned RegNum, bool isEH) const = 0;\n" + << " virtual bool needsStackRealignment(const MachineFunction &) const\n" + << " { return false; }\n" << " unsigned getSubReg(unsigned RegNo, unsigned Index) const;\n" << "};\n\n"; @@ -75,7 +80,7 @@ void RegisterInfoEmitter::runHeader(std::ostream &OS) { for (unsigned i = 0, e = RegisterClasses.size(); i != e; ++i) { if (i) OS << ",\n"; OS << " " << RegisterClasses[i].getName() << "RegClassID"; - if (!i) OS << " = 1"; + OS << " = " << (i+1); } OS << "\n };\n\n"; @@ -111,11 +116,10 @@ bool isSubRegisterClass(const CodeGenRegisterClass &RC, static void addSuperReg(Record *R, Record *S, std::map > &SubRegs, std::map > &SuperRegs, - std::map > &Aliases, - RegisterInfoEmitter &RIE) { + std::map > &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" - << " register " << RIE.getQualifiedName(R) + << " register " << getQualifiedName(R) << " and its sub-registers?\n"; abort(); } @@ -127,32 +131,45 @@ static void addSuperReg(Record *R, Record *S, if (SuperRegs.count(S)) for (std::set::iterator I = SuperRegs[S].begin(), E = SuperRegs[S].end(); I != E; ++I) - addSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE); + addSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } static void addSubSuperReg(Record *R, Record *S, std::map > &SubRegs, std::map > &SuperRegs, - std::map > &Aliases, - RegisterInfoEmitter &RIE) { + std::map > &Aliases) { if (R == S) { cerr << "Error: recursive sub-register relationship between" - << " register " << RIE.getQualifiedName(R) + << " register " << getQualifiedName(R) << " and its sub-registers?\n"; abort(); } if (!SubRegs[R].insert(S).second) return; - addSuperReg(S, R, SubRegs, SuperRegs, Aliases, RIE); + addSuperReg(S, R, SubRegs, SuperRegs, Aliases); Aliases[R].insert(S); Aliases[S].insert(R); if (SubRegs.count(S)) for (std::set::iterator I = SubRegs[S].begin(), E = SubRegs[S].end(); I != E; ++I) - addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases, RIE); + addSubSuperReg(R, *I, SubRegs, SuperRegs, Aliases); } +class RegisterSorter { +private: + std::map > &RegisterSubRegs; + +public: + RegisterSorter(std::map > &RS) + : RegisterSubRegs(RS) {}; + + bool operator()(Record *RegA, Record *RegB) { + // B is sub-register of A. + return RegisterSubRegs.count(RegA) && RegisterSubRegs[RegA].count(RegB); + } +}; + // RegisterInfoEmitter::run - Main register file description emitter. // void RegisterInfoEmitter::run(std::ostream &OS) { @@ -206,7 +223,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the register list now. OS << " // " << Name << " Register Class Value Types...\n" - << " static const MVT::ValueType " << Name + << " static const MVT " << Name << "[] = {\n "; for (unsigned i = 0, e = RC.VTs.size(); i != e; ++i) OS << getEnumName(RC.VTs[i]) << ", "; @@ -401,11 +418,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << " };\n"; // Emit register sub-registers / super-registers, aliases... - std::map > RegisterImmSubRegs; std::map > RegisterSubRegs; std::map > RegisterSuperRegs; std::map > RegisterAliases; std::map > > SubRegVectors; + std::map > DwarfRegNums; + const std::vector &Regs = Target.getRegisters(); for (unsigned i = 0, e = Regs.size(); i != e; ++i) { @@ -440,11 +458,86 @@ void RegisterInfoEmitter::run(std::ostream &OS) { cerr << "Warning: register " << getQualifiedName(SubReg) << " specified as a sub-register of " << getQualifiedName(R) << " multiple times!\n"; - RegisterImmSubRegs[R].insert(SubReg); addSubSuperReg(R, SubReg, RegisterSubRegs, RegisterSuperRegs, - RegisterAliases, *this); + RegisterAliases); } } + + // Print the SubregHashTable, a simple quadratically probed + // hash table for determining if a register is a subregister + // of another register. + unsigned NumSubRegs = 0; + std::map RegNo; + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + RegNo[Regs[i].TheDef] = i; + NumSubRegs += RegisterSubRegs[Regs[i].TheDef].size(); + } + + unsigned SubregHashTableSize = 2 * NextPowerOf2(2 * NumSubRegs); + unsigned* SubregHashTable = new unsigned[2 * SubregHashTableSize]; + std::fill(SubregHashTable, SubregHashTable + 2 * SubregHashTableSize, ~0U); + + unsigned hashMisses = 0; + + for (unsigned i = 0, e = Regs.size(); i != e; ++i) { + Record* R = Regs[i].TheDef; + for (std::set::iterator I = RegisterSubRegs[R].begin(), + E = RegisterSubRegs[R].end(); I != E; ++I) { + Record* RJ = *I; + // We have to increase the indices of both registers by one when + // computing the hash because, in the generated code, there + // will be an extra empty slot at register 0. + size_t index = ((i+1) + (RegNo[RJ]+1) * 37) & (SubregHashTableSize-1); + unsigned ProbeAmt = 2; + while (SubregHashTable[index*2] != ~0U && + SubregHashTable[index*2+1] != ~0U) { + index = (index + ProbeAmt) & (SubregHashTableSize-1); + ProbeAmt += 2; + + hashMisses++; + } + + SubregHashTable[index*2] = i; + SubregHashTable[index*2+1] = RegNo[RJ]; + } + } + + OS << "\n\n // Number of hash collisions: " << hashMisses << "\n"; + + if (SubregHashTableSize) { + std::string Namespace = Regs[0].TheDef->getValueAsString("Namespace"); + + OS << " const unsigned SubregHashTable[] = { "; + for (unsigned i = 0; i < SubregHashTableSize - 1; ++i) { + if (i != 0) + // Insert spaces for nice formatting. + OS << " "; + + if (SubregHashTable[2*i] != ~0U) { + OS << getQualifiedName(Regs[SubregHashTable[2*i]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[2*i+1]].TheDef) << ", \n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister, \n"; + } + } + + unsigned Idx = SubregHashTableSize*2-2; + if (SubregHashTable[Idx] != ~0U) { + OS << " " + << getQualifiedName(Regs[SubregHashTable[Idx]].TheDef) << ", " + << getQualifiedName(Regs[SubregHashTable[Idx+1]].TheDef) << " };\n"; + } else { + OS << Namespace << "::NoRegister, " << Namespace << "::NoRegister };\n"; + } + + OS << " const unsigned SubregHashTableSize = " + << SubregHashTableSize << ";\n"; + } else { + OS << " const unsigned SubregHashTable[] = { ~0U, ~0U };\n" + << " const unsigned SubregHashTableSize = 1;\n"; + } + + delete [] SubregHashTable; if (!RegisterAliases.empty()) OS << "\n\n // Register Alias Sets...\n"; @@ -472,24 +565,14 @@ void RegisterInfoEmitter::run(std::ostream &OS) { for (std::map >::iterator I = RegisterSubRegs.begin(), E = RegisterSubRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SubRegsSet[] = { "; + std::vector SubRegsVector; for (std::set::iterator ASI = I->second.begin(), E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; - OS << "0 };\n"; - } - - if (!RegisterImmSubRegs.empty()) - OS << "\n\n // Register Immediate Sub-registers Sets...\n"; - - // Loop over all of the registers which have sub-registers, emitting the - // sub-registers list to memory. - for (std::map >::iterator - I = RegisterImmSubRegs.begin(), E = RegisterImmSubRegs.end(); - I != E; ++I) { - OS << " const unsigned " << I->first->getName() << "_ImmSubRegsSet[] = { "; - for (std::set::iterator ASI = I->second.begin(), - E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; + SubRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SubRegsVector.begin(), SubRegsVector.end(), RS); + for (unsigned i = 0, e = SubRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SubRegsVector[i]) << ", "; OS << "0 };\n"; } @@ -503,14 +586,20 @@ void RegisterInfoEmitter::run(std::ostream &OS) { for (std::map >::iterator I = RegisterSuperRegs.begin(), E = RegisterSuperRegs.end(); I != E; ++I) { OS << " const unsigned " << I->first->getName() << "_SuperRegsSet[] = { "; + + std::vector SuperRegsVector; for (std::set::iterator ASI = I->second.begin(), E = I->second.end(); ASI != E; ++ASI) - OS << getQualifiedName(*ASI) << ", "; + SuperRegsVector.push_back(*ASI); + RegisterSorter RS(RegisterSubRegs); + std::stable_sort(SuperRegsVector.begin(), SuperRegsVector.end(), RS); + for (unsigned i = 0, e = SuperRegsVector.size(); i != e; ++i) + OS << getQualifiedName(SuperRegsVector[i]) << ", "; OS << "0 };\n"; } OS<<"\n const TargetRegisterDesc RegisterDescriptors[] = { // Descriptors\n"; - OS << " { \"NOREG\",\t0,\t0,\t0,\t0 },\n"; + OS << " { \"NOREG\",\t\"NOREG\",\t0,\t0,\t0 },\n"; // Now that register alias and sub-registers sets have been emitted, emit the // register descriptors now. @@ -518,11 +607,12 @@ void RegisterInfoEmitter::run(std::ostream &OS) { for (unsigned i = 0, e = Registers.size(); i != e; ++i) { const CodeGenRegister &Reg = Registers[i]; OS << " { \""; - if (!Reg.TheDef->getValueAsString("Name").empty()) - OS << Reg.TheDef->getValueAsString("Name"); + if (!Reg.TheDef->getValueAsString("AsmName").empty()) + OS << Reg.TheDef->getValueAsString("AsmName"); else OS << Reg.getName(); - OS << "\",\t"; + OS << "\",\t\""; + OS << Reg.getName() << "\",\t"; if (RegisterAliases.count(Reg.TheDef)) OS << Reg.getName() << "_AliasSet,\t"; else @@ -531,10 +621,6 @@ void RegisterInfoEmitter::run(std::ostream &OS) { OS << Reg.getName() << "_SubRegsSet,\t"; else OS << "Empty_SubRegsSet,\t"; - if (RegisterImmSubRegs.count(Reg.TheDef)) - OS << Reg.getName() << "_ImmSubRegsSet,\t"; - else - OS << "Empty_SubRegsSet,\t"; if (RegisterSuperRegs.count(Reg.TheDef)) OS << Reg.getName() << "_SuperRegsSet },\n"; else @@ -586,25 +672,62 @@ void RegisterInfoEmitter::run(std::ostream &OS) { // Emit the constructor of the class... OS << ClassName << "::" << ClassName << "(int CallFrameSetupOpcode, int CallFrameDestroyOpcode)\n" - << " : MRegisterInfo(RegisterDescriptors, " << Registers.size()+1 + << " : TargetRegisterInfo(RegisterDescriptors, " << Registers.size()+1 << ", RegisterClasses, RegisterClasses+" << RegisterClasses.size() <<",\n " - << " CallFrameSetupOpcode, CallFrameDestroyOpcode) {}\n\n"; + << " CallFrameSetupOpcode, CallFrameDestroyOpcode,\n" + << " SubregHashTable, SubregHashTableSize) {\n" + << "}\n\n"; - // Emit information about the dwarf register numbers. - OS << "int " << ClassName << "::getDwarfRegNum(unsigned RegNum) const {\n"; - OS << " static const int DwarfRegNums[] = { -1, // NoRegister"; + // Collect all information about dwarf register numbers + + // First, just pull all provided information to the map + unsigned maxLength = 0; for (unsigned i = 0, e = Registers.size(); i != e; ++i) { - if (!(i % 16)) OS << "\n "; - const CodeGenRegister &Reg = Registers[i]; - int DwarfRegNum = Reg.TheDef->getValueAsInt("DwarfNumber"); - OS << DwarfRegNum; - if ((i + 1) != e) OS << ", "; + Record *Reg = Registers[i].TheDef; + std::vector RegNums = Reg->getValueAsListOfInts("DwarfNumbers"); + maxLength = std::max((size_t)maxLength, RegNums.size()); + if (DwarfRegNums.count(Reg)) + cerr << "Warning: DWARF numbers for register " << getQualifiedName(Reg) + << "specified multiple times\n"; + DwarfRegNums[Reg] = RegNums; } - OS << "\n };\n"; - OS << " assert(RegNum < (sizeof(DwarfRegNums)/sizeof(int)) &&\n"; - OS << " \"RegNum exceeds number of registers\");\n"; - OS << " return DwarfRegNums[RegNum];\n"; - OS << "}\n\n"; + + // Now we know maximal length of number list. Append -1's, where needed + for (std::map >::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) + for (unsigned i = I->second.size(), e = maxLength; i != e; ++i) + I->second.push_back(-1); + + // Emit information about the dwarf register numbers. + OS << "int " << ClassName << "::getDwarfRegNumFull(unsigned RegNum, " + << "unsigned Flavour) const {\n" + << " switch (Flavour) {\n" + << " default:\n" + << " assert(0 && \"Unknown DWARF flavour\");\n" + << " return -1;\n"; + + for (unsigned i = 0, e = maxLength; i != e; ++i) { + OS << " case " << i << ":\n" + << " switch (RegNum) {\n" + << " default:\n" + << " assert(0 && \"Invalid RegNum\");\n" + << " return -1;\n"; + + for (std::map >::iterator + I = DwarfRegNums.begin(), E = DwarfRegNums.end(); I != E; ++I) { + int RegNo = I->second[i]; + if (RegNo != -2) + OS << " case " << getQualifiedName(I->first) << ":\n" + << " return " << RegNo << ";\n"; + else + OS << " case " << getQualifiedName(I->first) << ":\n" + << " assert(0 && \"Invalid register for this mode\");\n" + << " return -1;\n"; + } + OS << " };\n"; + } + + OS << " };\n}\n\n"; OS << "} // End llvm namespace \n"; }