X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FSubtargetEmitter.cpp;h=928fa4bee9009851a784637b648e9ce819e7c59f;hb=c017bc1c1e2fa0995e957f6c2ada1339832bb221;hp=919ac664efa0e1df07756a8b48cb9ab21d8531c5;hpb=1a55180238dbcf11113f610aea010447e51f595b;p=oota-llvm.git diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 919ac664efa..928fa4bee90 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -31,24 +31,30 @@ void SubtargetEmitter::Enumeration(raw_ostream &OS, // Open enumeration OS << "enum {\n"; - + // For each record - for (unsigned i = 0, N = DefList.size(); i < N;) { + unsigned N = DefList.size(); + if (N > 64) { + errs() << "Too many (> 64) subtarget features!\n"; + exit(1); + } + + for (unsigned i = 0; i < N;) { // Next record Record *Def = DefList[i]; - + // Get and emit name OS << " " << Def->getName(); - + // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1 << " << i; + if (isBits) OS << " = " << " 1ULL << " << i; // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // Close enumeration OS << "};\n"; } @@ -66,7 +72,7 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n"; - + // For each feature for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { // Next feature @@ -75,20 +81,20 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { const std::string &Name = Feature->getName(); const std::string &CommandLineName = Feature->getValueAsString("Name"); const std::string &Desc = Feature->getValueAsString("Desc"); - + if (CommandLineName.empty()) continue; - + // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } OS << " { " << "\"" << CommandLineName << "\", " << "\"" << Desc << "\", " << Name << ", "; - const std::vector &ImpliesList = + const std::vector &ImpliesList = Feature->getValueAsListOfDefs("Implies"); - + if (ImpliesList.empty()) { - OS << "0"; + OS << "0ULL"; } else { for (unsigned j = 0, M = ImpliesList.size(); j < M;) { OS << ImpliesList[j]->getName(); @@ -97,13 +103,13 @@ void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { } OS << " }"; - + // Depending on 'if more in the list' emit comma if ((i + 1) < N) OS << ","; - + OS << "\n"; } - + // End feature table OS << "};\n"; @@ -126,39 +132,39 @@ void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n"; - + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor Record *Processor = ProcessorList[i]; const std::string &Name = Processor->getValueAsString("Name"); - const std::vector &FeatureList = + const std::vector &FeatureList = Processor->getValueAsListOfDefs("Features"); - + // Emit as { "cpu", "description", f1 | f2 | ... fn }, OS << " { " << "\"" << Name << "\", " << "\"Select the " << Name << " processor\", "; - + if (FeatureList.empty()) { - OS << "0"; + OS << "0ULL"; } else { for (unsigned j = 0, M = FeatureList.size(); j < M;) { OS << FeatureList[j]->getName(); if (++j < M) OS << " | "; } } - + // The "0" is for the "implies" section of this data structure. - OS << ", 0 }"; - + OS << ", 0ULL }"; + // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; @@ -172,13 +178,10 @@ void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // CollectAllItinClasses - Gathers and enumerates all the itinerary classes. // Returns itinerary class count. // -unsigned SubtargetEmitter::CollectAllItinClasses(raw_ostream &OS, - std::map &ItinClassesMap) { - // Gather and sort all itinerary classes - std::vector ItinClassList = - Records.getAllDerivedDefinitions("InstrItinClass"); - std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); - +unsigned SubtargetEmitter:: +CollectAllItinClasses(raw_ostream &OS, + std::map &ItinClassesMap, + std::vector &ItinClassList) { // For each itinerary class unsigned N = ItinClassList.size(); for (unsigned i = 0; i < N; i++) { @@ -188,7 +191,7 @@ unsigned SubtargetEmitter::CollectAllItinClasses(raw_ostream &OS, // Assign itinerary class a unique number ItinClassesMap[ItinClass->getName()] = i; } - + // Emit size of table OS<<"\nenum {\n"; OS<<" ItinClassesSize = " << N << "\n"; @@ -199,12 +202,14 @@ unsigned SubtargetEmitter::CollectAllItinClasses(raw_ostream &OS, } // -// FormItineraryString - Compose a string containing the data initialization -// for the specified itinerary. N is the number of stages. +// FormItineraryStageString - Compose a string containing the stage +// data initialization for the specified itinerary. N is the number +// of stages. // -void SubtargetEmitter::FormItineraryString(Record *ItinData, - std::string &ItinString, - unsigned &NStages) { +void SubtargetEmitter::FormItineraryStageString(const std::string &Name, + Record *ItinData, + std::string &ItinString, + unsigned &NStages) { // Get states list const std::vector &StageList = ItinData->getValueAsListOfDefs("Stages"); @@ -214,21 +219,27 @@ void SubtargetEmitter::FormItineraryString(Record *ItinData, for (unsigned i = 0; i < N;) { // Next stage const Record *Stage = StageList[i]; - - // Form string as ,{ cycles, u1 | u2 | ... | un } + + // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); ItinString += " { " + itostr(Cycles) + ", "; - + // Get unit list const std::vector &UnitList = Stage->getValueAsListOfDefs("Units"); - + // For each unit for (unsigned j = 0, M = UnitList.size(); j < M;) { // Add name and bitwise or - ItinString += UnitList[j]->getName(); + ItinString += Name + "FU::" + UnitList[j]->getName(); if (++j < M) ItinString += " | "; } - + + int TimeInc = Stage->getValueAsInt("TimeInc"); + ItinString += ", " + itostr(TimeInc); + + int Kind = Stage->getValueAsInt("Kind"); + ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind); + // Close off stage ItinString += " }"; if (++i < N) ItinString += ", "; @@ -236,102 +247,235 @@ void SubtargetEmitter::FormItineraryString(Record *ItinData, } // -// EmitStageData - Generate unique itinerary stages. Record itineraries for -// processors. +// FormItineraryOperandCycleString - Compose a string containing the +// operand cycle initialization for the specified itinerary. N is the +// number of operands that has cycles specified. // -void SubtargetEmitter::EmitStageData(raw_ostream &OS, +void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, + std::string &ItinString, unsigned &NOperandCycles) { + // Get operand cycle list + const std::vector &OperandCycleList = + ItinData->getValueAsListOfInts("OperandCycles"); + + // For each operand cycle + unsigned N = NOperandCycles = OperandCycleList.size(); + for (unsigned i = 0; i < N;) { + // Next operand cycle + const int OCycle = OperandCycleList[i]; + + ItinString += " " + itostr(OCycle); + if (++i < N) ItinString += ", "; + } +} + +void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, + Record *ItinData, + std::string &ItinString, + unsigned NOperandCycles) { + const std::vector &BypassList = + ItinData->getValueAsListOfDefs("Bypasses"); + unsigned N = BypassList.size(); + unsigned i = 0; + for (; i < N;) { + ItinString += Name + "Bypass::" + BypassList[i]->getName(); + if (++i < NOperandCycles) ItinString += ", "; + } + for (; i < NOperandCycles;) { + ItinString += " 0"; + if (++i < NOperandCycles) ItinString += ", "; + } +} + +// +// EmitStageAndOperandCycleData - Generate unique itinerary stages and +// operand cycle tables. Record itineraries for processors. +// +void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses, - std::map &ItinClassesMap, + std::map &ItinClassesMap, + std::vector &ItinClassList, std::vector > &ProcList) { // Gather processor iteraries std::vector ProcItinList = Records.getAllDerivedDefinitions("ProcessorItineraries"); - + // If just no itinerary then don't bother if (ProcItinList.size() < 2) return; + // Emit functional units for all the itineraries. + for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) { + // Next record + Record *Proc = ProcItinList[i]; + + std::vector FUs = Proc->getValueAsListOfDefs("FU"); + if (FUs.empty()) + continue; + + const std::string &Name = Proc->getName(); + OS << "\n// Functional units for itineraries \"" << Name << "\"\n" + << "namespace " << Name << "FU {\n"; + + for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) + OS << " const unsigned " << FUs[j]->getName() + << " = 1 << " << j << ";\n"; + + OS << "}\n"; + + std::vector BPs = Proc->getValueAsListOfDefs("BP"); + if (BPs.size()) { + OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name + << "\"\n" << "namespace " << Name << "Bypass {\n"; + + OS << " const unsigned NoBypass = 0;\n"; + for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) + OS << " const unsigned " << BPs[j]->getName() + << " = 1 << " << j << ";\n"; + + OS << "}\n"; + } + } + // Begin stages table - OS << "static const llvm::InstrStage Stages[] = {\n" - " { 0, 0 }, // No itinerary\n"; - - unsigned StageCount = 1; - unsigned ItinEnum = 1; - std::map ItinMap; + std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n"; + StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; + + // Begin operand cycle table + std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n"; + OperandCycleTable += " 0, // No itinerary\n"; + + // Begin pipeline bypass table + std::string BypassTable = "static const unsigned ForwardingPathes[] = {\n"; + BypassTable += " 0, // No itinerary\n"; + + unsigned StageCount = 1, OperandCycleCount = 1; + std::map ItinStageMap, ItinOperandMap; for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { // Next record Record *Proc = ProcItinList[i]; - + // Get processor itinerary name const std::string &Name = Proc->getName(); - + // Skip default if (Name == "NoItineraries") continue; - + // Create and expand processor itinerary to cover all itinerary classes std::vector ItinList; ItinList.resize(NItinClasses); - + // Get itinerary data list std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); - + // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { // Next itinerary data Record *ItinData = ItinDataList[j]; - + // Get string and stage count - std::string ItinString; + std::string ItinStageString; unsigned NStages; - FormItineraryString(ItinData, ItinString, NStages); - - // Check to see if it already exists - unsigned Find = ItinMap[ItinString]; - - // If new itinerary - if (Find == 0) { - // Emit as { cycles, u1 | u2 | ... | un }, // index - OS << ItinString << ", // " << ItinEnum << "\n"; - // Record Itin class number. - ItinMap[ItinString] = Find = StageCount; - StageCount += NStages; - ItinEnum++; + FormItineraryStageString(Name, ItinData, ItinStageString, NStages); + + // Get string and operand cycle count + std::string ItinOperandCycleString; + unsigned NOperandCycles; + FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, + NOperandCycles); + + std::string ItinBypassString; + FormItineraryBypassString(Name, ItinData, ItinBypassString, + NOperandCycles); + + // Check to see if stage already exists and create if it doesn't + unsigned FindStage = 0; + if (NStages > 0) { + FindStage = ItinStageMap[ItinStageString]; + if (FindStage == 0) { + // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices + StageTable += ItinStageString + ", // " + itostr(StageCount); + if (NStages > 1) + StageTable += "-" + itostr(StageCount + NStages - 1); + StageTable += "\n"; + // Record Itin class number. + ItinStageMap[ItinStageString] = FindStage = StageCount; + StageCount += NStages; + } + } + + // Check to see if operand cycle already exists and create if it doesn't + unsigned FindOperandCycle = 0; + if (NOperandCycles > 0) { + std::string ItinOperandString = ItinOperandCycleString+ItinBypassString; + FindOperandCycle = ItinOperandMap[ItinOperandString]; + if (FindOperandCycle == 0) { + // Emit as cycle, // index + OperandCycleTable += ItinOperandCycleString + ", // "; + std::string OperandIdxComment = itostr(OperandCycleCount); + if (NOperandCycles > 1) + OperandIdxComment += "-" + + itostr(OperandCycleCount + NOperandCycles - 1); + OperandCycleTable += OperandIdxComment + "\n"; + // Record Itin class number. + ItinOperandMap[ItinOperandCycleString] = + FindOperandCycle = OperandCycleCount; + // Emit as bypass, // index + BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n"; + OperandCycleCount += NOperandCycles; + } } - - // Set up itinerary as location and location + stage count - InstrItinerary Intinerary = { Find, Find + NStages }; // Locate where to inject into processor itinerary table const std::string &Name = ItinData->getValueAsDef("TheClass")->getName(); - Find = ItinClassesMap[Name]; - + unsigned Find = ItinClassesMap[Name]; + + // Set up itinerary as location and location + stage count + unsigned NumUOps = ItinClassList[Find]->getValueAsInt("NumMicroOps"); + InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, + FindOperandCycle, + FindOperandCycle + NOperandCycles}; + // Inject - empty slots will be 0, 0 ItinList[Find] = Intinerary; } - + // Add process itinerary to list ProcList.push_back(ItinList); } - + // Closing stage - OS << " { 0, 0 } // End itinerary\n"; - // End stages table - OS << "};\n"; - - // Emit size of table + StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End itinerary\n"; + StageTable += "};\n"; + + // Closing operand cycles + OperandCycleTable += " 0 // End itinerary\n"; + OperandCycleTable += "};\n"; + + BypassTable += " 0 // End itinerary\n"; + BypassTable += "};\n"; + + // Emit tables. + OS << StageTable; + OS << OperandCycleTable; + OS << BypassTable; + + // Emit size of tables OS<<"\nenum {\n"; - OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n"; + OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n"; + OS<<" OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)\n"; OS<<"};\n"; } // // EmitProcessorData - Generate data for processor itineraries. // -void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, - std::vector > &ProcList) { +void SubtargetEmitter:: +EmitProcessorData(raw_ostream &OS, + std::vector &ItinClassList, + std::vector > &ProcList) { // Get an iterator for processor itinerary stages std::vector >::iterator ProcListIter = ProcList.begin(); - + // For each processor itinerary std::vector Itins = Records.getAllDerivedDefinitions("ProcessorItineraries"); @@ -341,33 +485,38 @@ void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, // Get processor itinerary name const std::string &Name = Itin->getName(); - + // Skip default if (Name == "NoItineraries") continue; // Begin processor itinerary table OS << "\n"; OS << "static const llvm::InstrItinerary " << Name << "[] = {\n"; - + // For each itinerary class std::vector &ItinList = *ProcListIter++; - for (unsigned j = 0, M = ItinList.size(); j < M;) { + assert(ItinList.size() == ItinClassList.size() && "bad itinerary"); + for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { InstrItinerary &Intinerary = ItinList[j]; - - // Emit in the form of { first, last } // index - if (Intinerary.First == 0) { - OS << " { 0, 0 }"; + + // Emit in the form of + // { firstStage, lastStage, firstCycle, lastCycle } // index + if (Intinerary.FirstStage == 0) { + OS << " { 1, 0, 0, 0, 0 }"; } else { - OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }"; + OS << " { " << + Intinerary.NumMicroOps << ", " << + Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << + Intinerary.LastOperandCycle << " }"; } - - // If more in list add comma - if (++j < M) OS << ","; - - OS << " // " << (j - 1) << "\n"; + + OS << ", // " << j << " " << ItinClassList[j]->getName() << "\n"; } - + // End processor itinerary table + OS << " { 1, ~0U, ~0U, ~0U, ~0U } // end marker\n"; OS << "};\n"; } } @@ -385,7 +534,7 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { OS << "\n"; OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n"; - + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor @@ -394,20 +543,20 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { const std::string &Name = Processor->getValueAsString("Name"); const std::string &ProcItin = Processor->getValueAsDef("ProcItin")->getName(); - + // Emit as { "cpu", procinit }, OS << " { " << "\"" << Name << "\", " << "(void *)&" << ProcItin; - + OS << " }"; - + // Depending on ''if more in the list'' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; @@ -423,18 +572,24 @@ void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { // void SubtargetEmitter::EmitData(raw_ostream &OS) { std::map ItinClassesMap; - std::vector > ProcList; - + // Gather and sort all itinerary classes + std::vector ItinClassList = + Records.getAllDerivedDefinitions("InstrItinClass"); + std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); + // Enumerate all the itinerary classes - unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap); + unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap, + ItinClassList); // Make sure the rest is worth the effort HasItineraries = NItinClasses != 1; // Ignore NoItinerary. - + if (HasItineraries) { + std::vector > ProcList; // Emit the stage data - EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList); + EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, + ItinClassList, ProcList); // Emit the processor itinerary data - EmitProcessorData(OS, ProcList); + EmitProcessorData(OS, ItinClassList, ProcList); // Emit the processor lookup data EmitProcessorLookup(OS); } @@ -449,15 +604,17 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { Records.getAllDerivedDefinitions("SubtargetFeature"); std::sort(Features.begin(), Features.end(), LessRecord()); - OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" - << "// subtarget options.\n" + OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" + << "// subtarget options.\n" << "std::string llvm::"; OS << Target; OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" << " const std::string &CPU) {\n" + << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" + << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" << " SubtargetFeatures Features(FS);\n" << " Features.setCPUIfNone(CPU);\n" - << " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" + << " uint64_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" << " FeatureKV, FeatureKVSize);\n"; for (unsigned i = 0; i < Features.size(); i++) { @@ -471,7 +628,7 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { OS << " if ((Bits & " << Instance << ") != 0) " << Attribute << " = " << Value << ";\n"; else - OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << + OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << " < " << Value << ") " << Attribute << " = " << Value << ";\n"; } @@ -479,7 +636,8 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { OS << "\n" << " InstrItinerary *Itinerary = (InstrItinerary *)" << "Features.getInfo(ProcItinKV, ProcItinKVSize);\n" - << " InstrItins = InstrItineraryData(Stages, Itinerary);\n"; + << " InstrItins = InstrItineraryData(Stages, OperandCycles, " + << "ForwardingPathes, Itinerary);\n"; } OS << " return Features.getCPU();\n" @@ -490,15 +648,17 @@ void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { // SubtargetEmitter::run - Main subtarget enumeration emitter. // void SubtargetEmitter::run(raw_ostream &OS) { - Target = CodeGenTarget().getName(); + Target = CodeGenTarget(Records).getName(); EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); + OS << "#include \"llvm/Support/Debug.h\"\n"; + OS << "#include \"llvm/Support/raw_ostream.h\"\n"; OS << "#include \"llvm/Target/SubtargetFeature.h\"\n"; OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n"; - - Enumeration(OS, "FuncUnit", true); - OS<<"\n"; + +// Enumeration(OS, "FuncUnit", true); +// OS<<"\n"; // Enumeration(OS, "InstrItinClass", false); // OS<<"\n"; Enumeration(OS, "SubtargetFeature", true);