X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FSubtargetEmitter.cpp;h=b04eaf88f73a3ddd1013f516dd195ae3baf52a8c;hb=162d3ba464c263256b6876674ceee2cc99969adf;hp=e6429eaecb848500a899f47e1aae97bae78dd296;hpb=f7bcde085440d1fd90eba8980ed9c512bc58824d;p=oota-llvm.git diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index e6429eaecb8..b04eaf88f73 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -2,8 +2,8 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by James M. Laskey and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // @@ -19,33 +19,15 @@ #include using namespace llvm; -// -// Record sort by name function. -// -struct LessRecord { - bool operator()(const Record *Rec1, const Record *Rec2) const { - return Rec1->getName() < Rec2->getName(); - } -}; - -// -// Record sort by field "Name" function. -// -struct LessRecordFieldName { - bool operator()(const Record *Rec1, const Record *Rec2) const { - return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name"); - } -}; - // // Enumeration - Emit the specified class as an enumeration. // -void SubtargetEmitter::Enumeration(std::ostream &OS, +void SubtargetEmitter::Enumeration(raw_ostream &OS, const char *ClassName, bool isBits) { // Get all records of class and sort std::vector DefList = Records.getAllDerivedDefinitions(ClassName); - sort(DefList.begin(), DefList.end(), LessRecord()); + std::sort(DefList.begin(), DefList.end(), LessRecord()); // Open enumeration OS << "enum {\n"; @@ -56,13 +38,12 @@ void SubtargetEmitter::Enumeration(std::ostream &OS, Record *Def = DefList[i]; // Get and emit name - std::string Name = Def->getName(); - OS << " " << Name; + OS << " " << Def->getName(); // If bit flags then emit expression (1 << i) if (isBits) OS << " = " << " 1 << " << i; - // Depending on if more in the list emit comma + // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; OS << "\n"; @@ -73,37 +54,52 @@ void SubtargetEmitter::Enumeration(std::ostream &OS, } // -// FeatureKeyValues - Emit data of all the subtarget features. Used by command -// line. +// FeatureKeyValues - Emit data of all the subtarget features. Used by the +// command line. // -void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) { +void SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { // Gather and sort all the features std::vector FeatureList = Records.getAllDerivedDefinitions("SubtargetFeature"); - sort(FeatureList.begin(), FeatureList.end(), LessRecord()); + std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" - << "static llvm::SubtargetFeatureKV FeatureKV[] = {\n"; + << "static const llvm::SubtargetFeatureKV FeatureKV[] = {\n"; // For each feature - for (unsigned i = 0, N = FeatureList.size(); i < N;) { + for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { // Next feature Record *Feature = FeatureList[i]; - std::string Name = Feature->getName(); - std::string CommandLineName = Feature->getValueAsString("Name"); - std::string Desc = Feature->getValueAsString("Desc"); + const std::string &Name = Feature->getName(); + const std::string &CommandLineName = Feature->getValueAsString("Name"); + const std::string &Desc = Feature->getValueAsString("Desc"); + + if (CommandLineName.empty()) continue; - // Emit as { "feature", "decription", feactureEnum } + // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } OS << " { " << "\"" << CommandLineName << "\", " << "\"" << Desc << "\", " - << Name - << " }"; + << Name << ", "; + + const std::vector &ImpliesList = + Feature->getValueAsListOfDefs("Implies"); - // Depending on if more in the list emit comma - if (++i < N) OS << ","; + if (ImpliesList.empty()) { + OS << "0"; + } else { + for (unsigned j = 0, M = ImpliesList.size(); j < M;) { + OS << ImpliesList[j]->getName(); + if (++j < M) OS << " | "; + } + } + + OS << " }"; + + // Depending on 'if more in the list' emit comma + if ((i + 1) < N) OS << ","; OS << "\n"; } @@ -121,11 +117,11 @@ void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) { // CPUKeyValues - Emit data of all the subtarget processors. Used by command // line. // -void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { +void SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // Gather and sort processor information std::vector ProcessorList = Records.getAllDerivedDefinitions("Processor"); - sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); + std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" @@ -136,8 +132,9 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { // Next processor Record *Processor = ProcessorList[i]; - std::string Name = Processor->getValueAsString("Name"); - std::vector FeatureList = Processor->getValueAsListDef("Features"); + const std::string &Name = Processor->getValueAsString("Name"); + const std::vector &FeatureList = + Processor->getValueAsListOfDefs("Features"); // Emit as { "cpu", "description", f1 | f2 | ... fn }, OS << " { " @@ -148,16 +145,15 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { OS << "0"; } else { for (unsigned j = 0, M = FeatureList.size(); j < M;) { - Record *Feature = FeatureList[j]; - std::string Name = Feature->getName(); - OS << Name; + OS << FeatureList[j]->getName(); if (++j < M) OS << " | "; } } - OS << " }"; + // The "0" is for the "implies" section of this data structure. + OS << ", 0 }"; - // Depending on if more in the list emit comma + // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; OS << "\n"; @@ -176,71 +172,104 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { // CollectAllItinClasses - Gathers and enumerates all the itinerary classes. // Returns itinerary class count. // -unsigned SubtargetEmitter::CollectAllItinClasses(std::map - &ItinClassesMap) { +unsigned SubtargetEmitter::CollectAllItinClasses(raw_ostream &OS, + std::map &ItinClassesMap) { // Gather and sort all itinerary classes std::vector ItinClassList = Records.getAllDerivedDefinitions("InstrItinClass"); - sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); + std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); // For each itinerary class unsigned N = ItinClassList.size(); for (unsigned i = 0; i < N; i++) { // Next itinerary class - Record *ItinClass = ItinClassList[i]; + const Record *ItinClass = ItinClassList[i]; // Get name of itinerary class - std::string Name = ItinClass->getName(); // Assign itinerary class a unique number - ItinClassesMap[Name] = i; + ItinClassesMap[ItinClass->getName()] = i; } + // Emit size of table + OS<<"\nenum {\n"; + OS<<" ItinClassesSize = " << N << "\n"; + OS<<"};\n"; + // Return itinerary class count return N; } // -// FormItineraryString - Compose a string containing the data initialization -// for the specified itinerary. N is the number of stages. +// FormItineraryStageString - Compose a string containing the stage +// data initialization for the specified itinerary. N is the number +// of stages. // -void SubtargetEmitter::FormItineraryString(Record *ItinData, - std::string &ItinString, - unsigned &NStages) { +void SubtargetEmitter::FormItineraryStageString(const std::string &Name, + Record *ItinData, + std::string &ItinString, + unsigned &NStages) { // Get states list - std::vector StageList = ItinData->getValueAsListDef("Stages"); + const std::vector &StageList = + ItinData->getValueAsListOfDefs("Stages"); // For each stage unsigned N = NStages = StageList.size(); - for (unsigned i = 0; i < N; i++) { + for (unsigned i = 0; i < N;) { // Next stage - Record *Stage = StageList[i]; + const Record *Stage = StageList[i]; - // Form string as ,{ cycles, u1 | u2 | ... | un } + // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); - ItinString += " ,{ " + itostr(Cycles) + ", "; + ItinString += " { " + itostr(Cycles) + ", "; // Get unit list - std::vector UnitList = Stage->getValueAsListDef("Units"); + const std::vector &UnitList = Stage->getValueAsListOfDefs("Units"); // For each unit for (unsigned j = 0, M = UnitList.size(); j < M;) { - // Next unit - Record *Unit = UnitList[j]; - // Add name and bitwise or - ItinString += Unit->getName(); + ItinString += Name + "FU::" + UnitList[j]->getName(); if (++j < M) ItinString += " | "; } + int TimeInc = Stage->getValueAsInt("TimeInc"); + ItinString += ", " + itostr(TimeInc); + + int Kind = Stage->getValueAsInt("Kind"); + ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind); + // Close off stage ItinString += " }"; + if (++i < N) ItinString += ", "; } } // -// EmitStageData - Generate unique itinerary stages. Record itineraries for -// processors. +// FormItineraryOperandCycleString - Compose a string containing the +// operand cycle initialization for the specified itinerary. N is the +// number of operands that has cycles specified. // -void SubtargetEmitter::EmitStageData(std::ostream &OS, +void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, + std::string &ItinString, unsigned &NOperandCycles) { + // Get operand cycle list + const std::vector &OperandCycleList = + ItinData->getValueAsListOfInts("OperandCycles"); + + // For each operand cycle + unsigned N = NOperandCycles = OperandCycleList.size(); + for (unsigned i = 0; i < N;) { + // Next operand cycle + const int OCycle = OperandCycleList[i]; + + ItinString += " " + itostr(OCycle); + if (++i < N) ItinString += ", "; + } +} + +// +// EmitStageAndOperandCycleData - Generate unique itinerary stages and +// operand cycle tables. Record itineraries for processors. +// +void SubtargetEmitter::EmitStageAndOperandCycleData(raw_ostream &OS, unsigned NItinClasses, std::map &ItinClassesMap, std::vector > &ProcList) { @@ -251,18 +280,43 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS, // If just no itinerary then don't bother if (ProcItinList.size() < 2) return; + // Emit functional units for all the itineraries. + for (unsigned i = 0, N = ProcItinList.size(); i < N; ++i) { + // Next record + Record *Proc = ProcItinList[i]; + + std::vector FUs = Proc->getValueAsListOfDefs("FU"); + if (FUs.empty()) + continue; + + const std::string &Name = Proc->getName(); + OS << "\n// Functional units for itineraries \"" << Name << "\"\n" + << "namespace " << Name << "FU {\n"; + + for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) + OS << " const unsigned " << FUs[j]->getName() + << " = 1 << " << j << ";\n"; + + OS << "}\n"; + } + // Begin stages table - OS << "static llvm::InstrStage Stages[] = {\n" - " { 0, 0 } // No itinerary\n"; + std::string StageTable = "\nstatic const llvm::InstrStage Stages[] = {\n"; + StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; - unsigned ItinEnum = 1; - std::map ItinMap; + // Begin operand cycle table + std::string OperandCycleTable = "static const unsigned OperandCycles[] = {\n"; + OperandCycleTable += " 0, // No itinerary\n"; + + unsigned StageCount = 1, OperandCycleCount = 1; + unsigned ItinStageEnum = 1, ItinOperandCycleEnum = 1; + std::map ItinStageMap, ItinOperandCycleMap; for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { // Next record Record *Proc = ProcItinList[i]; // Get processor itinerary name - std::string Name = Proc->getName(); + const std::string &Name = Proc->getName(); // Skip default if (Name == "NoItineraries") continue; @@ -272,7 +326,7 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS, ItinList.resize(NItinClasses); // Get itinerary data list - std::vector ItinDataList = Proc->getValueAsListDef("IID"); + std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); // For each itinerary data for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { @@ -280,26 +334,53 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS, Record *ItinData = ItinDataList[j]; // Get string and stage count - std::string ItinString; + std::string ItinStageString; unsigned NStages; - FormItineraryString(ItinData, ItinString, NStages); + FormItineraryStageString(Name, ItinData, ItinStageString, NStages); + + // Get string and operand cycle count + std::string ItinOperandCycleString; + unsigned NOperandCycles; + FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, + NOperandCycles); - // Check to see if it already exists - unsigned Find = ItinMap[ItinString]; + // Check to see if stage already exists and create if it doesn't + unsigned FindStage = 0; + if (NStages > 0) { + FindStage = ItinStageMap[ItinStageString]; + if (FindStage == 0) { + // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // index + StageTable += ItinStageString + ", // " + itostr(ItinStageEnum) + "\n"; + // Record Itin class number. + ItinStageMap[ItinStageString] = FindStage = StageCount; + StageCount += NStages; + ItinStageEnum++; + } + } - // If new itinerary - if (Find == 0) { - // Emit as ,{ cycles, u1 | u2 | ... | un } // index - OS << ItinString << " // " << ItinEnum << "\n"; - ItinMap[ItinString] = Find = ItinEnum++; + // Check to see if operand cycle already exists and create if it doesn't + unsigned FindOperandCycle = 0; + if (NOperandCycles > 0) { + FindOperandCycle = ItinOperandCycleMap[ItinOperandCycleString]; + if (FindOperandCycle == 0) { + // Emit as cycle, // index + OperandCycleTable += ItinOperandCycleString + ", // " + + itostr(ItinOperandCycleEnum) + "\n"; + // Record Itin class number. + ItinOperandCycleMap[ItinOperandCycleString] = + FindOperandCycle = OperandCycleCount; + OperandCycleCount += NOperandCycles; + ItinOperandCycleEnum++; + } } // Set up itinerary as location and location + stage count - InstrItinerary Intinerary = { Find, Find + NStages }; + InstrItinerary Intinerary = { FindStage, FindStage + NStages, + FindOperandCycle, FindOperandCycle + NOperandCycles}; // Locate where to inject into processor itinerary table - std::string Name = ItinData->getValueAsDef("TheClass")->getName(); - Find = ItinClassesMap[Name]; + const std::string &Name = ItinData->getValueAsDef("TheClass")->getName(); + unsigned Find = ItinClassesMap[Name]; // Inject - empty slots will be 0, 0 ItinList[Find] = Intinerary; @@ -309,14 +390,29 @@ void SubtargetEmitter::EmitStageData(std::ostream &OS, ProcList.push_back(ItinList); } - // End stages table - OS << "};\n"; + // Closing stage + StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End itinerary\n"; + StageTable += "};\n"; + + // Closing operand cycles + OperandCycleTable += " 0 // End itinerary\n"; + OperandCycleTable += "};\n"; + + // Emit tables. + OS << StageTable; + OS << OperandCycleTable; + + // Emit size of tables + OS<<"\nenum {\n"; + OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage),\n"; + OS<<" OperandCyclesSize = sizeof(OperandCycles)/sizeof(unsigned)\n"; + OS<<"};\n"; } // -// EmitProcessData - Generate data for processor itineraries. +// EmitProcessorData - Generate data for processor itineraries. // -void SubtargetEmitter::EmitProcessData(std::ostream &OS, +void SubtargetEmitter::EmitProcessorData(raw_ostream &OS, std::vector > &ProcList) { // Get an iterator for processor itinerary stages std::vector >::iterator @@ -330,100 +426,171 @@ void SubtargetEmitter::EmitProcessData(std::ostream &OS, Record *Itin = Itins[i]; // Get processor itinerary name - std::string Name = Itin->getName(); + const std::string &Name = Itin->getName(); // Skip default if (Name == "NoItineraries") continue; // Begin processor itinerary table OS << "\n"; - OS << "static llvm::InstrItinerary " << Name << "[] = {\n"; + OS << "static const llvm::InstrItinerary " << Name << "[] = {\n"; // For each itinerary class std::vector &ItinList = *ProcListIter++; - unsigned ItinIndex = 0; - for (unsigned j = 0, M = ItinList.size(); j < M;) { + for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { InstrItinerary &Intinerary = ItinList[j]; - // Emit in the form of { first, last } // index - if (Intinerary.First == 0) { - OS << " { 0, 0 }"; + // Emit in the form of + // { firstStage, lastStage, firstCycle, lastCycle } // index + if (Intinerary.FirstStage == 0) { + OS << " { 0, 0, 0, 0 }"; } else { - OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }"; + OS << " { " << Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << + Intinerary.LastOperandCycle << " }"; } - // If more in list add comma - if (++j < M) OS << ","; - - OS << " // " << (j - 1) << "\n"; + OS << ", // " << j << "\n"; } // End processor itinerary table + OS << " { ~0U, ~0U, ~0U, ~0U } // end marker\n"; OS << "};\n"; } } +// +// EmitProcessorLookup - generate cpu name to itinerary lookup table. +// +void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { + // Gather and sort processor information + std::vector ProcessorList = + Records.getAllDerivedDefinitions("Processor"); + std::sort(ProcessorList.begin(), ProcessorList.end(), LessRecordFieldName()); + + // Begin processor table + OS << "\n"; + OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" + << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n"; + + // For each processor + for (unsigned i = 0, N = ProcessorList.size(); i < N;) { + // Next processor + Record *Processor = ProcessorList[i]; + + const std::string &Name = Processor->getValueAsString("Name"); + const std::string &ProcItin = + Processor->getValueAsDef("ProcItin")->getName(); + + // Emit as { "cpu", procinit }, + OS << " { " + << "\"" << Name << "\", " + << "(void *)&" << ProcItin; + + OS << " }"; + + // Depending on ''if more in the list'' emit comma + if (++i < N) OS << ","; + + OS << "\n"; + } + + // End processor table + OS << "};\n"; + + // Emit size of table + OS<<"\nenum {\n"; + OS<<" ProcItinKVSize = sizeof(ProcItinKV)/" + "sizeof(llvm::SubtargetInfoKV)\n"; + OS<<"};\n"; +} + // // EmitData - Emits all stages and itineries, folding common patterns. // -void SubtargetEmitter::EmitData(std::ostream &OS) { +void SubtargetEmitter::EmitData(raw_ostream &OS) { std::map ItinClassesMap; std::vector > ProcList; // Enumerate all the itinerary classes - unsigned NItinClasses = CollectAllItinClasses(ItinClassesMap); - // Emit the stage data - EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList); - // Emit the processor itinerary data - EmitProcessData(OS, ProcList); + unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap); + // Make sure the rest is worth the effort + HasItineraries = NItinClasses != 1; // Ignore NoItinerary. + + if (HasItineraries) { + // Emit the stage data + EmitStageAndOperandCycleData(OS, NItinClasses, ItinClassesMap, ProcList); + // Emit the processor itinerary data + EmitProcessorData(OS, ProcList); + // Emit the processor lookup data + EmitProcessorLookup(OS); + } } // // ParseFeaturesFunction - Produces a subtarget specific function for parsing // the subtarget features string. // -void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) { +void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS) { std::vector Features = Records.getAllDerivedDefinitions("SubtargetFeature"); - sort(Features.begin(), Features.end(), LessRecord()); + std::sort(Features.begin(), Features.end(), LessRecord()); OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" - "// subtarget options.\n" - "void llvm::"; + << "// subtarget options.\n" + << "std::string llvm::"; OS << Target; OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" - " const std::string &CPU) {\n" - " SubtargetFeatures Features(FS);\n" - " Features.setCPUIfNone(CPU);\n" - " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" - " FeatureKV, FeatureKVSize);\n"; - + << " const std::string &CPU) {\n" + << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" + << " DEBUG(dbgs() << \"\\nCPU:\" << CPU);\n" + << " SubtargetFeatures Features(FS);\n" + << " Features.setCPUIfNone(CPU);\n" + << " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" + << " FeatureKV, FeatureKVSize);\n"; + for (unsigned i = 0; i < Features.size(); i++) { // Next record Record *R = Features[i]; - std::string Instance = R->getName(); - std::string Name = R->getValueAsString("Name"); - std::string Type = R->getValueAsString("Type"); - std::string Attribute = R->getValueAsString("Attribute"); - - OS << " " << Attribute << " = (Bits & " << Instance << ") != 0;\n"; + const std::string &Instance = R->getName(); + const std::string &Value = R->getValueAsString("Value"); + const std::string &Attribute = R->getValueAsString("Attribute"); + + if (Value=="true" || Value=="false") + OS << " if ((Bits & " << Instance << ") != 0) " + << Attribute << " = " << Value << ";\n"; + else + OS << " if ((Bits & " << Instance << ") != 0 && " << Attribute << + " < " << Value << ") " << Attribute << " = " << Value << ";\n"; + } + + if (HasItineraries) { + OS << "\n" + << " InstrItinerary *Itinerary = (InstrItinerary *)" + << "Features.getInfo(ProcItinKV, ProcItinKVSize);\n" + << " InstrItins = InstrItineraryData(Stages, OperandCycles, Itinerary);\n"; } - OS << "}\n"; + + OS << " return Features.getCPU();\n" + << "}\n"; } -// +// // SubtargetEmitter::run - Main subtarget enumeration emitter. // -void SubtargetEmitter::run(std::ostream &OS) { +void SubtargetEmitter::run(raw_ostream &OS) { Target = CodeGenTarget().getName(); EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); + OS << "#include \"llvm/Support/Debug.h\"\n"; + OS << "#include \"llvm/Support/raw_ostream.h\"\n"; OS << "#include \"llvm/Target/SubtargetFeature.h\"\n"; OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n"; - - Enumeration(OS, "FuncUnit", true); - OS<<"\n"; + +// Enumeration(OS, "FuncUnit", true); +// OS<<"\n"; // Enumeration(OS, "InstrItinClass", false); // OS<<"\n"; Enumeration(OS, "SubtargetFeature", true);