X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FSubtargetEmitter.cpp;h=b3bf4aa14ce37993d16c8bd15bbb9f9fafa77ed2;hb=4feb647283db0ea4660941d3ac4202947b1ce196;hp=091cbc679b3b3ddeb8577d5b3fe3389c09c29fe5;hpb=19c95507443ebd4f1cee80917d540c8bd27f8fe1;p=oota-llvm.git diff --git a/utils/TableGen/SubtargetEmitter.cpp b/utils/TableGen/SubtargetEmitter.cpp index 091cbc679b3..b3bf4aa14ce 100644 --- a/utils/TableGen/SubtargetEmitter.cpp +++ b/utils/TableGen/SubtargetEmitter.cpp @@ -2,127 +2,197 @@ // // The LLVM Compiler Infrastructure // -// This file was developed by James M. Laskey and is distributed under -// the University of Illinois Open Source License. See LICENSE.TXT for details. +// This file is distributed under the University of Illinois Open Source +// License. See LICENSE.TXT for details. // //===----------------------------------------------------------------------===// // -// This tablegen backend emits subtarget enumerations. The format is in a state -// flux and will be tightened up when integration to scheduling is complete. +// This tablegen backend emits subtarget enumerations. // //===----------------------------------------------------------------------===// -#include "SubtargetEmitter.h" #include "CodeGenTarget.h" -#include "Record.h" +#include "CodeGenSchedule.h" #include "llvm/ADT/StringExtras.h" +#include "llvm/MC/MCInstrItineraries.h" #include "llvm/Support/Debug.h" +#include "llvm/TableGen/Record.h" +#include "llvm/TableGen/TableGenBackend.h" #include +#include +#include +#include using namespace llvm; -// -// Record sort by name function. -// -struct LessRecord { - bool operator()(const Record *Rec1, const Record *Rec2) const { - return Rec1->getName() < Rec2->getName(); - } -}; +namespace { +class SubtargetEmitter { + + RecordKeeper &Records; + CodeGenSchedModels &SchedModels; + std::string Target; + + void Enumeration(raw_ostream &OS, const char *ClassName, bool isBits); + unsigned FeatureKeyValues(raw_ostream &OS); + unsigned CPUKeyValues(raw_ostream &OS); + void FormItineraryStageString(const std::string &Names, + Record *ItinData, std::string &ItinString, + unsigned &NStages); + void FormItineraryOperandCycleString(Record *ItinData, std::string &ItinString, + unsigned &NOperandCycles); + void FormItineraryBypassString(const std::string &Names, + Record *ItinData, + std::string &ItinString, unsigned NOperandCycles); + void EmitStageAndOperandCycleData(raw_ostream &OS, + std::vector > + &ProcItinLists); + void EmitItineraries(raw_ostream &OS, + std::vector > + &ProcItinLists); + void EmitProcessorProp(raw_ostream &OS, const Record *R, const char *Name, + char Separator); + void EmitProcessorModels(raw_ostream &OS); + void EmitProcessorLookup(raw_ostream &OS); + void EmitSchedModel(raw_ostream &OS); + void ParseFeaturesFunction(raw_ostream &OS, unsigned NumFeatures, + unsigned NumProcs); + +public: + SubtargetEmitter(RecordKeeper &R, CodeGenTarget &TGT): + Records(R), SchedModels(TGT.getSchedModels()), Target(TGT.getName()) {} + + void run(raw_ostream &o); -// -// Record sort by field "Name" function. -// -struct LessRecordFieldName { - bool operator()(const Record *Rec1, const Record *Rec2) const { - return Rec1->getValueAsString("Name") < Rec2->getValueAsString("Name"); - } }; +} // End anonymous namespace // // Enumeration - Emit the specified class as an enumeration. // -void SubtargetEmitter::Enumeration(std::ostream &OS, +void SubtargetEmitter::Enumeration(raw_ostream &OS, const char *ClassName, bool isBits) { // Get all records of class and sort std::vector DefList = Records.getAllDerivedDefinitions(ClassName); std::sort(DefList.begin(), DefList.end(), LessRecord()); - // Open enumeration - OS << "enum {\n"; - - // For each record - for (unsigned i = 0, N = DefList.size(); i < N;) { - // Next record - Record *Def = DefList[i]; - - // Get and emit name - std::string Name = Def->getName(); - OS << " " << Name; - - // If bit flags then emit expression (1 << i) - if (isBits) OS << " = " << " 1 << " << i; + unsigned N = DefList.size(); + if (N == 0) + return; + if (N > 64) { + errs() << "Too many (> 64) subtarget features!\n"; + exit(1); + } - // Depending on 'if more in the list' emit comma - if (++i < N) OS << ","; - - OS << "\n"; + OS << "namespace " << Target << " {\n"; + + // For bit flag enumerations with more than 32 items, emit constants. + // Emit an enum for everything else. + if (isBits && N > 32) { + // For each record + for (unsigned i = 0; i < N; i++) { + // Next record + Record *Def = DefList[i]; + + // Get and emit name and expression (1 << i) + OS << " const uint64_t " << Def->getName() << " = 1ULL << " << i << ";\n"; + } + } else { + // Open enumeration + OS << "enum {\n"; + + // For each record + for (unsigned i = 0; i < N;) { + // Next record + Record *Def = DefList[i]; + + // Get and emit name + OS << " " << Def->getName(); + + // If bit flags then emit expression (1 << i) + if (isBits) OS << " = " << " 1ULL << " << i; + + // Depending on 'if more in the list' emit comma + if (++i < N) OS << ","; + + OS << "\n"; + } + + // Close enumeration + OS << "};\n"; } - - // Close enumeration - OS << "};\n"; + + OS << "}\n"; } // -// FeatureKeyValues - Emit data of all the subtarget features. Used by command -// line. +// FeatureKeyValues - Emit data of all the subtarget features. Used by the +// command line. // -void SubtargetEmitter::FeatureKeyValues(std::ostream &OS) { +unsigned SubtargetEmitter::FeatureKeyValues(raw_ostream &OS) { // Gather and sort all the features std::vector FeatureList = Records.getAllDerivedDefinitions("SubtargetFeature"); - std::sort(FeatureList.begin(), FeatureList.end(), LessRecord()); + + if (FeatureList.empty()) + return 0; + + std::sort(FeatureList.begin(), FeatureList.end(), LessRecordFieldName()); // Begin feature table OS << "// Sorted (by key) array of values for CPU features.\n" - << "static llvm::SubtargetFeatureKV FeatureKV[] = {\n"; - + << "extern const llvm::SubtargetFeatureKV " << Target + << "FeatureKV[] = {\n"; + // For each feature - for (unsigned i = 0, N = FeatureList.size(); i < N;) { + unsigned NumFeatures = 0; + for (unsigned i = 0, N = FeatureList.size(); i < N; ++i) { // Next feature Record *Feature = FeatureList[i]; - std::string Name = Feature->getName(); - std::string CommandLineName = Feature->getValueAsString("Name"); - std::string Desc = Feature->getValueAsString("Desc"); - - // Emit as { "feature", "decription", feactureEnum } + const std::string &Name = Feature->getName(); + const std::string &CommandLineName = Feature->getValueAsString("Name"); + const std::string &Desc = Feature->getValueAsString("Desc"); + + if (CommandLineName.empty()) continue; + + // Emit as { "feature", "description", featureEnum, i1 | i2 | ... | in } OS << " { " << "\"" << CommandLineName << "\", " << "\"" << Desc << "\", " - << Name - << " }"; - + << Target << "::" << Name << ", "; + + const std::vector &ImpliesList = + Feature->getValueAsListOfDefs("Implies"); + + if (ImpliesList.empty()) { + OS << "0ULL"; + } else { + for (unsigned j = 0, M = ImpliesList.size(); j < M;) { + OS << Target << "::" << ImpliesList[j]->getName(); + if (++j < M) OS << " | "; + } + } + + OS << " }"; + ++NumFeatures; + // Depending on 'if more in the list' emit comma - if (++i < N) OS << ","; - + if ((i + 1) < N) OS << ","; + OS << "\n"; } - + // End feature table OS << "};\n"; - // Emit size of table - OS<<"\nenum {\n"; - OS<<" FeatureKVSize = sizeof(FeatureKV)/sizeof(llvm::SubtargetFeatureKV)\n"; - OS<<"};\n"; + return NumFeatures; } // // CPUKeyValues - Emit data of all the subtarget processors. Used by command // line. // -void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { +unsigned SubtargetEmitter::CPUKeyValues(raw_ostream &OS) { // Gather and sort processor information std::vector ProcessorList = Records.getAllDerivedDefinitions("Processor"); @@ -130,261 +200,408 @@ void SubtargetEmitter::CPUKeyValues(std::ostream &OS) { // Begin processor table OS << "// Sorted (by key) array of values for CPU subtype.\n" - << "static const llvm::SubtargetFeatureKV SubTypeKV[] = {\n"; - + << "extern const llvm::SubtargetFeatureKV " << Target + << "SubTypeKV[] = {\n"; + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor Record *Processor = ProcessorList[i]; - std::string Name = Processor->getValueAsString("Name"); - std::vector FeatureList = + const std::string &Name = Processor->getValueAsString("Name"); + const std::vector &FeatureList = Processor->getValueAsListOfDefs("Features"); - + // Emit as { "cpu", "description", f1 | f2 | ... fn }, OS << " { " << "\"" << Name << "\", " << "\"Select the " << Name << " processor\", "; - + if (FeatureList.empty()) { - OS << "0"; + OS << "0ULL"; } else { for (unsigned j = 0, M = FeatureList.size(); j < M;) { - Record *Feature = FeatureList[j]; - std::string Name = Feature->getName(); - OS << Name; + OS << Target << "::" << FeatureList[j]->getName(); if (++j < M) OS << " | "; } } - - OS << " }"; - + + // The "0" is for the "implies" section of this data structure. + OS << ", 0ULL }"; + // Depending on 'if more in the list' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; - // Emit size of table - OS<<"\nenum {\n"; - OS<<" SubTypeKVSize = sizeof(SubTypeKV)/sizeof(llvm::SubtargetFeatureKV)\n"; - OS<<"};\n"; + return ProcessorList.size(); } // -// CollectAllItinClasses - Gathers and enumerates all the itinerary classes. -// Returns itinerary class count. -// -unsigned SubtargetEmitter::CollectAllItinClasses(std::ostream &OS, - std::map &ItinClassesMap) { - // Gather and sort all itinerary classes - std::vector ItinClassList = - Records.getAllDerivedDefinitions("InstrItinClass"); - std::sort(ItinClassList.begin(), ItinClassList.end(), LessRecord()); - - // For each itinerary class - unsigned N = ItinClassList.size(); - for (unsigned i = 0; i < N; i++) { - // Next itinerary class - Record *ItinClass = ItinClassList[i]; - // Get name of itinerary class - std::string Name = ItinClass->getName(); - // Assign itinerary class a unique number - ItinClassesMap[Name] = i; - } - - // Emit size of table - OS<<"\nenum {\n"; - OS<<" ItinClassesSize = " << N << "\n"; - OS<<"};\n"; - - // Return itinerary class count - return N; -} - +// FormItineraryStageString - Compose a string containing the stage +// data initialization for the specified itinerary. N is the number +// of stages. // -// FormItineraryString - Compose a string containing the data initialization -// for the specified itinerary. N is the number of stages. -// -void SubtargetEmitter::FormItineraryString(Record *ItinData, - std::string &ItinString, - unsigned &NStages) { +void SubtargetEmitter::FormItineraryStageString(const std::string &Name, + Record *ItinData, + std::string &ItinString, + unsigned &NStages) { // Get states list - std::vector StageList = ItinData->getValueAsListOfDefs("Stages"); + const std::vector &StageList = + ItinData->getValueAsListOfDefs("Stages"); // For each stage unsigned N = NStages = StageList.size(); - for (unsigned i = 0; i < N; i++) { + for (unsigned i = 0; i < N;) { // Next stage - Record *Stage = StageList[i]; - - // Form string as ,{ cycles, u1 | u2 | ... | un } + const Record *Stage = StageList[i]; + + // Form string as ,{ cycles, u1 | u2 | ... | un, timeinc, kind } int Cycles = Stage->getValueAsInt("Cycles"); ItinString += " { " + itostr(Cycles) + ", "; - + // Get unit list - std::vector UnitList = Stage->getValueAsListOfDefs("Units"); - + const std::vector &UnitList = Stage->getValueAsListOfDefs("Units"); + // For each unit for (unsigned j = 0, M = UnitList.size(); j < M;) { - // Next unit - Record *Unit = UnitList[j]; - // Add name and bitwise or - ItinString += Unit->getName(); + ItinString += Name + "FU::" + UnitList[j]->getName(); if (++j < M) ItinString += " | "; } - + + int TimeInc = Stage->getValueAsInt("TimeInc"); + ItinString += ", " + itostr(TimeInc); + + int Kind = Stage->getValueAsInt("Kind"); + ItinString += ", (llvm::InstrStage::ReservationKinds)" + itostr(Kind); + // Close off stage ItinString += " }"; + if (++i < N) ItinString += ", "; + } +} + +// +// FormItineraryOperandCycleString - Compose a string containing the +// operand cycle initialization for the specified itinerary. N is the +// number of operands that has cycles specified. +// +void SubtargetEmitter::FormItineraryOperandCycleString(Record *ItinData, + std::string &ItinString, unsigned &NOperandCycles) { + // Get operand cycle list + const std::vector &OperandCycleList = + ItinData->getValueAsListOfInts("OperandCycles"); + + // For each operand cycle + unsigned N = NOperandCycles = OperandCycleList.size(); + for (unsigned i = 0; i < N;) { + // Next operand cycle + const int OCycle = OperandCycleList[i]; + + ItinString += " " + itostr(OCycle); + if (++i < N) ItinString += ", "; + } +} + +void SubtargetEmitter::FormItineraryBypassString(const std::string &Name, + Record *ItinData, + std::string &ItinString, + unsigned NOperandCycles) { + const std::vector &BypassList = + ItinData->getValueAsListOfDefs("Bypasses"); + unsigned N = BypassList.size(); + unsigned i = 0; + for (; i < N;) { + ItinString += Name + "Bypass::" + BypassList[i]->getName(); + if (++i < NOperandCycles) ItinString += ", "; + } + for (; i < NOperandCycles;) { + ItinString += " 0"; + if (++i < NOperandCycles) ItinString += ", "; } } // -// EmitStageData - Generate unique itinerary stages. Record itineraries for -// processors. +// EmitStageAndOperandCycleData - Generate unique itinerary stages and operand +// cycle tables. Create a list of InstrItinerary objects (ProcItinLists) indexed +// by CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitStageData(std::ostream &OS, - unsigned NItinClasses, - std::map &ItinClassesMap, - std::vector > &ProcList) { - // Gather processor iteraries - std::vector ProcItinList = - Records.getAllDerivedDefinitions("ProcessorItineraries"); - - // If just no itinerary then don't bother - if (ProcItinList.size() < 2) return; +void SubtargetEmitter:: +EmitStageAndOperandCycleData(raw_ostream &OS, + std::vector > + &ProcItinLists) { + + // Multiple processor models may share an itinerary record. Emit it once. + SmallPtrSet ItinsDefSet; + + // Emit functional units for all the itineraries. + for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), + PE = SchedModels.procModelEnd(); PI != PE; ++PI) { + + if (!ItinsDefSet.insert(PI->ItinsDef)) + continue; + + std::vector FUs = PI->ItinsDef->getValueAsListOfDefs("FU"); + if (FUs.empty()) + continue; + + const std::string &Name = PI->ItinsDef->getName(); + OS << "\n// Functional units for \"" << Name << "\"\n" + << "namespace " << Name << "FU {\n"; + + for (unsigned j = 0, FUN = FUs.size(); j < FUN; ++j) + OS << " const unsigned " << FUs[j]->getName() + << " = 1 << " << j << ";\n"; + + OS << "}\n"; + + std::vector BPs = PI->ItinsDef->getValueAsListOfDefs("BP"); + if (BPs.size()) { + OS << "\n// Pipeline forwarding pathes for itineraries \"" << Name + << "\"\n" << "namespace " << Name << "Bypass {\n"; + + OS << " const unsigned NoBypass = 0;\n"; + for (unsigned j = 0, BPN = BPs.size(); j < BPN; ++j) + OS << " const unsigned " << BPs[j]->getName() + << " = 1 << " << j << ";\n"; + + OS << "}\n"; + } + } // Begin stages table - OS << "static llvm::InstrStage Stages[] = {\n" - " { 0, 0 }, // No itinerary\n"; - - unsigned ItinEnum = 1; - std::map ItinMap; - for (unsigned i = 0, N = ProcItinList.size(); i < N; i++) { - // Next record - Record *Proc = ProcItinList[i]; - - // Get processor itinerary name - std::string Name = Proc->getName(); - - // Skip default - if (Name == "NoItineraries") continue; - - // Create and expand processor itinerary to cover all itinerary classes - std::vector ItinList; - ItinList.resize(NItinClasses); - - // Get itinerary data list - std::vector ItinDataList = Proc->getValueAsListOfDefs("IID"); - + std::string StageTable = "\nextern const llvm::InstrStage " + Target + + "Stages[] = {\n"; + StageTable += " { 0, 0, 0, llvm::InstrStage::Required }, // No itinerary\n"; + + // Begin operand cycle table + std::string OperandCycleTable = "extern const unsigned " + Target + + "OperandCycles[] = {\n"; + OperandCycleTable += " 0, // No itinerary\n"; + + // Begin pipeline bypass table + std::string BypassTable = "extern const unsigned " + Target + + "ForwardingPaths[] = {\n"; + BypassTable += " 0, // No itinerary\n"; + + // For each Itinerary across all processors, add a unique entry to the stages, + // operand cycles, and pipepine bypess tables. Then add the new Itinerary + // object with computed offsets to the ProcItinLists result. + unsigned StageCount = 1, OperandCycleCount = 1; + std::map ItinStageMap, ItinOperandMap; + for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), + PE = SchedModels.procModelEnd(); PI != PE; ++PI) { + const CodeGenProcModel &ProcModel = *PI; + + // Add process itinerary to the list. + ProcItinLists.resize(ProcItinLists.size()+1); + + // If this processor defines no itineraries, then leave the itinerary list + // empty. + std::vector &ItinList = ProcItinLists.back(); + if (ProcModel.ItinDefList.empty()) + continue; + + // Reserve index==0 for NoItinerary. + ItinList.resize(SchedModels.numItineraryClasses()+1); + + const std::string &Name = ProcModel.ItinsDef->getName(); + // For each itinerary data - for (unsigned j = 0, M = ItinDataList.size(); j < M; j++) { + for (unsigned SchedClassIdx = 0, + SchedClassEnd = ProcModel.ItinDefList.size(); + SchedClassIdx < SchedClassEnd; ++SchedClassIdx) { + // Next itinerary data - Record *ItinData = ItinDataList[j]; - + Record *ItinData = ProcModel.ItinDefList[SchedClassIdx]; + // Get string and stage count - std::string ItinString; - unsigned NStages; - FormItineraryString(ItinData, ItinString, NStages); - - // Check to see if it already exists - unsigned Find = ItinMap[ItinString]; - - // If new itinerary - if (Find == 0) { - // Emit as { cycles, u1 | u2 | ... | un }, // index - OS << ItinString << ", // " << ItinEnum << "\n"; - // Record Itin class number - ItinMap[ItinString] = Find = ItinEnum++; + std::string ItinStageString; + unsigned NStages = 0; + if (ItinData) + FormItineraryStageString(Name, ItinData, ItinStageString, NStages); + + // Get string and operand cycle count + std::string ItinOperandCycleString; + unsigned NOperandCycles = 0; + std::string ItinBypassString; + if (ItinData) { + FormItineraryOperandCycleString(ItinData, ItinOperandCycleString, + NOperandCycles); + + FormItineraryBypassString(Name, ItinData, ItinBypassString, + NOperandCycles); + } + + // Check to see if stage already exists and create if it doesn't + unsigned FindStage = 0; + if (NStages > 0) { + FindStage = ItinStageMap[ItinStageString]; + if (FindStage == 0) { + // Emit as { cycles, u1 | u2 | ... | un, timeinc }, // indices + StageTable += ItinStageString + ", // " + itostr(StageCount); + if (NStages > 1) + StageTable += "-" + itostr(StageCount + NStages - 1); + StageTable += "\n"; + // Record Itin class number. + ItinStageMap[ItinStageString] = FindStage = StageCount; + StageCount += NStages; + } } - + + // Check to see if operand cycle already exists and create if it doesn't + unsigned FindOperandCycle = 0; + if (NOperandCycles > 0) { + std::string ItinOperandString = ItinOperandCycleString+ItinBypassString; + FindOperandCycle = ItinOperandMap[ItinOperandString]; + if (FindOperandCycle == 0) { + // Emit as cycle, // index + OperandCycleTable += ItinOperandCycleString + ", // "; + std::string OperandIdxComment = itostr(OperandCycleCount); + if (NOperandCycles > 1) + OperandIdxComment += "-" + + itostr(OperandCycleCount + NOperandCycles - 1); + OperandCycleTable += OperandIdxComment + "\n"; + // Record Itin class number. + ItinOperandMap[ItinOperandCycleString] = + FindOperandCycle = OperandCycleCount; + // Emit as bypass, // index + BypassTable += ItinBypassString + ", // " + OperandIdxComment + "\n"; + OperandCycleCount += NOperandCycles; + } + } + // Set up itinerary as location and location + stage count - InstrItinerary Intinerary = { Find, Find + NStages }; + int NumUOps = ItinData ? ItinData->getValueAsInt("NumMicroOps") : 0; + InstrItinerary Intinerary = { NumUOps, FindStage, FindStage + NStages, + FindOperandCycle, + FindOperandCycle + NOperandCycles}; - // Locate where to inject into processor itinerary table - std::string Name = ItinData->getValueAsDef("TheClass")->getName(); - Find = ItinClassesMap[Name]; - // Inject - empty slots will be 0, 0 - ItinList[Find] = Intinerary; + ItinList[SchedClassIdx] = Intinerary; } - - // Add process itinerary to list - ProcList.push_back(ItinList); } - + // Closing stage - OS << " { 0, 0 } // End itinerary\n"; - // End stages table - OS << "};\n"; - - // Emit size of table - OS<<"\nenum {\n"; - OS<<" StagesSize = sizeof(Stages)/sizeof(llvm::InstrStage)\n"; - OS<<"};\n"; + StageTable += " { 0, 0, 0, llvm::InstrStage::Required } // End stages\n"; + StageTable += "};\n"; + + // Closing operand cycles + OperandCycleTable += " 0 // End operand cycles\n"; + OperandCycleTable += "};\n"; + + BypassTable += " 0 // End bypass tables\n"; + BypassTable += "};\n"; + + // Emit tables. + OS << StageTable; + OS << OperandCycleTable; + OS << BypassTable; } // -// EmitProcessorData - Generate data for processor itineraries. +// EmitProcessorData - Generate data for processor itineraries that were +// computed during EmitStageAndOperandCycleData(). ProcItinLists lists all +// Itineraries for each processor. The Itinerary lists are indexed on +// CodeGenSchedClass::Index. // -void SubtargetEmitter::EmitProcessorData(std::ostream &OS, - std::vector > &ProcList) { - // Get an iterator for processor itinerary stages +void SubtargetEmitter:: +EmitItineraries(raw_ostream &OS, + std::vector > &ProcItinLists) { + + // Multiple processor models may share an itinerary record. Emit it once. + SmallPtrSet ItinsDefSet; + + // For each processor's machine model std::vector >::iterator - ProcListIter = ProcList.begin(); - - // For each processor itinerary - std::vector Itins = - Records.getAllDerivedDefinitions("ProcessorItineraries"); - for (unsigned i = 0, N = Itins.size(); i < N; i++) { - // Next record - Record *Itin = Itins[i]; + ProcItinListsIter = ProcItinLists.begin(); + for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), + PE = SchedModels.procModelEnd(); PI != PE; ++PI) { + + Record *ItinsDef = PI->ItinsDef; + if (!ItinsDefSet.insert(ItinsDef)) + continue; // Get processor itinerary name - std::string Name = Itin->getName(); - - // Skip default - if (Name == "NoItineraries") continue; + const std::string &Name = ItinsDef->getName(); + + // Get the itinerary list for the processor. + assert(ProcItinListsIter != ProcItinLists.end() && "bad iterator"); + std::vector &ItinList = *ProcItinListsIter++; - // Begin processor itinerary table OS << "\n"; - OS << "static llvm::InstrItinerary " << Name << "[] = {\n"; - - // For each itinerary class - std::vector &ItinList = *ProcListIter++; - unsigned ItinIndex = 0; - for (unsigned j = 0, M = ItinList.size(); j < M;) { + OS << "static const llvm::InstrItinerary "; + if (ItinList.empty()) { + OS << '*' << Name << " = 0;\n"; + continue; + } + + // Begin processor itinerary table + OS << Name << "[] = {\n"; + + // For each itinerary class in CodeGenSchedClass::Index order. + for (unsigned j = 0, M = ItinList.size(); j < M; ++j) { InstrItinerary &Intinerary = ItinList[j]; - - // Emit in the form of { first, last } // index - if (Intinerary.First == 0) { - OS << " { 0, 0 }"; - } else { - OS << " { " << Intinerary.First << ", " << Intinerary.Last << " }"; - } - - // If more in list add comma - if (++j < M) OS << ","; - - OS << " // " << (j - 1) << "\n"; + + // Emit Itinerary in the form of + // { firstStage, lastStage, firstCycle, lastCycle } // index + OS << " { " << + Intinerary.NumMicroOps << ", " << + Intinerary.FirstStage << ", " << + Intinerary.LastStage << ", " << + Intinerary.FirstOperandCycle << ", " << + Intinerary.LastOperandCycle << " }" << + ", // " << j << " " << SchedModels.getSchedClass(j).Name << "\n"; } - // End processor itinerary table + OS << " { 0, ~0U, ~0U, ~0U, ~0U } // end marker\n"; OS << "};\n"; } - +} + +// Emit either the value defined in the TableGen Record, or the default +// value defined in the C++ header. The Record is null if the processor does not +// define a model. +void SubtargetEmitter::EmitProcessorProp(raw_ostream &OS, const Record *R, + const char *Name, char Separator) { + OS << " "; + int V = R ? R->getValueAsInt(Name) : -1; + if (V >= 0) + OS << V << Separator << " // " << Name; + else + OS << "MCSchedModel::Default" << Name << Separator; + OS << '\n'; +} + +void SubtargetEmitter::EmitProcessorModels(raw_ostream &OS) { + // For each processor model. + for (CodeGenSchedModels::ProcIter PI = SchedModels.procModelBegin(), + PE = SchedModels.procModelEnd(); PI != PE; ++PI) { + // Skip default + // Begin processor itinerary properties OS << "\n"; - OS << "static llvm::InstrItinerary NoItineraries[] = {};\n"; + OS << "static const llvm::MCSchedModel " << PI->ModelName << "(\n"; + EmitProcessorProp(OS, PI->ModelDef, "IssueWidth", ','); + EmitProcessorProp(OS, PI->ModelDef, "MinLatency", ','); + EmitProcessorProp(OS, PI->ModelDef, "LoadLatency", ','); + EmitProcessorProp(OS, PI->ModelDef, "HighLatency", ','); + if (SchedModels.hasItineraryClasses()) + OS << " " << PI->ItinsDef->getName(); + else + OS << " 0"; + OS << ");\n"; + } } // // EmitProcessorLookup - generate cpu name to itinerary lookup table. // -void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) { +void SubtargetEmitter::EmitProcessorLookup(raw_ostream &OS) { // Gather and sort processor information std::vector ProcessorList = Records.getAllDerivedDefinitions("Processor"); @@ -393,125 +610,225 @@ void SubtargetEmitter::EmitProcessorLookup(std::ostream &OS) { // Begin processor table OS << "\n"; OS << "// Sorted (by key) array of itineraries for CPU subtype.\n" - << "static const llvm::SubtargetInfoKV ProcItinKV[] = {\n"; - + << "extern const llvm::SubtargetInfoKV " + << Target << "ProcSchedKV[] = {\n"; + // For each processor for (unsigned i = 0, N = ProcessorList.size(); i < N;) { // Next processor Record *Processor = ProcessorList[i]; - std::string Name = Processor->getValueAsString("Name"); - std::string ProcItin = Processor->getValueAsDef("ProcItin")->getName(); - + const std::string &Name = Processor->getValueAsString("Name"); + const std::string &ProcModelName = + SchedModels.getProcModel(Processor).ModelName; + // Emit as { "cpu", procinit }, OS << " { " << "\"" << Name << "\", " - << "(void *)&" << ProcItin; - + << "(void *)&" << ProcModelName; + OS << " }"; - + // Depending on ''if more in the list'' emit comma if (++i < N) OS << ","; - + OS << "\n"; } - + // End processor table OS << "};\n"; - - // Emit size of table - OS<<"\nenum {\n"; - OS<<" ProcItinKVSize = sizeof(ProcItinKV)/" - "sizeof(llvm::SubtargetInfoKV)\n"; - OS<<"};\n"; } // -// EmitData - Emits all stages and itineries, folding common patterns. +// EmitSchedModel - Emits all scheduling model tables, folding common patterns. // -void SubtargetEmitter::EmitData(std::ostream &OS) { - std::map ItinClassesMap; - std::vector > ProcList; - - // Enumerate all the itinerary classes - unsigned NItinClasses = CollectAllItinClasses(OS, ItinClassesMap); - // Make sure the rest is worth the effort - HasItineraries = NItinClasses != 1; // Ignore NoItinerary. - - if (HasItineraries) { +void SubtargetEmitter::EmitSchedModel(raw_ostream &OS) { + if (SchedModels.hasItineraryClasses()) { + std::vector > ProcItinLists; // Emit the stage data - EmitStageData(OS, NItinClasses, ItinClassesMap, ProcList); - // Emit the processor itinerary data - EmitProcessorData(OS, ProcList); - // Emit the processor lookup data - EmitProcessorLookup(OS); + EmitStageAndOperandCycleData(OS, ProcItinLists); + EmitItineraries(OS, ProcItinLists); } + // Emit the processor machine model + EmitProcessorModels(OS); + // Emit the processor lookup data + EmitProcessorLookup(OS); } // // ParseFeaturesFunction - Produces a subtarget specific function for parsing // the subtarget features string. // -void SubtargetEmitter::ParseFeaturesFunction(std::ostream &OS) { +void SubtargetEmitter::ParseFeaturesFunction(raw_ostream &OS, + unsigned NumFeatures, + unsigned NumProcs) { std::vector Features = Records.getAllDerivedDefinitions("SubtargetFeature"); std::sort(Features.begin(), Features.end(), LessRecord()); - OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" - "// subtarget options.\n" - "void llvm::"; + OS << "// ParseSubtargetFeatures - Parses features string setting specified\n" + << "// subtarget options.\n" + << "void llvm::"; OS << Target; - OS << "Subtarget::ParseSubtargetFeatures(const std::string &FS,\n" - " const std::string &CPU) {\n" - " SubtargetFeatures Features(FS);\n" - " Features.setCPUIfNone(CPU);\n" - " uint32_t Bits = Features.getBits(SubTypeKV, SubTypeKVSize,\n" - " FeatureKV, FeatureKVSize);\n"; - + OS << "Subtarget::ParseSubtargetFeatures(StringRef CPU, StringRef FS) {\n" + << " DEBUG(dbgs() << \"\\nFeatures:\" << FS);\n" + << " DEBUG(dbgs() << \"\\nCPU:\" << CPU << \"\\n\\n\");\n"; + + if (Features.empty()) { + OS << "}\n"; + return; + } + + OS << " uint64_t Bits = ReInitMCSubtargetInfo(CPU, FS);\n"; + for (unsigned i = 0; i < Features.size(); i++) { // Next record Record *R = Features[i]; - std::string Instance = R->getName(); - std::string Name = R->getValueAsString("Name"); - std::string Value = R->getValueAsString("Value"); - std::string Attribute = R->getValueAsString("Attribute"); - - OS << " if ((Bits & " << Instance << ") != 0) " - << Attribute << " = " << Value << ";\n"; - } - - if (HasItineraries) { - OS << "\n" - << " InstrItinerary *Itinerary = (InstrItinerary *)" - "Features.getInfo(ProcItinKV, ProcItinKVSize);\n" - " InstrItins = InstrItineraryData(Stages, Itinerary);\n"; + const std::string &Instance = R->getName(); + const std::string &Value = R->getValueAsString("Value"); + const std::string &Attribute = R->getValueAsString("Attribute"); + + if (Value=="true" || Value=="false") + OS << " if ((Bits & " << Target << "::" + << Instance << ") != 0) " + << Attribute << " = " << Value << ";\n"; + else + OS << " if ((Bits & " << Target << "::" + << Instance << ") != 0 && " + << Attribute << " < " << Value << ") " + << Attribute << " = " << Value << ";\n"; } - + OS << "}\n"; } -// +// // SubtargetEmitter::run - Main subtarget enumeration emitter. // -void SubtargetEmitter::run(std::ostream &OS) { - Target = CodeGenTarget().getName(); - - EmitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); - - OS << "#include \"llvm/Target/SubtargetFeature.h\"\n"; - OS << "#include \"llvm/Target/TargetInstrItineraries.h\"\n\n"; - - Enumeration(OS, "FuncUnit", true); - OS<<"\n"; -// Enumeration(OS, "InstrItinClass", false); -// OS<<"\n"; +void SubtargetEmitter::run(raw_ostream &OS) { + emitSourceFileHeader("Subtarget Enumeration Source Fragment", OS); + + OS << "\n#ifdef GET_SUBTARGETINFO_ENUM\n"; + OS << "#undef GET_SUBTARGETINFO_ENUM\n"; + + OS << "namespace llvm {\n"; Enumeration(OS, "SubtargetFeature", true); - OS<<"\n"; - FeatureKeyValues(OS); - OS<<"\n"; - CPUKeyValues(OS); - OS<<"\n"; - EmitData(OS); - OS<<"\n"; - ParseFeaturesFunction(OS); + OS << "} // End llvm namespace \n"; + OS << "#endif // GET_SUBTARGETINFO_ENUM\n\n"; + + OS << "\n#ifdef GET_SUBTARGETINFO_MC_DESC\n"; + OS << "#undef GET_SUBTARGETINFO_MC_DESC\n"; + + OS << "namespace llvm {\n"; +#if 0 + OS << "namespace {\n"; +#endif + unsigned NumFeatures = FeatureKeyValues(OS); + OS << "\n"; + unsigned NumProcs = CPUKeyValues(OS); + OS << "\n"; + EmitSchedModel(OS); + OS << "\n"; +#if 0 + OS << "}\n"; +#endif + + // MCInstrInfo initialization routine. + OS << "static inline void Init" << Target + << "MCSubtargetInfo(MCSubtargetInfo *II, " + << "StringRef TT, StringRef CPU, StringRef FS) {\n"; + OS << " II->InitMCSubtargetInfo(TT, CPU, FS, "; + if (NumFeatures) + OS << Target << "FeatureKV, "; + else + OS << "0, "; + if (NumProcs) + OS << Target << "SubTypeKV, "; + else + OS << "0, "; + if (SchedModels.hasItineraryClasses()) { + OS << Target << "ProcSchedKV, " + << Target << "Stages, " + << Target << "OperandCycles, " + << Target << "ForwardingPaths, "; + } else + OS << "0, 0, 0, 0, "; + OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; + + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_SUBTARGETINFO_MC_DESC\n\n"; + + OS << "\n#ifdef GET_SUBTARGETINFO_TARGET_DESC\n"; + OS << "#undef GET_SUBTARGETINFO_TARGET_DESC\n"; + + OS << "#include \"llvm/Support/Debug.h\"\n"; + OS << "#include \"llvm/Support/raw_ostream.h\"\n"; + ParseFeaturesFunction(OS, NumFeatures, NumProcs); + + OS << "#endif // GET_SUBTARGETINFO_TARGET_DESC\n\n"; + + // Create a TargetSubtargetInfo subclass to hide the MC layer initialization. + OS << "\n#ifdef GET_SUBTARGETINFO_HEADER\n"; + OS << "#undef GET_SUBTARGETINFO_HEADER\n"; + + std::string ClassName = Target + "GenSubtargetInfo"; + OS << "namespace llvm {\n"; + OS << "class DFAPacketizer;\n"; + OS << "struct " << ClassName << " : public TargetSubtargetInfo {\n" + << " explicit " << ClassName << "(StringRef TT, StringRef CPU, " + << "StringRef FS);\n" + << "public:\n" + << " DFAPacketizer *createDFAPacketizer(const InstrItineraryData *IID)" + << " const;\n" + << "};\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_SUBTARGETINFO_HEADER\n\n"; + + OS << "\n#ifdef GET_SUBTARGETINFO_CTOR\n"; + OS << "#undef GET_SUBTARGETINFO_CTOR\n"; + + OS << "namespace llvm {\n"; + OS << "extern const llvm::SubtargetFeatureKV " << Target << "FeatureKV[];\n"; + OS << "extern const llvm::SubtargetFeatureKV " << Target << "SubTypeKV[];\n"; + if (SchedModels.hasItineraryClasses()) { + OS << "extern const llvm::SubtargetInfoKV " << Target << "ProcSchedKV[];\n"; + OS << "extern const llvm::InstrStage " << Target << "Stages[];\n"; + OS << "extern const unsigned " << Target << "OperandCycles[];\n"; + OS << "extern const unsigned " << Target << "ForwardingPaths[];\n"; + } + + OS << ClassName << "::" << ClassName << "(StringRef TT, StringRef CPU, " + << "StringRef FS)\n" + << " : TargetSubtargetInfo() {\n" + << " InitMCSubtargetInfo(TT, CPU, FS, "; + if (NumFeatures) + OS << Target << "FeatureKV, "; + else + OS << "0, "; + if (NumProcs) + OS << Target << "SubTypeKV, "; + else + OS << "0, "; + if (SchedModels.hasItineraryClasses()) { + OS << Target << "ProcSchedKV, " + << Target << "Stages, " + << Target << "OperandCycles, " + << Target << "ForwardingPaths, "; + } else + OS << "0, 0, 0, 0, "; + OS << NumFeatures << ", " << NumProcs << ");\n}\n\n"; + OS << "} // End llvm namespace \n"; + + OS << "#endif // GET_SUBTARGETINFO_CTOR\n\n"; } + +namespace llvm { + +void EmitSubtarget(RecordKeeper &RK, raw_ostream &OS) { + CodeGenTarget CGTarget(RK); + SubtargetEmitter(RK, CGTarget).run(OS); +} + +} // End llvm namespace