X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FTableGen.cpp;h=d6e84609f430aa961d5fd1d35260b3f6a4ce4acc;hb=11a353a20614010029ee11bd30be4414ec36e315;hp=f4ece12897ead0007cb19a3450c81c77435e94f8;hpb=f460165a4c1bf4bc762f9b3f12b9ed284b89cc99;p=oota-llvm.git

diff --git a/utils/TableGen/TableGen.cpp b/utils/TableGen/TableGen.cpp
index f4ece12897e..d6e84609f43 100644
--- a/utils/TableGen/TableGen.cpp
+++ b/utils/TableGen/TableGen.cpp
@@ -2,8 +2,8 @@
 //
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
 //
 //===----------------------------------------------------------------------===//
 //
@@ -26,10 +26,13 @@
 #include "CodeEmitterGen.h"
 #include "RegisterInfoEmitter.h"
 #include "InstrInfoEmitter.h"
+#include "InstrEnumEmitter.h"
 #include "AsmWriterEmitter.h"
 #include "DAGISelEmitter.h"
+#include "FastISelEmitter.h"
 #include "SubtargetEmitter.h"
 #include "IntrinsicEmitter.h"
+#include "LLVMCConfigurationEmitter.h"
 #include <algorithm>
 #include <cstdio>
 #include <fstream>
@@ -40,11 +43,13 @@ enum ActionType {
   PrintRecords,
   GenEmitter,
   GenRegisterEnums, GenRegister, GenRegisterHeader,
-  GenInstrEnums, GenInstrs, GenAsmWriter, 
+  GenInstrEnums, GenInstrs, GenAsmWriter,
   GenCallingConv,
   GenDAGISel,
+  GenFastISel,
   GenSubtarget,
   GenIntrinsic,
+  GenLLVMCConf,
   PrintEnums
 };
 
@@ -71,10 +76,14 @@ namespace {
                                "Generate assembly writer"),
                     clEnumValN(GenDAGISel, "gen-dag-isel",
                                "Generate a DAG instruction selector"),
+                    clEnumValN(GenFastISel, "gen-fast-isel",
+                               "Generate a \"fast\" instruction selector"),
                     clEnumValN(GenSubtarget, "gen-subtarget",
                                "Generate subtarget enumerations"),
                     clEnumValN(GenIntrinsic, "gen-intrinsic",
                                "Generate intrinsic information"),
+                    clEnumValN(GenLLVMCConf, "gen-llvmc",
+                               "Generate LLVMC configuration library"),
                     clEnumValN(PrintEnums, "print-enums",
                                "Print enum values for a class"),
                     clEnumValEnd));
@@ -99,22 +108,21 @@ RecordKeeper llvm::Records;
 
 /// ParseFile - this function begins the parsing of the specified tablegen
 /// file.
-static bool ParseFile(const std::string &Filename, 
+static bool ParseFile(const std::string &Filename,
                       const std::vector<std::string> &IncludeDirs) {
   std::string ErrorStr;
-  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(&Filename[0], Filename.size(),
-                                                 &ErrorStr);
+  MemoryBuffer *F = MemoryBuffer::getFileOrSTDIN(Filename.c_str(), &ErrorStr);
   if (F == 0) {
     cerr << "Could not open input file '" + Filename + "': " << ErrorStr <<"\n";
     return true;
   }
-  
+
   TGParser Parser(F);
-  
+
   // Record the location of the include directory so that the lexer can find
   // it later.
   Parser.setIncludeDirs(IncludeDirs);
-  
+
   return Parser.ParseFile();
 }
 
@@ -158,7 +166,7 @@ int main(int argc, char **argv) {
       break;
 
     case GenInstrEnums:
-      InstrInfoEmitter(Records).runEnums(*Out);
+      InstrEnumEmitter(Records).run(*Out);
       break;
     case GenInstrs:
       InstrInfoEmitter(Records).run(*Out);
@@ -173,12 +181,18 @@ int main(int argc, char **argv) {
     case GenDAGISel:
       DAGISelEmitter(Records).run(*Out);
       break;
+    case GenFastISel:
+      FastISelEmitter(Records).run(*Out);
+      break;
     case GenSubtarget:
       SubtargetEmitter(Records).run(*Out);
       break;
     case GenIntrinsic:
       IntrinsicEmitter(Records).run(*Out);
       break;
+    case GenLLVMCConf:
+      LLVMCConfigurationEmitter(Records).run(*Out);
+      break;
     case PrintEnums:
     {
       std::vector<Record*> Recs = Records.getAllDerivedDefinitions(Class);