X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FX86RecognizableInstr.cpp;h=17fd0ec5c6efa617c6a941011eccef86e3e5c8cc;hb=8e31bc35ecd78d23fc5999f4dd24d8152a97f0fa;hp=8de948a64275baa9bdbfdfd1c721277dccf39fab;hpb=5747f946ec810d22d36260a4b18114d5673fd55f;p=oota-llvm.git diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 8de948a6427..17fd0ec5c6e 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -80,7 +80,7 @@ namespace X86Local { XD = 11, XS = 12, T8 = 13, P_TA = 14, A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19, - XOP8 = 20, XOP9 = 21, XOPA = 22 + XOP8 = 20, XOP9 = 21, XOPA = 22, PD = 23, T8PD = 24, TAPD = 25 }; } @@ -230,7 +230,6 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Prefix = byteFromRec(Rec, "Prefix"); Opcode = byteFromRec(Rec, "Opcode"); Form = byteFromRec(Rec, "FormBits"); - SegOvr = byteFromRec(Rec, "SegOvrBits"); HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); @@ -244,18 +243,21 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, HasEVEXPrefix = Rec->getValueAsBit("hasEVEXPrefix"); HasEVEX_L2Prefix = Rec->getValueAsBit("hasEVEX_L2"); HasEVEX_K = Rec->getValueAsBit("hasEVEX_K"); + HasEVEX_KZ = Rec->getValueAsBit("hasEVEX_Z"); HasEVEX_B = Rec->getValueAsBit("hasEVEX_B"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); + ForceDisassemble = Rec->getValueAsBit("ForceDisassemble"); Name = Rec->getName(); AsmString = Rec->getValueAsString("AsmString"); Operands = &insn.Operands.OperandList; - IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || + IsSSE = ((HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) && + (Name.find("16") == Name.npos)) || (Name.find("CRC32") != Name.npos); - HasFROperands = hasFROperands(); HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); // Check for 64-bit inst which does not require REX @@ -264,26 +266,16 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, // FIXME: Is there some better way to check for In64BitMode? std::vector Predicates = Rec->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { - if (Predicates[i]->getName().find("32Bit") != Name.npos) { + if (Predicates[i]->getName().find("Not64Bit") != Name.npos || + Predicates[i]->getName().find("In32Bit") != Name.npos) { Is32Bit = true; break; } - if (Predicates[i]->getName().find("64Bit") != Name.npos) { + if (Predicates[i]->getName().find("In64Bit") != Name.npos) { Is64Bit = true; break; } } - // FIXME: These instructions aren't marked as 64-bit in any way - Is64Bit |= Rec->getName() == "JMP64pcrel32" || - Rec->getName() == "MASKMOVDQU64" || - Rec->getName() == "POPFS64" || - Rec->getName() == "POPGS64" || - Rec->getName() == "PUSHFS64" || - Rec->getName() == "PUSHGS64" || - Rec->getName() == "REX64_PREFIX" || - Rec->getName().find("MOV64") != Name.npos || - Rec->getName().find("PUSH64") != Name.npos || - Rec->getName().find("POP64") != Name.npos; ShouldBeEmitted = true; } @@ -298,14 +290,16 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, RecognizableInstr recogInstr(tables, insn, uid); - recogInstr.emitInstructionSpecifier(tables); + recogInstr.emitInstructionSpecifier(); if (recogInstr.shouldBeEmitted()) recogInstr.emitDecodePath(tables); } -#define EVEX_KB(n) (HasEVEX_K && HasEVEX_B? n##_K_B : \ - (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))) +#define EVEX_KB(n) (HasEVEX_KZ && HasEVEX_B ? n##_KZ_B : \ + (HasEVEX_K && HasEVEX_B ? n##_K_B : \ + (HasEVEX_KZ ? n##_KZ : \ + (HasEVEX_K? n##_K : (HasEVEX_B ? n##_B : n))))) InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; @@ -317,7 +311,7 @@ InstructionContext RecognizableInstr::insnContext() const { } // VEX_L & VEX_W if (HasVEX_LPrefix && HasVEX_WPrefix) { - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD) insnContext = EVEX_KB(IC_EVEX_L_W_OPSIZE); else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = EVEX_KB(IC_EVEX_L_W_XS); @@ -328,7 +322,8 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = EVEX_KB(IC_EVEX_L_W); } else if (HasVEX_LPrefix) { // VEX_L - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = EVEX_KB(IC_EVEX_L_OPSIZE); else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = EVEX_KB(IC_EVEX_L_XS); @@ -340,7 +335,8 @@ InstructionContext RecognizableInstr::insnContext() const { } else if (HasEVEX_L2Prefix && HasVEX_WPrefix) { // EVEX_L2 & VEX_W - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = EVEX_KB(IC_EVEX_L2_W_OPSIZE); else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = EVEX_KB(IC_EVEX_L2_W_XS); @@ -351,10 +347,11 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = EVEX_KB(IC_EVEX_L2_W); } else if (HasEVEX_L2Prefix) { // EVEX_L2 - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = EVEX_KB(IC_EVEX_L2_OPSIZE); else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || - Prefix == X86Local::TAXD) + Prefix == X86Local::TAXD) insnContext = EVEX_KB(IC_EVEX_L2_XD); else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = EVEX_KB(IC_EVEX_L2_XS); @@ -363,7 +360,8 @@ InstructionContext RecognizableInstr::insnContext() const { } else if (HasVEX_WPrefix) { // VEX_W - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = EVEX_KB(IC_EVEX_W_OPSIZE); else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = EVEX_KB(IC_EVEX_W_XS); @@ -374,7 +372,8 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = EVEX_KB(IC_EVEX_W); } // No L, no W - else if (HasOpSizePrefix) + else if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = EVEX_KB(IC_EVEX_OPSIZE); else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || Prefix == X86Local::TAXD) @@ -386,7 +385,8 @@ InstructionContext RecognizableInstr::insnContext() const { /// eof EVEX } else if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { if (HasVEX_LPrefix && HasVEX_WPrefix) { - if (HasOpSizePrefix) + if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = IC_VEX_L_W_OPSIZE; else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = IC_VEX_L_W_XS; @@ -395,11 +395,16 @@ InstructionContext RecognizableInstr::insnContext() const { insnContext = IC_VEX_L_W_XD; else insnContext = IC_VEX_L_W; - } else if (HasOpSizePrefix && HasVEX_LPrefix) + } else if ((HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) && + HasVEX_LPrefix) insnContext = IC_VEX_L_OPSIZE; - else if (HasOpSizePrefix && HasVEX_WPrefix) + else if ((HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) && + HasVEX_WPrefix) insnContext = IC_VEX_W_OPSIZE; - else if (HasOpSizePrefix) + else if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = IC_VEX_OPSIZE; else if (HasVEX_LPrefix && (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) @@ -427,7 +432,8 @@ InstructionContext RecognizableInstr::insnContext() const { else insnContext = IC_VEX; } else if (Is64Bit || HasREX_WPrefix) { - if (HasREX_WPrefix && HasOpSizePrefix) + if (HasREX_WPrefix && (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD)) insnContext = IC_64BIT_REXW_OPSIZE; else if (HasOpSizePrefix && (Prefix == X86Local::XD || Prefix == X86Local::T8XD || @@ -436,7 +442,8 @@ InstructionContext RecognizableInstr::insnContext() const { else if (HasOpSizePrefix && (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) insnContext = IC_64BIT_XS_OPSIZE; - else if (HasOpSizePrefix) + else if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = IC_64BIT_OPSIZE; else if (HasAdSizePrefix) insnContext = IC_64BIT_ADSIZE; @@ -464,7 +471,10 @@ InstructionContext RecognizableInstr::insnContext() const { else if (HasOpSizePrefix && (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) insnContext = IC_XS_OPSIZE; - else if (HasOpSizePrefix) + else if (HasOpSizePrefix && HasAdSizePrefix) + insnContext = IC_OPSIZE_ADSIZE; + else if (HasOpSizePrefix || Prefix == X86Local::PD || + Prefix == X86Local::T8PD || Prefix == X86Local::TAPD) insnContext = IC_OPSIZE; else if (HasAdSizePrefix) insnContext = IC_ADSIZE; @@ -490,25 +500,13 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions"); - if (Form == X86Local::Pseudo || - (IsCodeGenOnly && Name.find("_REV") == Name.npos && - Name.find("INC32") == Name.npos && Name.find("DEC32") == Name.npos)) + if (Form == X86Local::Pseudo || (IsCodeGenOnly && !ForceDisassemble)) return FILTER_STRONG; // Filter out artificial instructions but leave in the LOCK_PREFIX so it is // printed as a separate "instruction". - if (Name.find("_Int") != Name.npos || - Name.find("Int_") != Name.npos) - return FILTER_STRONG; - - // Filter out instructions with segment override prefixes. - // They're too messy to handle now and we'll special case them if needed. - - if (SegOvr) - return FILTER_STRONG; - ///////////////// // FILTER_WEAK @@ -520,26 +518,9 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { if (HasLockPrefix) return FILTER_WEAK; - // Filter out alternate forms of AVX instructions - if (Name.find("_alt") != Name.npos || - (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || - Name.find("_64mr") != Name.npos || - Name.find("rr64") != Name.npos) - return FILTER_WEAK; - // Special cases. - if (Name.find("MOV") != Name.npos && Name.find("r0") != Name.npos) - return FILTER_WEAK; - if (Name.find("MOVZ") != Name.npos && Name.find("MOVZX") == Name.npos && - Name != "MOVZPQILo2PQIrr") - return FILTER_WEAK; - if (Name.find("Fs") != Name.npos) - return FILTER_WEAK; - if (Name == "PUSH64i16" || - Name == "MOVPQI2QImr" || - Name == "VMOVPQI2QImr" || - Name == "VMASKMOVDQU64") + if (Name == "VMASKMOVDQU64") return FILTER_WEAK; // XACQUIRE and XRELEASE reuse REPNE and REP respectively. @@ -548,27 +529,9 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { Name == "XRELEASE_PREFIX") return FILTER_WEAK; - if (HasFROperands && Name.find("MOV") != Name.npos && - ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || - (Name.find("to") != Name.npos))) - return FILTER_STRONG; - return FILTER_NORMAL; } -bool RecognizableInstr::hasFROperands() const { - const std::vector &OperandList = *Operands; - unsigned numOperands = OperandList.size(); - - for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { - const std::string &recName = OperandList[operandIndex].Rec->getName(); - - if (recName.find("FR") != recName.npos) - return true; - } - return false; -} - void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, unsigned &physicalOperandIndex, unsigned &numPhysicalOperands, @@ -603,7 +566,7 @@ void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, ++physicalOperandIndex; } -void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { +void RecognizableInstr::emitInstructionSpecifier() { Spec->name = Name; if (!ShouldBeEmitted) @@ -904,7 +867,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { switch (Prefix) { default: llvm_unreachable("Invalid prefix!"); - // Extended two-byte opcodes can start with f2 0f, f3 0f, or 0f + // Extended two-byte opcodes can start with 66 0f, f2 0f, f3 0f, or 0f + case X86Local::PD: case X86Local::XD: case X86Local::XS: case X86Local::TB: @@ -950,6 +914,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = Opcode; break; case X86Local::T8: + case X86Local::T8PD: case X86Local::T8XD: case X86Local::T8XS: opcodeType = THREEBYTE_38; @@ -993,6 +958,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = Opcode; break; case X86Local::P_TA: + case X86Local::TAPD: case X86Local::TAXD: opcodeType = THREEBYTE_3A; if (needsModRMForDecode(Form)) @@ -1083,14 +1049,9 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { case X86Local::DE: case X86Local::DF: assert(Opcode >= 0xc0 && "Unexpected opcode for an escape opcode"); + assert(Form == X86Local::RawFrm); opcodeType = ONEBYTE; - if (Form == X86Local::AddRegFrm) { - Spec->modifierType = MODIFIER_MODRM; - Spec->modifierBase = Opcode; - filter = new AddRegEscapeFilter(Opcode); - } else { - filter = new EscapeFilter(true, Opcode); - } + filter = new ExactFilter(Opcode); opcodeToSet = 0xd8 + (Prefix - X86Local::D8); break; case X86Local::REP: @@ -1135,7 +1096,30 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { case 0xdd: case 0xde: case 0xdf: - filter = new EscapeFilter(false, Form - X86Local::MRM0m); + switch (Form) { + default: + llvm_unreachable("Unhandled escape opcode form"); + case X86Local::MRM0r: + case X86Local::MRM1r: + case X86Local::MRM2r: + case X86Local::MRM3r: + case X86Local::MRM4r: + case X86Local::MRM5r: + case X86Local::MRM6r: + case X86Local::MRM7r: + filter = new ExtendedFilter(true, Form - X86Local::MRM0r); + break; + case X86Local::MRM0m: + case X86Local::MRM1m: + case X86Local::MRM2m: + case X86Local::MRM3m: + case X86Local::MRM4m: + case X86Local::MRM5m: + case X86Local::MRM6m: + case X86Local::MRM7m: + filter = new ExtendedFilter(false, Form - X86Local::MRM0m); + break; + } // switch (Form) break; default: if (needsModRMForDecode(Form)) @@ -1152,40 +1136,25 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { assert(filter && "Filter not set"); if (Form == X86Local::AddRegFrm) { - if(Spec->modifierType != MODIFIER_MODRM) { - assert(opcodeToSet < 0xf9 && - "Not enough room for all ADDREG_FRM operands"); - - uint8_t currentOpcode; - - for (currentOpcode = opcodeToSet; - currentOpcode < opcodeToSet + 8; - ++currentOpcode) - tables.setTableFields(opcodeType, - insnContext(), - currentOpcode, - *filter, - UID, Is32Bit, IgnoresVEX_L); - - Spec->modifierType = MODIFIER_OPCODE; - Spec->modifierBase = opcodeToSet; - } else { - // modifierBase was set where MODIFIER_MODRM was set + assert(((opcodeToSet & 7) == 0) && + "ADDREG_FRM opcode not aligned"); + + uint8_t currentOpcode; + + for (currentOpcode = opcodeToSet; + currentOpcode < opcodeToSet + 8; + ++currentOpcode) tables.setTableFields(opcodeType, insnContext(), - opcodeToSet, + currentOpcode, *filter, UID, Is32Bit, IgnoresVEX_L); - } } else { tables.setTableFields(opcodeType, insnContext(), opcodeToSet, *filter, UID, Is32Bit, IgnoresVEX_L); - - Spec->modifierType = MODIFIER_NONE; - Spec->modifierBase = opcodeToSet; } delete filter; @@ -1225,6 +1194,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("i32i8imm", TYPE_IMM32) TYPE("u32u8imm", TYPE_IMM32) TYPE("GR32", TYPE_Rv) + TYPE("GR32orGR64", TYPE_R32) TYPE("i64mem", TYPE_Mv) TYPE("i64i32imm", TYPE_IMM64) TYPE("i64i8imm", TYPE_IMM64) @@ -1254,6 +1224,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("i32imm_pcrel", TYPE_REL32) TYPE("SSECC", TYPE_IMM3) TYPE("AVXCC", TYPE_IMM5) + TYPE("AVX512RC", TYPE_IMM32) TYPE("brtarget", TYPE_RELv) TYPE("uncondbrtarget", TYPE_RELv) TYPE("brtarget8", TYPE_REL8) @@ -1277,6 +1248,8 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("VR256", TYPE_XMM256) TYPE("VR256X", TYPE_XMM256) TYPE("VR512", TYPE_XMM512) + TYPE("VK1", TYPE_VK1) + TYPE("VK1WM", TYPE_VK1) TYPE("VK8", TYPE_VK8) TYPE("VK8WM", TYPE_VK8) TYPE("VK16", TYPE_VK16) @@ -1309,6 +1282,7 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString ENCODING("u32u8imm", ENCODING_IB) ENCODING("SSECC", ENCODING_IB) ENCODING("AVXCC", ENCODING_IB) + ENCODING("AVX512RC", ENCODING_IB) ENCODING("i16imm", ENCODING_Iv) ENCODING("i16i8imm", ENCODING_IB) ENCODING("i32imm", ENCODING_Iv) @@ -1333,8 +1307,10 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString OperandEncoding RecognizableInstr::rmRegisterEncodingFromString (const std::string &s, bool hasOpSizePrefix) { + ENCODING("RST", ENCODING_FP) ENCODING("GR16", ENCODING_RM) ENCODING("GR32", ENCODING_RM) + ENCODING("GR32orGR64", ENCODING_RM) ENCODING("GR64", ENCODING_RM) ENCODING("GR8", ENCODING_RM) ENCODING("VR128", ENCODING_RM) @@ -1347,6 +1323,7 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString ENCODING("VR256", ENCODING_RM) ENCODING("VR256X", ENCODING_RM) ENCODING("VR512", ENCODING_RM) + ENCODING("VK1", ENCODING_RM) ENCODING("VK8", ENCODING_RM) ENCODING("VK16", ENCODING_RM) errs() << "Unhandled R/M register encoding " << s << "\n"; @@ -1358,6 +1335,7 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString bool hasOpSizePrefix) { ENCODING("GR16", ENCODING_REG) ENCODING("GR32", ENCODING_REG) + ENCODING("GR32orGR64", ENCODING_REG) ENCODING("GR64", ENCODING_REG) ENCODING("GR8", ENCODING_REG) ENCODING("VR128", ENCODING_REG) @@ -1373,8 +1351,10 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("FR64X", ENCODING_REG) ENCODING("FR32X", ENCODING_REG) ENCODING("VR512", ENCODING_REG) + ENCODING("VK1", ENCODING_REG) ENCODING("VK8", ENCODING_REG) ENCODING("VK16", ENCODING_REG) + ENCODING("VK1WM", ENCODING_REG) ENCODING("VK8WM", ENCODING_REG) ENCODING("VK16WM", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; @@ -1395,6 +1375,7 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString ENCODING("VR128X", ENCODING_VVVV) ENCODING("VR256X", ENCODING_VVVV) ENCODING("VR512", ENCODING_VVVV) + ENCODING("VK1", ENCODING_VVVV) ENCODING("VK8", ENCODING_VVVV) ENCODING("VK16", ENCODING_VVVV) errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; @@ -1404,6 +1385,7 @@ OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString OperandEncoding RecognizableInstr::writemaskRegisterEncodingFromString (const std::string &s, bool hasOpSizePrefix) { + ENCODING("VK1WM", ENCODING_WRITEMASK) ENCODING("VK8WM", ENCODING_WRITEMASK) ENCODING("VK16WM", ENCODING_WRITEMASK) errs() << "Unhandled mask register encoding " << s << "\n"; @@ -1478,7 +1460,6 @@ OperandEncoding RecognizableInstr::relocationEncodingFromString OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString (const std::string &s, bool hasOpSizePrefix) { - ENCODING("RST", ENCODING_I) ENCODING("GR32", ENCODING_Rv) ENCODING("GR64", ENCODING_RO) ENCODING("GR16", ENCODING_Rv)