X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FX86RecognizableInstr.cpp;h=24155c0a5a66f9e460f527670513276541903df9;hb=fcb5e95c310f37f648c2150fabc861fb687e3732;hp=7f502cc561004969163122dfb312a01df8ea4655;hpb=b2ef4c1235c846c2503d0796541f4255ef1e13f5;p=oota-llvm.git diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 7f502cc5610..24155c0a5a6 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -34,7 +34,18 @@ using namespace llvm; MAP(E8, 39) \ MAP(F0, 40) \ MAP(F8, 41) \ - MAP(F9, 42) + MAP(F9, 42) \ + MAP(D0, 45) \ + MAP(D1, 46) \ + MAP(D4, 47) \ + MAP(D8, 48) \ + MAP(D9, 49) \ + MAP(DA, 50) \ + MAP(DB, 51) \ + MAP(DC, 52) \ + MAP(DD, 53) \ + MAP(DE, 54) \ + MAP(DF, 55) // A clone of X86 since we can't depend on something that is generated. namespace X86Local { @@ -46,18 +57,19 @@ namespace X86Local { MRMDestMem = 4, MRMSrcReg = 5, MRMSrcMem = 6, - MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, + MRM0r = 16, MRM1r = 17, MRM2r = 18, MRM3r = 19, MRM4r = 20, MRM5r = 21, MRM6r = 22, MRM7r = 23, MRM0m = 24, MRM1m = 25, MRM2m = 26, MRM3m = 27, MRM4m = 28, MRM5m = 29, MRM6m = 30, MRM7m = 31, MRMInitReg = 32, - + RawFrmImm8 = 43, + RawFrmImm16 = 44, #define MAP(from, to) MRM_##from = to, MRM_MAPPING #undef MAP lastMRM }; - + enum { TB = 1, REP = 2, @@ -65,22 +77,22 @@ namespace X86Local { DC = 7, DD = 8, DE = 9, DF = 10, XD = 11, XS = 12, T8 = 13, P_TA = 14, - P_0F_AE = 16, P_0F_01 = 17 + A6 = 15, A7 = 16, T8XD = 17, T8XS = 18, TAXD = 19 }; } // If rows are added to the opcode extension tables, then corresponding entries -// must be added here. +// must be added here. // // If the row corresponds to a single byte (i.e., 8f), then add an entry for // that byte to ONE_BYTE_EXTENSION_TABLES. // -// If the row corresponds to two bytes where the first is 0f, add an entry for +// If the row corresponds to two bytes where the first is 0f, add an entry for // the second byte to TWO_BYTE_EXTENSION_TABLES. // // If the row corresponds to some other set of bytes, you will need to modify // the code in RecognizableInstr::emitDecodePath() as well, and add new prefixes -// to the X86 TD files, except in two cases: if the first two bytes of such a +// to the X86 TD files, except in two cases: if the first two bytes of such a // new combination are 0f 38 or 0f 3a, you just have to add maps called // THREE_BYTE_38_EXTENSION_TABLES and THREE_BYTE_3A_EXTENSION_TABLES and add a // switch(Opcode) just below the case X86Local::T8: or case X86Local::TA: line @@ -104,7 +116,7 @@ namespace X86Local { EXTENSION_TABLE(f7) \ EXTENSION_TABLE(fe) \ EXTENSION_TABLE(ff) - + #define TWO_BYTE_EXTENSION_TABLES \ EXTENSION_TABLE(00) \ EXTENSION_TABLE(01) \ @@ -113,14 +125,16 @@ namespace X86Local { EXTENSION_TABLE(72) \ EXTENSION_TABLE(73) \ EXTENSION_TABLE(ae) \ - EXTENSION_TABLE(b9) \ EXTENSION_TABLE(ba) \ EXTENSION_TABLE(c7) +#define THREE_BYTE_38_EXTENSION_TABLES \ + EXTENSION_TABLE(F3) + using namespace X86Disassembler; /// needsModRMForDecode - Indicates whether a particular instruction requires a -/// ModR/M byte for the instruction to be properly decoded. For example, a +/// ModR/M byte for the instruction to be properly decoded. For example, a /// MRMDestReg instruction needs the Mod field in the ModR/M byte to be set to /// 0b11. /// @@ -199,46 +213,81 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Rec = insn.TheDef; Name = Rec->getName(); Spec = &tables.specForUID(UID); - + if (!Rec->isSubClassOf("X86Inst")) { ShouldBeEmitted = false; return; } - + Prefix = byteFromRec(Rec, "Prefix"); Opcode = byteFromRec(Rec, "Opcode"); Form = byteFromRec(Rec, "FormBits"); SegOvr = byteFromRec(Rec, "SegOvrBits"); - + HasOpSizePrefix = Rec->getValueAsBit("hasOpSizePrefix"); + HasAdSizePrefix = Rec->getValueAsBit("hasAdSizePrefix"); HasREX_WPrefix = Rec->getValueAsBit("hasREX_WPrefix"); + HasVEXPrefix = Rec->getValueAsBit("hasVEXPrefix"); HasVEX_4VPrefix = Rec->getValueAsBit("hasVEX_4VPrefix"); + HasVEX_4VOp3Prefix = Rec->getValueAsBit("hasVEX_4VOp3Prefix"); + HasVEX_WPrefix = Rec->getValueAsBit("hasVEX_WPrefix"); + HasMemOp4Prefix = Rec->getValueAsBit("hasMemOp4Prefix"); + IgnoresVEX_L = Rec->getValueAsBit("ignoresVEX_L"); HasLockPrefix = Rec->getValueAsBit("hasLockPrefix"); IsCodeGenOnly = Rec->getValueAsBit("isCodeGenOnly"); - + Name = Rec->getName(); AsmString = Rec->getValueAsString("AsmString"); - - Operands = &insn.OperandList; - - IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos); - HasFROperands = false; - + + Operands = &insn.Operands.OperandList; + + IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || + (Name.find("CRC32") != Name.npos); + HasFROperands = hasFROperands(); + HasVEX_LPrefix = Rec->getValueAsBit("hasVEX_L"); + + // Check for 64-bit inst which does not require REX + Is32Bit = false; + Is64Bit = false; + // FIXME: Is there some better way to check for In64BitMode? + std::vector Predicates = Rec->getValueAsListOfDefs("Predicates"); + for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { + if (Predicates[i]->getName().find("32Bit") != Name.npos) { + Is32Bit = true; + break; + } + if (Predicates[i]->getName().find("64Bit") != Name.npos) { + Is64Bit = true; + break; + } + } + // FIXME: These instructions aren't marked as 64-bit in any way + Is64Bit |= Rec->getName() == "JMP64pcrel32" || + Rec->getName() == "MASKMOVDQU64" || + Rec->getName() == "POPFS64" || + Rec->getName() == "POPGS64" || + Rec->getName() == "PUSHFS64" || + Rec->getName() == "PUSHGS64" || + Rec->getName() == "REX64_PREFIX" || + Rec->getName().find("MOV64") != Name.npos || + Rec->getName().find("PUSH64") != Name.npos || + Rec->getName().find("POP64") != Name.npos; + ShouldBeEmitted = true; } - + void RecognizableInstr::processInstr(DisassemblerTables &tables, - const CodeGenInstruction &insn, - InstrUID uid) + const CodeGenInstruction &insn, + InstrUID uid) { // Ignore "asm parser only" instructions. if (insn.TheDef->getValueAsBit("isAsmParserOnly")) return; - + RecognizableInstr recogInstr(tables, insn, uid); - + recogInstr.emitInstructionSpecifier(tables); - + if (recogInstr.shouldBeEmitted()) recogInstr.emitDecodePath(tables); } @@ -246,29 +295,90 @@ void RecognizableInstr::processInstr(DisassemblerTables &tables, InstructionContext RecognizableInstr::insnContext() const { InstructionContext insnContext; - if (Name.find("64") != Name.npos || HasREX_WPrefix) { + if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix|| HasVEXPrefix) { + if (HasVEX_LPrefix && HasVEX_WPrefix) { + if (HasOpSizePrefix) + insnContext = IC_VEX_L_W_OPSIZE; + else + llvm_unreachable("Don't support VEX.L and VEX.W together"); + } else if (HasOpSizePrefix && HasVEX_LPrefix) + insnContext = IC_VEX_L_OPSIZE; + else if (HasOpSizePrefix && HasVEX_WPrefix) + insnContext = IC_VEX_W_OPSIZE; + else if (HasOpSizePrefix) + insnContext = IC_VEX_OPSIZE; + else if (HasVEX_LPrefix && + (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) + insnContext = IC_VEX_L_XS; + else if (HasVEX_LPrefix && (Prefix == X86Local::XD || + Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD)) + insnContext = IC_VEX_L_XD; + else if (HasVEX_WPrefix && + (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) + insnContext = IC_VEX_W_XS; + else if (HasVEX_WPrefix && (Prefix == X86Local::XD || + Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD)) + insnContext = IC_VEX_W_XD; + else if (HasVEX_WPrefix) + insnContext = IC_VEX_W; + else if (HasVEX_LPrefix) + insnContext = IC_VEX_L; + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) + insnContext = IC_VEX_XD; + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) + insnContext = IC_VEX_XS; + else + insnContext = IC_VEX; + } else if (Is64Bit || HasREX_WPrefix) { if (HasREX_WPrefix && HasOpSizePrefix) insnContext = IC_64BIT_REXW_OPSIZE; + else if (HasOpSizePrefix && (Prefix == X86Local::XD || + Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD)) + insnContext = IC_64BIT_XD_OPSIZE; + else if (HasOpSizePrefix && + (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) + insnContext = IC_64BIT_XS_OPSIZE; else if (HasOpSizePrefix) insnContext = IC_64BIT_OPSIZE; - else if (HasREX_WPrefix && Prefix == X86Local::XS) + else if (HasAdSizePrefix) + insnContext = IC_64BIT_ADSIZE; + else if (HasREX_WPrefix && + (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) insnContext = IC_64BIT_REXW_XS; - else if (HasREX_WPrefix && Prefix == X86Local::XD) + else if (HasREX_WPrefix && (Prefix == X86Local::XD || + Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD)) insnContext = IC_64BIT_REXW_XD; - else if (Prefix == X86Local::XD) + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) insnContext = IC_64BIT_XD; - else if (Prefix == X86Local::XS) + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS) insnContext = IC_64BIT_XS; else if (HasREX_WPrefix) insnContext = IC_64BIT_REXW; else insnContext = IC_64BIT; } else { - if (HasOpSizePrefix) + if (HasOpSizePrefix && (Prefix == X86Local::XD || + Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD)) + insnContext = IC_XD_OPSIZE; + else if (HasOpSizePrefix && + (Prefix == X86Local::XS || Prefix == X86Local::T8XS)) + insnContext = IC_XS_OPSIZE; + else if (HasOpSizePrefix) insnContext = IC_OPSIZE; - else if (Prefix == X86Local::XD) + else if (HasAdSizePrefix) + insnContext = IC_ADSIZE; + else if (Prefix == X86Local::XD || Prefix == X86Local::T8XD || + Prefix == X86Local::TAXD) insnContext = IC_XD; - else if (Prefix == X86Local::XS) + else if (Prefix == X86Local::XS || Prefix == X86Local::T8XS || + Prefix == X86Local::REP) insnContext = IC_XS; else insnContext = IC; @@ -276,39 +386,53 @@ InstructionContext RecognizableInstr::insnContext() const { return insnContext; } - + RecognizableInstr::filter_ret RecognizableInstr::filter() const { + /////////////////// + // FILTER_STRONG + // + // Filter out intrinsics - - if (!Rec->isSubClassOf("X86Inst")) - return FILTER_STRONG; - + + assert(Rec->isSubClassOf("X86Inst") && "Can only filter X86 instructions"); + if (Form == X86Local::Pseudo || - IsCodeGenOnly) + (IsCodeGenOnly && Name.find("_REV") == Name.npos)) return FILTER_STRONG; - - if (Form == X86Local::MRMInitReg) + + + // Filter out artificial instructions but leave in the LOCK_PREFIX so it is + // printed as a separate "instruction". + + if (Name.find("_Int") != Name.npos || + Name.find("Int_") != Name.npos) return FILTER_STRONG; - + // Filter out instructions with segment override prefixes. + // They're too messy to handle now and we'll special case them if needed. + + if (SegOvr) + return FILTER_STRONG; + + + ///////////////// + // FILTER_WEAK + // + + // Filter out instructions with a LOCK prefix; // prefer forms that do not have the prefix if (HasLockPrefix) return FILTER_WEAK; - - // Filter out artificial instructions - - if (Name.find("TAILJMP") != Name.npos || - Name.find("_Int") != Name.npos || - Name.find("_int") != Name.npos || - Name.find("Int_") != Name.npos || - Name.find("_NOREX") != Name.npos || - Name.find("_TC") != Name.npos || - Name.find("EH_RETURN") != Name.npos || - Name.find("V_SET") != Name.npos || - Name.find("LOCK_") != Name.npos || - Name.find("WIN") != Name.npos) - return FILTER_STRONG; + + // Filter out alternate forms of AVX instructions + if (Name.find("_alt") != Name.npos || + Name.find("XrYr") != Name.npos || + (Name.find("r64r") != Name.npos && Name.find("r64r64") == Name.npos) || + Name.find("_64mr") != Name.npos || + Name.find("Xrr") != Name.npos || + Name.find("rr64") != Name.npos) + return FILTER_WEAK; // Special cases. @@ -323,100 +447,78 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { return FILTER_WEAK; if (Name.find("Fs") != Name.npos) return FILTER_WEAK; - if (Name == "MOVLPDrr" || - Name == "MOVLPSrr" || - Name == "PUSHFQ" || - Name == "BSF16rr" || - Name == "BSF16rm" || - Name == "BSR16rr" || - Name == "BSR16rm" || - Name == "MOVSX16rm8" || - Name == "MOVSX16rr8" || - Name == "MOVZX16rm8" || - Name == "MOVZX16rr8" || - Name == "PUSH32i16" || - Name == "PUSH64i16" || + if (Name == "PUSH64i16" || Name == "MOVPQI2QImr" || - Name == "MOVSDmr" || - Name == "MOVSDrm" || - Name == "MOVSSmr" || - Name == "MOVSSrm" || + Name == "VMOVPQI2QImr" || Name == "MMX_MOVD64rrv164" || - Name == "CRC32m16" || Name == "MOV64ri64i32" || - Name == "CRC32r16") + Name == "VMASKMOVDQU64" || + Name == "VEXTRACTPSrr64" || + Name == "VMOVQd64rr" || + Name == "VMOVQs64rr") return FILTER_WEAK; - // Filter out instructions with segment override prefixes. - // They're too messy to handle now and we'll special case them if needed. - - if (SegOvr) - return FILTER_STRONG; - - // Filter out instructions that can't be printed. - - if (AsmString.size() == 0) - return FILTER_STRONG; - - // Filter out instructions with subreg operands. - - if (AsmString.find("subreg") != AsmString.npos) - return FILTER_STRONG; - if (HasFROperands && Name.find("MOV") != Name.npos && - ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || + ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || (Name.find("to") != Name.npos))) - return FILTER_WEAK; + return FILTER_STRONG; - // Filter out the intrinsic form of instructions that also have an llvm - // operator form. FIXME this is temporary. - if (Name.find("irm") != Name.npos || - Name.find("irr") != Name.npos) - return FILTER_WEAK; - return FILTER_NORMAL; } - -void RecognizableInstr::handleOperand( - bool optional, - unsigned &operandIndex, - unsigned &physicalOperandIndex, - unsigned &numPhysicalOperands, - unsigned *operandMapping, - OperandEncoding (*encodingFromString)(const std::string&, bool hasOpSizePrefix)) { + +bool RecognizableInstr::hasFROperands() const { + const std::vector &OperandList = *Operands; + unsigned numOperands = OperandList.size(); + + for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { + const std::string &recName = OperandList[operandIndex].Rec->getName(); + + if (recName.find("FR") != recName.npos) + return true; + } + return false; +} + +void RecognizableInstr::handleOperand(bool optional, unsigned &operandIndex, + unsigned &physicalOperandIndex, + unsigned &numPhysicalOperands, + const unsigned *operandMapping, + OperandEncoding (*encodingFromString) + (const std::string&, + bool hasOpSizePrefix)) { if (optional) { if (physicalOperandIndex >= numPhysicalOperands) return; } else { assert(physicalOperandIndex < numPhysicalOperands); } - + while (operandMapping[operandIndex] != operandIndex) { Spec->operands[operandIndex].encoding = ENCODING_DUP; Spec->operands[operandIndex].type = (OperandType)(TYPE_DUP0 + operandMapping[operandIndex]); ++operandIndex; } - + const std::string &typeName = (*Operands)[operandIndex].Rec->getName(); - + Spec->operands[operandIndex].encoding = encodingFromString(typeName, HasOpSizePrefix); - Spec->operands[operandIndex].type = typeFromString(typeName, - IsSSE, - HasREX_WPrefix, - HasOpSizePrefix); - + Spec->operands[operandIndex].type = typeFromString(typeName, + IsSSE, + HasREX_WPrefix, + HasOpSizePrefix); + ++operandIndex; ++physicalOperandIndex; } void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { Spec->name = Name; - - if (!Rec->isSubClassOf("X86Inst")) + + if (!ShouldBeEmitted) return; - + switch (filter()) { case FILTER_WEAK: Spec->filtered = true; @@ -427,29 +529,26 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case FILTER_NORMAL: break; } - + Spec->insnContext = insnContext(); - - const std::vector &OperandList = *Operands; - - unsigned operandIndex; + + const std::vector &OperandList = *Operands; + unsigned numOperands = OperandList.size(); unsigned numPhysicalOperands = 0; - + // operandMapping maps from operands in OperandList to their originals. // If operandMapping[i] != i, then the entry is a duplicate. unsigned operandMapping[X86_MAX_OPERANDS]; - - bool hasFROperands = false; - - assert(numOperands < X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); - - for (operandIndex = 0; operandIndex < numOperands; ++operandIndex) { + assert(numOperands <= X86_MAX_OPERANDS && "X86_MAX_OPERANDS is not large enough"); + + for (unsigned operandIndex = 0; operandIndex < numOperands; ++operandIndex) { if (OperandList[operandIndex].Constraints.size()) { - const CodeGenInstruction::ConstraintInfo &Constraint = + const CGIOperandList::ConstraintInfo &Constraint = OperandList[operandIndex].Constraints[0]; if (Constraint.isTied()) { - operandMapping[operandIndex] = Constraint.getTiedOperand(); + operandMapping[operandIndex] = operandIndex; + operandMapping[Constraint.getTiedOperand()] = operandIndex; } else { ++numPhysicalOperands; operandMapping[operandIndex] = operandIndex; @@ -458,20 +557,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { ++numPhysicalOperands; operandMapping[operandIndex] = operandIndex; } - - const std::string &recName = OperandList[operandIndex].Rec->getName(); - - if (recName.find("FR") != recName.npos) - hasFROperands = true; } - - if (hasFROperands && Name.find("MOV") != Name.npos && - ((Name.find("2") != Name.npos && Name.find("32") == Name.npos) || - (Name.find("to") != Name.npos))) - ShouldBeEmitted = false; - - if (!ShouldBeEmitted) - return; #define HANDLE_OPERAND(class) \ handleOperand(false, \ @@ -480,7 +566,7 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { numPhysicalOperands, \ operandMapping, \ class##EncodingFromString); - + #define HANDLE_OPTIONAL(class) \ handleOperand(true, \ operandIndex, \ @@ -488,17 +574,17 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { numPhysicalOperands, \ operandMapping, \ class##EncodingFromString); - + // operandIndex should always be < numOperands - operandIndex = 0; + unsigned operandIndex = 0; // physicalOperandIndex should always be < numPhysicalOperands unsigned physicalOperandIndex = 0; - + switch (Form) { case X86Local::RawFrm: // Operand 1 (optional) is an address or immediate. // Operand 2 (optional) is an immediate. - assert(numPhysicalOperands <= 2 && + assert(numPhysicalOperands <= 2 && "Unexpected number of operands for RawFrm"); HANDLE_OPTIONAL(relocation) HANDLE_OPTIONAL(immediate) @@ -514,54 +600,111 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRMDestReg: // Operand 1 is a register operand in the R/M field. // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestRegFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestRegFrm"); + HANDLE_OPERAND(rmRegister) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; case X86Local::MRMDestMem: // Operand 1 is a memory operand (possibly SIB-extended) // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestMemFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestMemFrm"); HANDLE_OPERAND(memory) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcReg: // Operand 1 is a register operand in the Reg/Opcode field. // Operand 2 is a register operand in the R/M field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMSrcRegFrm"); + // Operand 4 (optional) is an immediate. + + if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && + "Unexpected number of operands for MRMSrcRegFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMSrcRegFrm"); + HANDLE_OPERAND(roRegister) - HANDLE_OPERAND(rmRegister) if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field - HANDLE_OPTIONAL(rmRegister) - else + HANDLE_OPERAND(vvvvRegister) + + if (HasMemOp4Prefix) + HANDLE_OPERAND(immediate) + + HANDLE_OPERAND(rmRegister) + + if (HasVEX_4VOp3Prefix) + HANDLE_OPERAND(vvvvRegister) + + if (!HasMemOp4Prefix) HANDLE_OPTIONAL(immediate) + HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 + HANDLE_OPTIONAL(immediate) break; case X86Local::MRMSrcMem: // Operand 1 is a register operand in the Reg/Opcode field. // Operand 2 is a memory operand (possibly SIB-extended) + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMSrcMemFrm"); + + if (HasVEX_4VPrefix || HasVEX_4VOp3Prefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 5 && + "Unexpected number of operands for MRMSrcMemFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMSrcMemFrm"); + HANDLE_OPERAND(roRegister) if (HasVEX_4VPrefix) // FIXME: In AVX, the register below becomes the one encoded // in ModRMVEX and the one above the one in the VEX.VVVV field - HANDLE_OPTIONAL(rmRegister) + HANDLE_OPERAND(vvvvRegister) + + if (HasMemOp4Prefix) + HANDLE_OPERAND(immediate) HANDLE_OPERAND(memory) - HANDLE_OPTIONAL(immediate) + + if (HasVEX_4VOp3Prefix) + HANDLE_OPERAND(vvvvRegister) + + if (!HasMemOp4Prefix) + HANDLE_OPTIONAL(immediate) + HANDLE_OPTIONAL(immediate) // above might be a register in 7:4 break; case X86Local::MRM0r: case X86Local::MRM1r: @@ -573,10 +716,18 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM7r: // Operand 1 is a register operand in the R/M field. // Operand 2 (optional) is an immediate or relocation. - assert(numPhysicalOperands <= 2 && - "Unexpected number of operands for MRMnRFrm"); + // Operand 3 (optional) is an immediate. + if (HasVEX_4VPrefix) + assert(numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMnRFrm with VEX_4V"); + else + assert(numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMnRFrm"); + if (HasVEX_4VPrefix) + HANDLE_OPERAND(vvvvRegister) HANDLE_OPTIONAL(rmRegister) HANDLE_OPTIONAL(relocation) + HANDLE_OPTIONAL(immediate) break; case X86Local::MRM0m: case X86Local::MRM1m: @@ -588,16 +739,36 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRM7m: // Operand 1 is a memory operand (possibly SIB-extended) // Operand 2 (optional) is an immediate or relocation. - assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && - "Unexpected number of operands for MRMnMFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMnMFrm"); + else + assert(numPhysicalOperands >= 1 && numPhysicalOperands <= 2 && + "Unexpected number of operands for MRMnMFrm"); + if (HasVEX_4VPrefix) + HANDLE_OPERAND(vvvvRegister) HANDLE_OPERAND(memory) HANDLE_OPTIONAL(relocation) break; + case X86Local::RawFrmImm8: + // operand 1 is a 16-bit immediate + // operand 2 is an 8-bit immediate + assert(numPhysicalOperands == 2 && + "Unexpected number of operands for X86Local::RawFrmImm8"); + HANDLE_OPERAND(immediate) + HANDLE_OPERAND(immediate) + break; + case X86Local::RawFrmImm16: + // operand 1 is a 16-bit immediate + // operand 2 is a 16-bit immediate + HANDLE_OPERAND(immediate) + HANDLE_OPERAND(immediate) + break; case X86Local::MRMInitReg: // Ignored. break; } - + #undef HANDLE_OPERAND #undef HANDLE_OPTIONAL } @@ -611,8 +782,8 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { break; OpcodeType opcodeType = (OpcodeType)-1; - - ModRMFilter* filter = NULL; + + ModRMFilter* filter = NULL; uint8_t opcodeToSet = 0; switch (Prefix) { @@ -662,15 +833,67 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = Opcode; break; case X86Local::T8: + case X86Local::T8XD: + case X86Local::T8XS: opcodeType = THREEBYTE_38; + switch (Opcode) { + default: + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + break; +#define EXTENSION_TABLE(n) case 0x##n: + THREE_BYTE_38_EXTENSION_TABLES +#undef EXTENSION_TABLE + switch (Form) { + default: + llvm_unreachable("Unhandled two-byte extended opcode"); + case X86Local::MRM0r: + case X86Local::MRM1r: + case X86Local::MRM2r: + case X86Local::MRM3r: + case X86Local::MRM4r: + case X86Local::MRM5r: + case X86Local::MRM6r: + case X86Local::MRM7r: + filter = new ExtendedFilter(true, Form - X86Local::MRM0r); + break; + case X86Local::MRM0m: + case X86Local::MRM1m: + case X86Local::MRM2m: + case X86Local::MRM3m: + case X86Local::MRM4m: + case X86Local::MRM5m: + case X86Local::MRM6m: + case X86Local::MRM7m: + filter = new ExtendedFilter(false, Form - X86Local::MRM0m); + break; + MRM_MAPPING + } // switch (Form) + break; + } // switch (Opcode) + opcodeToSet = Opcode; + break; + case X86Local::P_TA: + case X86Local::TAXD: + opcodeType = THREEBYTE_3A; if (needsModRMForDecode(Form)) filter = new ModFilter(isRegFormat(Form)); else filter = new DumbFilter(); opcodeToSet = Opcode; break; - case X86Local::P_TA: - opcodeType = THREEBYTE_3A; + case X86Local::A6: + opcodeType = THREEBYTE_A6; + if (needsModRMForDecode(Form)) + filter = new ModFilter(isRegFormat(Form)); + else + filter = new DumbFilter(); + opcodeToSet = Opcode; + break; + case X86Local::A7: + opcodeType = THREEBYTE_A7; if (needsModRMForDecode(Form)) filter = new ModFilter(isRegFormat(Form)); else @@ -696,6 +919,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { } opcodeToSet = 0xd8 + (Prefix - X86Local::D8); break; + case X86Local::REP: default: opcodeType = ONEBYTE; switch (Opcode) { @@ -757,41 +981,41 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { if(Spec->modifierType != MODIFIER_MODRM) { assert(opcodeToSet < 0xf9 && "Not enough room for all ADDREG_FRM operands"); - + uint8_t currentOpcode; for (currentOpcode = opcodeToSet; currentOpcode < opcodeToSet + 8; ++currentOpcode) - tables.setTableFields(opcodeType, - insnContext(), - currentOpcode, - *filter, - UID); - + tables.setTableFields(opcodeType, + insnContext(), + currentOpcode, + *filter, + UID, Is32Bit, IgnoresVEX_L); + Spec->modifierType = MODIFIER_OPCODE; Spec->modifierBase = opcodeToSet; } else { // modifierBase was set where MODIFIER_MODRM was set - tables.setTableFields(opcodeType, - insnContext(), - opcodeToSet, - *filter, - UID); + tables.setTableFields(opcodeType, + insnContext(), + opcodeToSet, + *filter, + UID, Is32Bit, IgnoresVEX_L); } } else { tables.setTableFields(opcodeType, insnContext(), opcodeToSet, *filter, - UID); - + UID, Is32Bit, IgnoresVEX_L); + Spec->modifierType = MODIFIER_NONE; Spec->modifierBase = opcodeToSet; } - + delete filter; - + #undef MAP } @@ -801,7 +1025,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, bool hasREX_WPrefix, bool hasOpSizePrefix) { if (isSSE) { - // For SSE instructions, we ignore the OpSize prefix and force operand + // For SSE instructions, we ignore the OpSize prefix and force operand // sizes. TYPE("GR16", TYPE_R16) TYPE("GR32", TYPE_R32) @@ -825,6 +1049,7 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("i32mem", TYPE_Mv) TYPE("i32imm", TYPE_IMMv) TYPE("i32i8imm", TYPE_IMM32) + TYPE("u32u8imm", TYPE_IMM32) TYPE("GR32", TYPE_Rv) TYPE("i64mem", TYPE_Mv) TYPE("i64i32imm", TYPE_IMM64) @@ -844,11 +1069,14 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("ssmem", TYPE_M32FP) TYPE("RST", TYPE_ST) TYPE("i128mem", TYPE_M128) + TYPE("i256mem", TYPE_M256) TYPE("i64i32imm_pcrel", TYPE_REL64) TYPE("i16imm_pcrel", TYPE_REL16) TYPE("i32imm_pcrel", TYPE_REL32) TYPE("SSECC", TYPE_IMM3) + TYPE("AVXCC", TYPE_IMM5) TYPE("brtarget", TYPE_RELv) + TYPE("uncondbrtarget", TYPE_RELv) TYPE("brtarget8", TYPE_REL8) TYPE("f80mem", TYPE_M80FP) TYPE("lea32mem", TYPE_LEA) @@ -867,6 +1095,14 @@ OperandType RecognizableInstr::typeFromString(const std::string &s, TYPE("offset16", TYPE_MOFFS16) TYPE("offset32", TYPE_MOFFS32) TYPE("offset64", TYPE_MOFFS64) + TYPE("VR256", TYPE_XMM256) + TYPE("GR16_NOAX", TYPE_Rv) + TYPE("GR32_NOAX", TYPE_Rv) + TYPE("GR64_NOAX", TYPE_R64) + TYPE("vx32mem", TYPE_M32) + TYPE("vy32mem", TYPE_M32) + TYPE("vx64mem", TYPE_M64) + TYPE("vy64mem", TYPE_M64) errs() << "Unhandled type string " << s << "\n"; llvm_unreachable("Unhandled type string"); } @@ -882,13 +1118,21 @@ OperandEncoding RecognizableInstr::immediateEncodingFromString ENCODING("i16imm", ENCODING_IW) } ENCODING("i32i8imm", ENCODING_IB) + ENCODING("u32u8imm", ENCODING_IB) ENCODING("SSECC", ENCODING_IB) + ENCODING("AVXCC", ENCODING_IB) ENCODING("i16imm", ENCODING_Iv) ENCODING("i16i8imm", ENCODING_IB) ENCODING("i32imm", ENCODING_Iv) ENCODING("i64i32imm", ENCODING_ID) ENCODING("i64i8imm", ENCODING_IB) ENCODING("i8imm", ENCODING_IB) + // This is not a typo. Instructions like BLENDVPD put + // register IDs in 8-bit immediates nowadays. + ENCODING("VR256", ENCODING_IB) + ENCODING("VR128", ENCODING_IB) + ENCODING("FR32", ENCODING_IB) + ENCODING("FR64", ENCODING_IB) errs() << "Unhandled immediate encoding " << s << "\n"; llvm_unreachable("Unhandled immediate encoding"); } @@ -904,6 +1148,7 @@ OperandEncoding RecognizableInstr::rmRegisterEncodingFromString ENCODING("FR64", ENCODING_RM) ENCODING("FR32", ENCODING_RM) ENCODING("VR64", ENCODING_RM) + ENCODING("VR256", ENCODING_RM) errs() << "Unhandled R/M register encoding " << s << "\n"; llvm_unreachable("Unhandled R/M register encoding"); } @@ -922,10 +1167,24 @@ OperandEncoding RecognizableInstr::roRegisterEncodingFromString ENCODING("SEGMENT_REG", ENCODING_REG) ENCODING("DEBUG_REG", ENCODING_REG) ENCODING("CONTROL_REG", ENCODING_REG) + ENCODING("VR256", ENCODING_REG) errs() << "Unhandled reg/opcode register encoding " << s << "\n"; llvm_unreachable("Unhandled reg/opcode register encoding"); } +OperandEncoding RecognizableInstr::vvvvRegisterEncodingFromString + (const std::string &s, + bool hasOpSizePrefix) { + ENCODING("GR32", ENCODING_VVVV) + ENCODING("GR64", ENCODING_VVVV) + ENCODING("FR32", ENCODING_VVVV) + ENCODING("FR64", ENCODING_VVVV) + ENCODING("VR128", ENCODING_VVVV) + ENCODING("VR256", ENCODING_VVVV) + errs() << "Unhandled VEX.vvvv register encoding " << s << "\n"; + llvm_unreachable("Unhandled VEX.vvvv register encoding"); +} + OperandEncoding RecognizableInstr::memoryEncodingFromString (const std::string &s, bool hasOpSizePrefix) { @@ -940,6 +1199,7 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString ENCODING("f64mem", ENCODING_RM) ENCODING("f32mem", ENCODING_RM) ENCODING("i128mem", ENCODING_RM) + ENCODING("i256mem", ENCODING_RM) ENCODING("f80mem", ENCODING_RM) ENCODING("lea32mem", ENCODING_RM) ENCODING("lea64_32mem", ENCODING_RM) @@ -948,6 +1208,10 @@ OperandEncoding RecognizableInstr::memoryEncodingFromString ENCODING("opaque48mem", ENCODING_RM) ENCODING("opaque80mem", ENCODING_RM) ENCODING("opaque512mem", ENCODING_RM) + ENCODING("vx32mem", ENCODING_RM) + ENCODING("vy32mem", ENCODING_RM) + ENCODING("vx64mem", ENCODING_RM) + ENCODING("vy64mem", ENCODING_RM) errs() << "Unhandled memory encoding " << s << "\n"; llvm_unreachable("Unhandled memory encoding"); } @@ -989,6 +1253,9 @@ OperandEncoding RecognizableInstr::opcodeModifierEncodingFromString ENCODING("GR64", ENCODING_RO) ENCODING("GR16", ENCODING_Rv) ENCODING("GR8", ENCODING_RB) + ENCODING("GR16_NOAX", ENCODING_Rv) + ENCODING("GR32_NOAX", ENCODING_Rv) + ENCODING("GR64_NOAX", ENCODING_RO) errs() << "Unhandled opcode modifier encoding " << s << "\n"; llvm_unreachable("Unhandled opcode modifier encoding"); }