X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FX86RecognizableInstr.cpp;h=4118293ae5677ee85a61391ecefbe8f3c77f36ec;hb=1045a594e65c65c55dfcd9585658eee85ef79e75;hp=998476954eacdaa4963944859660d099d455bd8d;hpb=f37dd02f7743ebd2424480361f5a7db510495c4f;p=oota-llvm.git diff --git a/utils/TableGen/X86RecognizableInstr.cpp b/utils/TableGen/X86RecognizableInstr.cpp index 998476954ea..4118293ae56 100644 --- a/utils/TableGen/X86RecognizableInstr.cpp +++ b/utils/TableGen/X86RecognizableInstr.cpp @@ -68,7 +68,7 @@ namespace X86Local { DC = 7, DD = 8, DE = 9, DF = 10, XD = 11, XS = 12, T8 = 13, P_TA = 14, - A6 = 15, A7 = 16 + A6 = 15, A7 = 16, TF = 17 }; } @@ -162,7 +162,7 @@ static bool isRegFormat(uint8_t form) { /// @param init - A reference to the BitsInit to be decoded. /// @return - The field, with the first bit in the BitsInit as the lowest /// order bit. -static uint8_t byteFromBitsInit(const BitsInit &init) { +static uint8_t byteFromBitsInit(BitsInit &init) { int width = init.getNumBits(); assert(width <= 8 && "Field is too large for uint8_t!"); @@ -173,7 +173,7 @@ static uint8_t byteFromBitsInit(const BitsInit &init) { uint8_t ret = 0; for (index = 0; index < width; index++) { - if (static_cast(init.getBit(index))->getValue()) + if (static_cast(init.getBit(index))->getValue()) ret |= mask; mask <<= 1; @@ -189,7 +189,7 @@ static uint8_t byteFromBitsInit(const BitsInit &init) { /// @param name - The name of the field in the record. /// @return - The field, as translated by byteFromBitsInit(). static uint8_t byteFromRec(const Record* rec, const std::string &name) { - const BitsInit* bits = rec->getValueAsBitsInit(name); + BitsInit* bits = rec->getValueAsBitsInit(name); return byteFromBitsInit(*bits); } @@ -225,15 +225,21 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, Operands = &insn.Operands.OperandList; - IsSSE = HasOpSizePrefix && (Name.find("16") == Name.npos); + IsSSE = (HasOpSizePrefix && (Name.find("16") == Name.npos)) || + (Name.find("CRC32") != Name.npos); HasFROperands = hasFROperands(); HasVEX_LPrefix = has256BitOperands() || Rec->getValueAsBit("hasVEX_L"); // Check for 64-bit inst which does not require REX + Is32Bit = false; Is64Bit = false; // FIXME: Is there some better way to check for In64BitMode? std::vector Predicates = Rec->getValueAsListOfDefs("Predicates"); for (unsigned i = 0, e = Predicates.size(); i != e; ++i) { + if (Predicates[i]->getName().find("32Bit") != Name.npos) { + Is32Bit = true; + break; + } if (Predicates[i]->getName().find("64Bit") != Name.npos) { Is64Bit = true; break; @@ -257,7 +263,7 @@ RecognizableInstr::RecognizableInstr(DisassemblerTables &tables, } void RecognizableInstr::processInstr(DisassemblerTables &tables, - const CodeGenInstruction &insn, + const CodeGenInstruction &insn, InstrUID uid) { // Ignore "asm parser only" instructions. @@ -318,11 +324,13 @@ InstructionContext RecognizableInstr::insnContext() const { else insnContext = IC_64BIT; } else { - if (HasOpSizePrefix) + if (HasOpSizePrefix && Prefix == X86Local::TF) + insnContext = IC_XD; + else if (HasOpSizePrefix) insnContext = IC_OPSIZE; else if (Prefix == X86Local::XD) insnContext = IC_XD; - else if (Prefix == X86Local::XS) + else if (Prefix == X86Local::XS || Prefix == X86Local::REP) insnContext = IC_XS; else insnContext = IC; @@ -342,20 +350,13 @@ RecognizableInstr::filter_ret RecognizableInstr::filter() const { return FILTER_STRONG; if (Form == X86Local::Pseudo || - IsCodeGenOnly) + (IsCodeGenOnly && Name.find("_REV") == Name.npos)) return FILTER_STRONG; if (Form == X86Local::MRMInitReg) return FILTER_STRONG; - // TEMPORARY pending bug fixes - - if (Name.find("VMOVDQU") != Name.npos || - Name.find("VMOVDQA") != Name.npos || - Name.find("VROUND") != Name.npos) - return FILTER_STRONG; - // Filter out artificial instructions if (Name.find("TAILJMP") != Name.npos || @@ -623,20 +624,43 @@ void RecognizableInstr::emitInstructionSpecifier(DisassemblerTables &tables) { case X86Local::MRMDestReg: // Operand 1 is a register operand in the R/M field. // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestRegFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestRegFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestRegFrm"); + HANDLE_OPERAND(rmRegister) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; case X86Local::MRMDestMem: // Operand 1 is a memory operand (possibly SIB-extended) // Operand 2 is a register operand in the Reg/Opcode field. + // - In AVX, there is a register operand in the VEX.vvvv field here - // Operand 3 (optional) is an immediate. - assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && - "Unexpected number of operands for MRMDestMemFrm"); + if (HasVEX_4VPrefix) + assert(numPhysicalOperands >= 3 && numPhysicalOperands <= 4 && + "Unexpected number of operands for MRMDestMemFrm with VEX_4V"); + else + assert(numPhysicalOperands >= 2 && numPhysicalOperands <= 3 && + "Unexpected number of operands for MRMDestMemFrm"); HANDLE_OPERAND(memory) + + if (HasVEX_4VPrefix) + // FIXME: In AVX, the register below becomes the one encoded + // in ModRMVEX and the one above the one in the VEX.VVVV field + HANDLE_OPERAND(vvvvRegister) + HANDLE_OPERAND(roRegister) HANDLE_OPTIONAL(immediate) break; @@ -805,6 +829,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { opcodeToSet = Opcode; break; case X86Local::T8: + case X86Local::TF: opcodeType = THREEBYTE_38; if (needsModRMForDecode(Form)) filter = new ModFilter(isRegFormat(Form)); @@ -855,6 +880,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { } opcodeToSet = 0xd8 + (Prefix - X86Local::D8); break; + case X86Local::REP: default: opcodeType = ONEBYTE; switch (Opcode) { @@ -926,7 +952,7 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { insnContext(), currentOpcode, *filter, - UID); + UID, Is32Bit); Spec->modifierType = MODIFIER_OPCODE; Spec->modifierBase = opcodeToSet; @@ -936,14 +962,14 @@ void RecognizableInstr::emitDecodePath(DisassemblerTables &tables) const { insnContext(), opcodeToSet, *filter, - UID); + UID, Is32Bit); } } else { tables.setTableFields(opcodeType, insnContext(), opcodeToSet, *filter, - UID); + UID, Is32Bit); Spec->modifierType = MODIFIER_NONE; Spec->modifierBase = opcodeToSet;