X-Git-Url: http://demsky.eecs.uci.edu/git/?a=blobdiff_plain;f=utils%2FTableGen%2FX86RecognizableInstr.h;h=9ec36a39df4503af5dcac60a80146bbd760f4766;hb=1b0dc64919e947bb4f4677b138c734e33061f7c4;hp=84374b000bf0131ffaf01e8fef52dfecb917c637;hpb=1087f54ddb70bd2a7ab62608161e4a3f0c345935;p=oota-llvm.git diff --git a/utils/TableGen/X86RecognizableInstr.h b/utils/TableGen/X86RecognizableInstr.h index 84374b000bf..9ec36a39df4 100644 --- a/utils/TableGen/X86RecognizableInstr.h +++ b/utils/TableGen/X86RecognizableInstr.h @@ -17,13 +17,11 @@ #ifndef X86RECOGNIZABLEINSTR_H #define X86RECOGNIZABLEINSTR_H -#include "X86DisassemblerTables.h" - #include "CodeGenTarget.h" -#include "Record.h" - -#include "llvm/System/DataTypes.h" +#include "X86DisassemblerTables.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/Support/DataTypes.h" +#include "llvm/TableGen/Record.h" namespace llvm { @@ -50,13 +48,33 @@ private: uint8_t SegOvr; /// The hasOpSizePrefix field from the record bool HasOpSizePrefix; + /// The hasAdSizePrefix field from the record + bool HasAdSizePrefix; /// The hasREX_WPrefix field from the record bool HasREX_WPrefix; + /// The hasVEXPrefix field from the record + bool HasVEXPrefix; + /// The hasVEX_4VPrefix field from the record + bool HasVEX_4VPrefix; + /// The hasVEX_4VOp3Prefix field from the record + bool HasVEX_4VOp3Prefix; + /// The hasVEX_WPrefix field from the record + bool HasVEX_WPrefix; + /// Inferred from the operands; indicates whether the L bit in the VEX prefix is set + bool HasVEX_LPrefix; + /// The hasMemOp4Prefix field from the record + bool HasMemOp4Prefix; + /// The ignoreVEX_L field from the record + bool IgnoresVEX_L; /// The hasLockPrefix field from the record bool HasLockPrefix; /// The isCodeGenOnly filed from the record bool IsCodeGenOnly; - + // Whether the instruction has the predicate "In64BitMode" + bool Is64Bit; + // Whether the instruction has the predicate "In32BitMode" + bool Is32Bit; + /// The instruction name as listed in the tables std::string Name; /// The AT&T AsmString for the instruction @@ -74,7 +92,8 @@ private: /// The operands of the instruction, as listed in the CodeGenInstruction. /// They are not one-to-one with operands listed in the MCInst; for example, /// memory operands expand to 5 operands in the MCInst - const std::vector* Operands; + const std::vector* Operands; + /// The description of the instruction that is emitted into the instruction /// info table InstructionSpecifier* Spec; @@ -93,7 +112,7 @@ private: // error if it conflcits with any other FILTER_NORMAL // instruction }; - + /// filter - Determines whether the instruction should be decodable. Some /// instructions are pure intrinsics and use unencodable operands; many /// synthetic instructions are duplicates of other instructions; other @@ -103,7 +122,10 @@ private: /// /// @return - The degree of filtering to be applied (see filter_ret). filter_ret filter() const; - + + /// hasFROperands - Returns true if any operand is a FR operand. + bool hasFROperands() const; + /// typeFromString - Translates an operand type from the string provided in /// the LLVM tables to an OperandType for use in the operand specifier. /// @@ -116,7 +138,7 @@ private: /// @param hasREX_WPrefix - Indicates whether the instruction has a REX.W /// prefix. If it does, 32-bit register operands stay /// 32-bit regardless of the operand size. - /// @param hasOpSizePrefix- Indicates whether the instruction has an OpSize + /// @param hasOpSizePrefix Indicates whether the instruction has an OpSize /// prefix. If it does not, then 16-bit register /// operands stay 16-bit. /// @return - The operand's type. @@ -152,6 +174,8 @@ private: bool hasOpSizePrefix); static OperandEncoding opcodeModifierEncodingFromString(const std::string &s, bool hasOpSizePrefix); + static OperandEncoding vvvvRegisterEncodingFromString(const std::string &s, + bool HasOpSizePrefix); /// handleOperand - Converts a single operand from the LLVM table format to /// the emitted table format, handling any duplicate operands it encounters @@ -175,7 +199,7 @@ private: unsigned &operandIndex, unsigned &physicalOperandIndex, unsigned &numPhysicalOperands, - unsigned *operandMapping, + const unsigned *operandMapping, OperandEncoding (*encodingFromString) (const std::string&, bool hasOpSizePrefix)); @@ -196,23 +220,23 @@ private: /// emitInstructionSpecifier - Loads the instruction specifier for the current /// instruction into a DisassemblerTables. /// - /// @arg tables - The DisassemblerTables to populate with the specifier for + /// \param tables The DisassemblerTables to populate with the specifier for /// the current instruction. void emitInstructionSpecifier(DisassemblerTables &tables); /// emitDecodePath - Populates the proper fields in the decode tables /// corresponding to the decode paths for this instruction. /// - /// @arg tables - The DisassemblerTables to populate with the decode + /// \param tables The DisassemblerTables to populate with the decode /// decode information for the current instruction. void emitDecodePath(DisassemblerTables &tables) const; /// Constructor - Initializes a RecognizableInstr with the appropriate fields /// from a CodeGenInstruction. /// - /// @arg tables - The DisassemblerTables that the specifier will be added to. - /// @arg insn - The CodeGenInstruction to extract information from. - /// @arg uid - The unique ID of the current instruction. + /// \param tables The DisassemblerTables that the specifier will be added to. + /// \param insn The CodeGenInstruction to extract information from. + /// \param uid The unique ID of the current instruction. RecognizableInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid); @@ -220,11 +244,11 @@ public: /// processInstr - Accepts a CodeGenInstruction and loads decode information /// for it into a DisassemblerTables if appropriate. /// - /// @arg tables - The DiassemblerTables to be populated with decode + /// \param tables The DiassemblerTables to be populated with decode /// information. - /// @arg insn - The CodeGenInstruction to be used as a source for this + /// \param insn The CodeGenInstruction to be used as a source for this /// information. - /// @uid - The unique ID of the instruction. + /// \param uid The unique ID of the instruction. static void processInstr(DisassemblerTables &tables, const CodeGenInstruction &insn, InstrUID uid);