IR: add a second ordering operand to cmpxhg for failure
authorTim Northover <tnorthover@apple.com>
Tue, 11 Mar 2014 10:48:52 +0000 (10:48 +0000)
committerTim Northover <tnorthover@apple.com>
Tue, 11 Mar 2014 10:48:52 +0000 (10:48 +0000)
commitca396e391e13d417605ebed06780d92c88f14a6b
treea984bbd50ef52c0ad3f0fd66b81d1021b072d16c
parentfb411c8b8ce42689d42b0d8e3a871d81f86a7298
IR: add a second ordering operand to cmpxhg for failure

The syntax for "cmpxchg" should now look something like:

cmpxchg i32* %addr, i32 42, i32 3 acquire monotonic

where the second ordering argument gives the required semantics in the case
that no exchange takes place. It should be no stronger than the first ordering
constraint and cannot be either "release" or "acq_rel" (since no store will
have taken place).

rdar://problem/15996804

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203559 91177308-0d34-0410-b5e6-96231b3b80d8
60 files changed:
docs/LangRef.rst
include/llvm/CodeGen/SelectionDAG.h
include/llvm/CodeGen/SelectionDAGNodes.h
include/llvm/IR/IRBuilder.h
include/llvm/IR/Instructions.h
lib/Analysis/AliasAnalysis.cpp
lib/AsmParser/LLParser.cpp
lib/AsmParser/LLParser.h
lib/Bitcode/Reader/BitcodeReader.cpp
lib/Bitcode/Writer/BitcodeWriter.cpp
lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp
lib/CodeGen/SelectionDAG/SelectionDAG.cpp
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
lib/IR/AsmWriter.cpp
lib/IR/AsmWriter.h
lib/IR/Instruction.cpp
lib/IR/Instructions.cpp
lib/IR/Verifier.cpp
lib/Target/ARM/ARMISelLowering.cpp
lib/Target/CppBackend/CPPBackend.cpp
lib/Target/X86/X86ISelLowering.cpp
lib/Transforms/IPO/MergeFunctions.cpp
lib/Transforms/Instrumentation/MemorySanitizer.cpp
lib/Transforms/Instrumentation/ThreadSanitizer.cpp
test/Assembler/atomic.ll
test/Bitcode/cmpxchg-upgrade.ll [new file with mode: 0644]
test/Bitcode/cmpxchg-upgrade.ll.bc [new file with mode: 0644]
test/Bitcode/memInstructions.3.2.ll
test/CodeGen/AArch64/atomic-ops.ll
test/CodeGen/ARM/atomic-64bit.ll
test/CodeGen/ARM/atomic-cmp.ll
test/CodeGen/ARM/atomic-ops-v8.ll
test/CodeGen/Mips/atomic.ll
test/CodeGen/Mips/atomicops.ll
test/CodeGen/PowerPC/Atomics-32.ll
test/CodeGen/PowerPC/Atomics-64.ll
test/CodeGen/PowerPC/atomic-1.ll
test/CodeGen/PowerPC/atomic-2.ll
test/CodeGen/SPARC/atomics.ll
test/CodeGen/SystemZ/cmpxchg-01.ll
test/CodeGen/SystemZ/cmpxchg-02.ll
test/CodeGen/SystemZ/cmpxchg-03.ll
test/CodeGen/SystemZ/cmpxchg-04.ll
test/CodeGen/X86/2010-10-08-cmpxchg8b.ll
test/CodeGen/X86/Atomics-64.ll
test/CodeGen/X86/atomic16.ll
test/CodeGen/X86/atomic32.ll
test/CodeGen/X86/atomic64.ll
test/CodeGen/X86/atomic6432.ll
test/CodeGen/X86/atomic8.ll
test/CodeGen/X86/atomic_op.ll
test/CodeGen/X86/cmpxchg16b.ll
test/CodeGen/X86/coalescer-remat.ll
test/CodeGen/X86/nocx16.ll
test/Instrumentation/AddressSanitizer/test64.ll
test/Instrumentation/MemorySanitizer/atomics.ll
test/Instrumentation/ThreadSanitizer/atomic.ll
test/Transforms/LowerAtomic/atomic-swap.ll
test/Transforms/SimplifyCFG/trapping-load-unreachable.ll