While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and...
authorKit Barton <kbarton@ca.ibm.com>
Thu, 5 Mar 2015 16:24:38 +0000 (16:24 +0000)
committerKit Barton <kbarton@ca.ibm.com>
Thu, 5 Mar 2015 16:24:38 +0000 (16:24 +0000)
commitb98636a0f89c6887c852e6a9e4670b2dfbcbce23
treeed83ae1fe87233eb510e7de5f2f2a7b41bc954c9
parent684d323b9be58d1afaa9178661cc510035e114f8
While reviewing the changes to Clang to add builtin support for the vsld, vsrd, and vsrad instructions, it was pointed out that the builtins are generating the LLVM opcodes (shl, lshr, and ashr) not calls to the intrinsics. This patch changes the implementation of the vsld, vsrd, and vsrad instructions from from intrinsics to VXForm_1 instructions and makes them legal with P8 Altivec. It also removes the definition of the int_ppc_altivec_vsld, int_ppc_altivec_vsrd, and int_ppc_altivec_vsrad intrinsics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@231378 91177308-0d34-0410-b5e6-96231b3b80d8
include/llvm/IR/IntrinsicsPowerPC.td
lib/Target/PowerPC/PPCISelLowering.cpp
lib/Target/PowerPC/PPCInstrAltivec.td
test/CodeGen/PowerPC/vec_rotate_shift.ll