UPSTREAM: PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"

UPSTREAM: PCI: rockchip: Disable RC's ASPM L0s based on DT "aspm-no-l0s"

Rockchip's RC produces a 100MHz reference clock but there are two
methods for the PHY to generate it:

(1) Use the system PLL to generate a 100MHz clock.  The PHY will relock
    it, filter signal noise, and output the reference clock.  ASPM L0s
    works correctly, but circuit noise issues make it difficult to pass
    the TX compatibility test.

(2) Share the SoC's 24MHZ crystal oscillator with the PHY and force the
    PHY's PLL to generate 100MHz internally.  In this case, exit from
    ASPM L0s sometimes fails due to a design error in the RC receiver
    circuit.  Even if we use extended-synch, the PHY sometimes fails to
    relock the bits from FTS, which will hang the system.

We want the flexibility to use both clocking methods, so add a DT
property, "aspm-no-l0s".  If that's present, disable L0s to avoid the
issues with case (2).

Change-Id: Iefbac055dc9d916815aace25f3558e0642e3522b
[bhelgaas: changelog]
Reported-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
Reviewed-by: Brian Norris <briannorris@chromium.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
(cherry picked from git.kernel.org/cgit/linux/kernel/git/helgaas/pci.git
commit afc9595ea4770f0157ae06fb3acedff703e169b6)