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(parent: 7cf9764) | patch
When using CR bit registers on PPC32, handle the i1 vaarg case
authorHal Finkel <hfinkel@anl.gov>
Thu, 6 Mar 2014 00:23:33 +0000 (00:23 +0000)
committerHal Finkel <hfinkel@anl.gov>
Thu, 6 Mar 2014 00:23:33 +0000 (00:23 +0000)
commit025c1cefca00f262452c8c42717a4047b1836cd2
tree1990aa14403fa135fa0b928ebc83ecd954cc14fftree | snapshot
parent7cf97649660c15c81ce7dfdd4eed564297e15bdecommit | diff
When using CR bit registers on PPC32, handle the i1 vaarg case

When copying an i1 value into a GPR for a vaarg call, we need to explicitly
zero-extend the i1 value (otherwise an invalid CRBIT -> GPR copy will be
generated).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203041 91177308-0d34-0410-b5e6-96231b3b80d8
lib/Target/PowerPC/PPCISelLowering.cpp diff | blob | history
test/CodeGen/PowerPC/ppc32-i1-vaarg.ll [new file with mode: 0644] blob
C/C++ LLVM-based compilers that forbids OOTA behaviors