serial: tegra_hsuart: fix receive DMA, RTS, timeout, and tx trigger

serial: tegra_hsuart: fix receive DMA, RTS, timeout, and tx trigger

initialize baud rate and configuration settings to safe default values
when receive DMA is in use, so that the DMA request may be enqueued at
initialization time

re-enqueue the receive DMA buffer immediately it is dequeued by the
DMA threshold callback and the receive ISR, rather than waiting for the
DMA complete callback

originally fixed by Gary King <gking@nvidia.com>

Fixing tx trigger level setting:

On tegra uart, the FCR setting for different tx trigger level
is not same as the 16550 tx trigger level setting. The tegra
uart have the setting in reverse direction on tx fifo attention
level:
b00 for 16 bytes attention level.
b01 for 8 byte attention level.
b10 for 4 byte attention level
b11 for 1 byte attention level.

The rx trigger attention level match with the standard uart
FCR register setttings.

Also fixing the typo in code when setting DTR.
originally fixed by Laxman Dewangan (ldewangan@nvidia.com)

Change-Id: Iea00478f143e61c604828035c6c92d614fa7cccb
Signed-off-by: Jay Cheng <jacheng@nvidia.com>